From: sashiko-bot@kernel.org
To: "Sascha Bischoff" <Sascha.Bischoff@arm.com>
Cc: "Oliver Upton" <oupton@kernel.org>,
"Marc Zyngier" <maz@kernel.org>,
kvmarm@lists.linux.dev, kvm@vger.kernel.org
Subject: Re: [PATCH v6 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state
Date: Fri, 04 Sep 2026 13:05:56 +0000 [thread overview]
Message-ID: <20260904130556.A8CFD1F01564@smtp.kernel.org> (raw)
In-Reply-To: <20260904113404.4051341-24-sascha.bischoff@arm.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Skipping the doorbell request when the IRS is disabled breaks vSGI wakeups and causes a KVM blocked-state deadlock when the IRS is re-enabled.
--
commit 614bfb31d4f0af06eb90b62b9d08cfb10894ae32
Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state
This commit uses the GICv5 ICH_CONTEXTR_EL2 IRICHPPIDIS field to emulate the
guest enabling and disabling the IRS. It programs IRICHPPIDIS when loading a
VPE and skips calculating the doorbell priority mask and requesting a doorbell
when a VPE enters WFI with a disabled IRS.
> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index bdf06dbff4231..5a5abf51d4ddd 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
[ ... ]
> @@ -1101,7 +1103,10 @@ void vgic_v5_put(struct kvm_vcpu *vcpu)
> kvm_call_hyp(__vgic_v5_save_apr, cpu_if);
>
> cpu_if->vgic_contextr = 0;
> - if (vcpu_get_flag(vcpu, IN_WFI)) {
> +
> + /* Request a doorbell if entering WFI, unless the IRS is disabled */
> + if (vcpu_get_flag(vcpu, IN_WFI) &&
> + READ_ONCE(vcpu->kvm->arch.vgic.enabled)) {
[Severity: High]
Does skipping the doorbell request when the IRS is disabled break vSGI wakeups
and cause a KVM blocked-state deadlock when the IRS is re-enabled?
If a guest disables the IRS (setting vgic.enabled = false) and a VCPU
executes WFI, vgic_v5_put() will skip requesting the hardware doorbell.
If another VCPU sends a vSGI to this sleeping VCPU, the hardware cannot
assert a doorbell to wake the physical CPU, so the vSGI is ignored.
Furthermore, if another VCPU later re-enables the IRS, KVM sets
KVM_REQ_RELOAD_GICv5 and kicks the sleeping VCPU. The VCPU thread wakes up in
kvm_vcpu_block(), but because KVM_REQ_RELOAD_GICv5 does not set
KVM_REQ_UNBLOCK and does not make kvm_arch_vcpu_runnable() return true
(as db_fired is false), kvm_vcpu_check_block() returns 0. The VCPU thread
goes right back to sleep without processing the request or re-requesting a
doorbell, resulting in a permanent hang.
> u32 priority_mask;
> int dbpm;
>
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260904113404.4051341-1-sascha.bischoff@arm.com?part=23
next prev parent reply other threads:[~2026-09-04 13:05 UTC|newest]
Thread overview: 74+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 11:34 [PATCH v6 00/49] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-09-04 11:34 ` [PATCH v6 01/49] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 02/49] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-09-04 12:07 ` sashiko-bot
2026-09-04 12:16 ` Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 05/49] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-09-04 12:14 ` sashiko-bot
2026-09-04 12:21 ` Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 07/49] KVM: arm64: gic-v5: Cache host IRS ID registers Sascha Bischoff
2026-09-04 12:25 ` sashiko-bot
2026-09-04 12:37 ` Sascha Bischoff
2026-09-04 11:38 ` [PATCH v6 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-09-04 12:26 ` sashiko-bot
2026-09-04 11:38 ` [PATCH v6 09/49] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-09-04 12:24 ` sashiko-bot
2026-09-04 11:39 ` [PATCH v6 10/49] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-09-04 12:30 ` sashiko-bot
2026-09-04 11:39 ` [PATCH v6 11/49] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-09-04 12:39 ` sashiko-bot
2026-09-04 11:40 ` [PATCH v6 12/49] KVM: arm64: vgic: Enforce model-specific vCPU limits Sascha Bischoff
2026-09-04 11:40 ` [PATCH v6 13/49] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-09-04 12:36 ` sashiko-bot
2026-09-04 11:41 ` [PATCH v6 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-09-04 12:50 ` sashiko-bot
2026-09-04 11:41 ` [PATCH v6 15/49] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-09-04 12:42 ` sashiko-bot
2026-09-04 11:42 ` [PATCH v6 16/49] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-09-04 13:08 ` sashiko-bot
2026-09-04 11:42 ` [PATCH v6 17/49] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 18/49] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-09-04 11:44 ` [PATCH v6 20/49] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-09-04 12:59 ` sashiko-bot
2026-09-04 11:44 ` [PATCH v6 21/49] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-09-04 13:00 ` sashiko-bot
2026-09-04 11:45 ` [PATCH v6 22/49] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-09-04 13:10 ` sashiko-bot
2026-09-04 11:45 ` [PATCH v6 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-09-04 13:05 ` sashiko-bot [this message]
2026-09-04 11:46 ` [PATCH v6 24/49] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-09-04 11:46 ` [PATCH v6 25/49] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 26/49] KVM: arm64: gic: Introduce set_pending_state() to irq_ops Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 27/49] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-09-04 11:48 ` [PATCH v6 28/49] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-09-04 13:25 ` sashiko-bot
2026-09-04 11:49 ` [PATCH v6 29/49] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-09-04 11:49 ` [PATCH v6 30/49] KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-09-04 11:50 ` [PATCH v6 31/49] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-09-04 13:27 ` sashiko-bot
2026-09-04 11:50 ` [PATCH v6 32/49] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-09-04 13:34 ` sashiko-bot
2026-09-04 11:51 ` [PATCH v6 33/49] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-09-04 11:51 ` [PATCH v6 34/49] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-09-04 11:52 ` [PATCH v6 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-09-04 13:45 ` sashiko-bot
2026-09-04 11:52 ` [PATCH v6 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 37/49] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 38/49] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 39/49] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 40/49] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 41/49] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 42/49] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 43/49] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 44/49] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 45/49] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 46/49] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-09-04 11:58 ` [PATCH v6 47/49] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-09-04 13:56 ` sashiko-bot
2026-09-04 11:58 ` [PATCH v6 48/49] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
2026-09-04 13:58 ` sashiko-bot
2026-09-04 11:59 ` [PATCH v6 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test Sascha Bischoff
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260904130556.A8CFD1F01564@smtp.kernel.org \
--to=sashiko-bot@kernel.org \
--cc=Sascha.Bischoff@arm.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=maz@kernel.org \
--cc=oupton@kernel.org \
--cc=sashiko-reviews@lists.linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox