Re: [PATCH 03/15] MIPS: OCTEON: Move CAVIUM_OCTEON_CVMSEG_SIZE to CPU_CAVIUM_OCTEON

[James Hogan <james.hogan@imgtec.com>]

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Hi Andreas,

On Tuesday 20 May 2014 16:47:04 Andreas Herrmann wrote:
> From: David Daney <david.daney@cavium.com>
> 
> CVMSEG is related to the CPU core not the SoC system.  So needs to be
> configurable there.
> 
> Signed-off-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
> ---
>  arch/mips/cavium-octeon/Kconfig |   30 ++++++++++++++++++++----------
>  1 file changed, 20 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/mips/cavium-octeon/Kconfig
> b/arch/mips/cavium-octeon/Kconfig index 227705d..c5e9975 100644
> --- a/arch/mips/cavium-octeon/Kconfig
> +++ b/arch/mips/cavium-octeon/Kconfig
> @@ -10,6 +10,17 @@ config CAVIUM_CN63XXP1
>  	  non-CN63XXP1 hardware, so it is recommended to select "n"
>  	  unless it is known the workarounds are needed.
> 
> +config CAVIUM_OCTEON_CVMSEG_SIZE
> +	int "Number of L1 cache lines reserved for CVMSEG memory"
> +	range 0 54
> +	default 1
> +	help
> +	  CVMSEG LM is a segment that accesses portions of the dcache as a
> +	  local memory; the larger CVMSEG is, the smaller the cache is.
> +	  This selects the size of CVMSEG LM, which is in cache blocks. The
> +	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
> +	  between zero and 6192 bytes).
> +
>  endif # CPU_CAVIUM_OCTEON
> 
>  if CAVIUM_OCTEON_SOC
> @@ -23,16 +34,16 @@ config CAVIUM_OCTEON_2ND_KERNEL
>  	  with this option to be run at the same time as one built without this
>  	  option.
> 
> -config CAVIUM_OCTEON_CVMSEG_SIZE
> -	int "Number of L1 cache lines reserved for CVMSEG memory"
> -	range 0 54
> -	default 1
> +config CAVIUM_OCTEON_HW_FIX_UNALIGNED
> +	bool "Enable hardware fixups of unaligned loads and stores"
> +	default "y"

Is adding CAVIUM_OCTEON_HW_FIX_UNALIGNED in this patch intentional? It seems 
unrelated.

Cheers
James

>  	help
> -	  CVMSEG LM is a segment that accesses portions of the dcache as a
> -	  local memory; the larger CVMSEG is, the smaller the cache is.
> -	  This selects the size of CVMSEG LM, which is in cache blocks. The
> -	  legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
> -	  between zero and 6192 bytes).
> +	  Configure the Octeon hardware to automatically fix unaligned loads
> +	  and stores. Normally unaligned accesses are fixed using a kernel
> +	  exception handler. This option enables the hardware automatic fixups,
> +	  which requires only an extra 3 cycles. Disable this option if you
> +	  are running code that relies on address exceptions on unaligned
> +	  accesses.
> 
>  config CAVIUM_OCTEON_LOCK_L2
>  	bool "Lock often used kernel code in the L2"
> @@ -86,7 +97,6 @@ config SWIOTLB
>  	select IOMMU_HELPER
>  	select NEED_SG_DMA_LENGTH
> 
> -
>  config OCTEON_ILM
>  	tristate "Module to measure interrupt latency using Octeon CIU Timer"
>  	help

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