From: Liam Merwick <liam.merwick@oracle.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>
Cc: kvm@vger.kernel.org, Dapeng Mi <dapeng1.mi@linux.intel.com>,
liam.merwick@oracle.com
Subject: Re: [kvm-unit-tests PATCH v2 14/14] x86: Move SEV MSR definitions to msr.h
Date: Wed, 11 Jun 2025 16:41:21 +0100 [thread overview]
Message-ID: <47906f80-d896-4839-bb31-2d3fcd876db9@oracle.com> (raw)
In-Reply-To: <20250610195415.115404-15-seanjc@google.com>
On 10/06/2025 20:54, Sean Christopherson wrote:
> Move the SEV MSR definitions to msr.h so that they're available for non-EFI
> builds. There is nothing EFI specific about the architectural definitions.
>
> Opportunistically massage the names to align with existing style.
>
> No functional change intended.
>
> Signed-off-by: Sean Christopherson <seanjc@google.com>
> ---
> lib/x86/amd_sev.c | 6 +++---
> lib/x86/amd_sev.h | 14 --------------
> lib/x86/msr.h | 6 ++++++
> 3 files changed, 9 insertions(+), 17 deletions(-)
>
> diff --git a/lib/x86/amd_sev.c b/lib/x86/amd_sev.c
> index da0e2077..7c6d2804 100644
> --- a/lib/x86/amd_sev.c
> +++ b/lib/x86/amd_sev.c
Maybe msr.h should be explicitly #included?
either way
Reviewed-by: Liam Merwick <liam.merwick@oracle.com>
> @@ -25,7 +25,7 @@ bool amd_sev_enabled(void)
> initialized = true;
>
> sev_enabled = this_cpu_has(X86_FEATURE_SEV) &&
> - rdmsr(MSR_SEV_STATUS) & SEV_ENABLED_MASK;
> + rdmsr(MSR_SEV_STATUS) & SEV_STATUS_SEV_ENABLED;
> }
>
> return sev_enabled;
> @@ -52,7 +52,7 @@ bool amd_sev_es_enabled(void)
>
> sev_es_enabled = amd_sev_enabled() &&
> this_cpu_has(X86_FEATURE_SEV_ES) &&
> - rdmsr(MSR_SEV_STATUS) & SEV_ES_ENABLED_MASK;
> + rdmsr(MSR_SEV_STATUS) & SEV_STATUS_SEV_ES_ENABLED;
> }
>
> return sev_es_enabled;
> @@ -100,7 +100,7 @@ void setup_ghcb_pte(pgd_t *page_table)
> pteval_t *pte;
>
> /* Read the current GHCB page addr */
> - ghcb_addr = rdmsr(SEV_ES_GHCB_MSR_INDEX);
> + ghcb_addr = rdmsr(MSR_SEV_ES_GHCB);
>
> /* Search Level 1 page table entry for GHCB page */
> pte = get_pte_level(page_table, (void *)ghcb_addr, 1);
> diff --git a/lib/x86/amd_sev.h b/lib/x86/amd_sev.h
> index daa33a05..9d587e2d 100644
> --- a/lib/x86/amd_sev.h
> +++ b/lib/x86/amd_sev.h
> @@ -19,23 +19,9 @@
> #include "asm/page.h"
> #include "efi.h"
>
> -/*
> - * AMD Programmer's Manual Volume 2
> - * - Section "SEV_STATUS MSR"
> - */
> -#define MSR_SEV_STATUS 0xc0010131
> -#define SEV_ENABLED_MASK 0b1
> -#define SEV_ES_ENABLED_MASK 0b10
> -
> bool amd_sev_enabled(void);
> efi_status_t setup_amd_sev(void);
>
> -/*
> - * AMD Programmer's Manual Volume 2
> - * - Section "GHCB"
> - */
> -#define SEV_ES_GHCB_MSR_INDEX 0xc0010130
> -
> bool amd_sev_es_enabled(void);
> efi_status_t setup_amd_sev_es(void);
> void setup_ghcb_pte(pgd_t *page_table);
> diff --git a/lib/x86/msr.h b/lib/x86/msr.h
> index 658d237f..ccfd6bdd 100644
> --- a/lib/x86/msr.h
> +++ b/lib/x86/msr.h
> @@ -523,4 +523,10 @@
> #define MSR_VM_IGNNE 0xc0010115
> #define MSR_VM_HSAVE_PA 0xc0010117
>
> +#define MSR_SEV_STATUS 0xc0010131
> +#define SEV_STATUS_SEV_ENABLED BIT(0)
> +#define SEV_STATUS_SEV_ES_ENABLED BIT(1)
> +
> +#define MSR_SEV_ES_GHCB 0xc0010130
> +
> #endif /* _X86_MSR_H_ */
next prev parent reply other threads:[~2025-06-11 15:41 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-10 19:54 [kvm-unit-tests PATCH v2 00/14] x86: Add CPUID properties, clean up related code Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 01/14] x86: Encode X86_FEATURE_* definitions using a structure Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 02/14] x86: Add X86_PROPERTY_* framework to retrieve CPUID values Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 03/14] x86: Use X86_PROPERTY_MAX_VIRT_ADDR in is_canonical() Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 04/14] x86: Implement get_supported_xcr0() using X86_PROPERTY_SUPPORTED_XCR0_{LO,HI} Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 05/14] x86: Add and use X86_PROPERTY_INTEL_PT_NR_RANGES Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 06/14] x86/pmu: Mark all arch events as available on AMD, and rename fields Sean Christopherson
2025-06-11 1:32 ` Mi, Dapeng
2025-06-11 12:02 ` Liam Merwick
2025-06-13 6:24 ` Sandipan Das
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 07/14] x86/pmu: Mark Intel architectural event available iff X <= CPUID.0xA.EAX[31:24] Sean Christopherson
2025-06-11 1:35 ` Mi, Dapeng
2025-06-11 12:10 ` Liam Merwick
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 08/14] x86/pmu: Use X86_PROPERTY_PMU_* macros to retrieve PMU information Sean Christopherson
2025-06-13 6:25 ` Sandipan Das
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 09/14] x86/sev: Use VC_VECTOR from processor.h Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 10/14] x86/sev: Skip the AMD SEV test if SEV is unsupported/disabled Sean Christopherson
2025-06-11 12:28 ` Liam Merwick
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 11/14] x86/sev: Define and use X86_FEATURE_* flags for CPUID 0x8000001F Sean Christopherson
2025-06-11 12:38 ` Liam Merwick
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 12/14] x86/sev: Use X86_PROPERTY_SEV_C_BIT to get the AMD SEV C-bit location Sean Christopherson
2025-06-11 12:58 ` Liam Merwick
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 13/14] x86/sev: Use amd_sev_es_enabled() to detect if SEV-ES is enabled Sean Christopherson
2025-06-10 19:54 ` [kvm-unit-tests PATCH v2 14/14] x86: Move SEV MSR definitions to msr.h Sean Christopherson
2025-06-11 15:41 ` Liam Merwick [this message]
2025-06-25 22:25 ` [kvm-unit-tests PATCH v2 00/14] x86: Add CPUID properties, clean up related code Sean Christopherson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=47906f80-d896-4839-bb31-2d3fcd876db9@oracle.com \
--to=liam.merwick@oracle.com \
--cc=dapeng1.mi@linux.intel.com \
--cc=kvm@vger.kernel.org \
--cc=pbonzini@redhat.com \
--cc=seanjc@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox