[PATCH resend v5 0/6] KVM: nVMX: Enable nested apicv support

[PATCH resend v5 0/6] KVM: nVMX: Enable nested apicv support

[Wincy Van]

v1 ---> v2:
  Use spin lock to ensure vmcs12 is safe when doing nested
  posted interrupt delivery.

v2 ---> v3:
  1. Add a new field in nested_vmx to avoid the spin lock in v2.
  2. Drop send eoi to L1 when doing nested interrupt delivery.
  3. Use hardware MSR bitmap to enable nested virtualize x2apic
     mode.

v3 ---> v4:
  1. Optimize nested msr bitmap merging.
  2. Allocate nested msr bitmap only when nested == 1.
  3. Inline the nested vmx control checking functions.

v4 ---> v5:
  1. Move EXIT_REASON_APIC_WRITE to the apic register
     virtualization patch.
  2. Accomplish nested posted interrupts manually if
     they are not recognized by hardware.

Wincy Van (6):
  KVM: nVMX: Use hardware MSR bitmap
  KVM: nVMX: Enable nested virtualize x2apic mode
  KVM: nVMX: Make nested control MSRs per-cpu
  KVM: nVMX: Enable nested apic register virtualization
  KVM: nVMX: Enable nested virtual interrupt delivery
  KVM: nVMX: Enable nested posted interrupt processing

 arch/x86/kvm/lapic.c |   13 +-
 arch/x86/kvm/lapic.h |    1 +
 arch/x86/kvm/vmx.c   |  647 ++++++++++++++++++++++++++++++++++++++++++--------
 3 files changed, 557 insertions(+), 104 deletions(-)

Re: [PATCH resend v5 0/6] KVM: nVMX: Enable nested apicv support

[Paolo Bonzini]

On 03/02/2015 16:46, Wincy Van wrote:
> v1 ---> v2:
>   Use spin lock to ensure vmcs12 is safe when doing nested
>   posted interrupt delivery.
> 
> v2 ---> v3:
>   1. Add a new field in nested_vmx to avoid the spin lock in v2.
>   2. Drop send eoi to L1 when doing nested interrupt delivery.
>   3. Use hardware MSR bitmap to enable nested virtualize x2apic
>      mode.
> 
> v3 ---> v4:
>   1. Optimize nested msr bitmap merging.
>   2. Allocate nested msr bitmap only when nested == 1.
>   3. Inline the nested vmx control checking functions.
> 
> v4 ---> v5:
>   1. Move EXIT_REASON_APIC_WRITE to the apic register
>      virtualization patch.
>   2. Accomplish nested posted interrupts manually if
>      they are not recognized by hardware.

Thanks, will apply soon to kvm/queue.

Paolo

> Wincy Van (6):
>   KVM: nVMX: Use hardware MSR bitmap
>   KVM: nVMX: Enable nested virtualize x2apic mode
>   KVM: nVMX: Make nested control MSRs per-cpu
>   KVM: nVMX: Enable nested apic register virtualization
>   KVM: nVMX: Enable nested virtual interrupt delivery
>   KVM: nVMX: Enable nested posted interrupt processing
> 
>  arch/x86/kvm/lapic.c |   13 +-
>  arch/x86/kvm/lapic.h |    1 +
>  arch/x86/kvm/vmx.c   |  647 ++++++++++++++++++++++++++++++++++++++++++--------
>  3 files changed, 557 insertions(+), 104 deletions(-)
> 
> --
> To unsubscribe from this list: send the line "unsubscribe kvm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 

Re: [PATCH resend v5 0/6] KVM: nVMX: Enable nested apicv support

[Wincy Van]

On Wed, Feb 4, 2015 at 12:15 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
>
> On 03/02/2015 16:46, Wincy Van wrote:
>> v1 ---> v2:
>>   Use spin lock to ensure vmcs12 is safe when doing nested
>>   posted interrupt delivery.
>>
>> v2 ---> v3:
>>   1. Add a new field in nested_vmx to avoid the spin lock in v2.
>>   2. Drop send eoi to L1 when doing nested interrupt delivery.
>>   3. Use hardware MSR bitmap to enable nested virtualize x2apic
>>      mode.
>>
>> v3 ---> v4:
>>   1. Optimize nested msr bitmap merging.
>>   2. Allocate nested msr bitmap only when nested == 1.
>>   3. Inline the nested vmx control checking functions.
>>
>> v4 ---> v5:
>>   1. Move EXIT_REASON_APIC_WRITE to the apic register
>>      virtualization patch.
>>   2. Accomplish nested posted interrupts manually if
>>      they are not recognized by hardware.
>
> Thanks, will apply soon to kvm/queue.
>

Thanks a lot for your review, Paolo and Yang!

Wincy