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From: Marc Zyngier <maz@kernel.org>
To: sashiko-reviews@lists.linux.dev
Cc: kvmarm@lists.linux.dev, "Oliver Upton" <oupton@kernel.org>,
	kvm@vger.kernel.org
Subject: Re: [PATCH 27/28] KVM: arm64: Expose FEAT_NV3 to guests
Date: Thu, 02 Jul 2026 21:01:21 +0100	[thread overview]
Message-ID: <87qzll6u0e.wl-maz@kernel.org> (raw)
In-Reply-To: <20260702163903.852691F00A3E@smtp.kernel.org>

On Thu, 02 Jul 2026 17:39:02 +0100,
sashiko-bot@kernel.org wrote:
> 
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> 
> Pre-existing issues:
> - [Critical] A maliciously or incorrectly configured vCPU can trigger a host NULL pointer dereference by requesting an ID register configuration where NV_frac = 0, causing KVM to skip VNCR TLB allocation while still trapping VNCR accesses.
> --
> 
> commit ca23c995d48d1c5c8370918930aa81e2eeb147ab
> Author: Marc Zyngier <maz@kernel.org>
> 
> KVM: arm64: Expose FEAT_NV3 to guests
> 
> Further enable FEAT_NV3 by making it visible to NV guests.
> 
> > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
> > index c9bf04944f9cb..64c8fb82fadf6 100644
> > --- a/arch/arm64/kvm/nested.c
> > +++ b/arch/arm64/kvm/nested.c
> > @@ -1728,7 +1728,7 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
> >  		 * You get EITHER
> >  		 *
> >  		 * - FEAT_VHE without FEAT_E2H0
> > -		 * - FEAT_NV limited to FEAT_NV2(p1)
> > +		 * - FEAT_NV limited to FEAT_NV2(p1)/NV3
> >  		 * - HCR_EL2.NV1 being RES0
> >  		 *
> >  		 * OR
> > @@ -1740,7 +1740,9 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val)
> >  		if (test_bit(KVM_ARM_VCPU_HAS_EL2_E2H0, kvm->arch.vcpu_features)) {
> >  			val = 0;
> 
> [Severity: Critical]
> This is a pre-existing issue, but could this cause a host NULL pointer
> dereference?
> 
> If userspace configures a vCPU with KVM_ARM_VCPU_HAS_EL2_E2H0, this branch
> forces the entire ID_AA64MMFR4_EL1 register to 0. This includes the NV_frac
> field. Alternatively, userspace could explicitly set ID_AA64MMFR4_EL1.NV_frac
> to 0 via KVM's ID register UAPI.
> 
> When KVM initializes the nested vCPU, it calls kvm_vcpu_allocate_vncr_tlb()
> which checks NV_frac:
> 
> arch/arm64/kvm/nested.c:kvm_vcpu_allocate_vncr_tlb() {
>         if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY))
>                 return 0;
>         ...
> }
> 
> Because NV_frac is 0, the check evaluates to false and the function silently
> returns success without allocating vcpu->arch.vncr_tlb.
> 
> Since vcpu_has_nv() only checks for KVM_ARM_VCPU_HAS_EL2, the vCPU is allowed
> to run. If the guest then accesses a VNCR-trapped register or sets HCR_EL2.NV,

Beeeeeeeep!!!! It looked so good until then...

"VNCR-trapped register" means nothing, as the whole point of VNCR is
to *not* trap, but to write to memory instead. So OK, the page isn't
there, and a write to a register targeting VNCR_EL2 could generate a
fault.

But if ID_AA64MMFR4_EL1.NV_frac==0, then HCR_EL2.NV is RES0:

	NEEDS_FEAT(HCR_EL2_AT		| /* Ignore the original FEAT_NV */
		   HCR_EL2_NV2		|
		   HCR_EL2_NV,
		   feat_nv2),

and feat_nv2 reads:

static bool feat_nv2(struct kvm *kvm)
{
	return ((kvm_has_feat(kvm, ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) &&
		 kvm_has_feat_enum(kvm, ID_AA64MMFR2_EL1, NV, NI)) ||
		kvm_has_feat(kvm, ID_AA64MMFR2_EL1, NV, NV2));
}

which will return false in the proposed case, making HCR_EL2.NV firmly
RES0. Yes, there's a reason why I spent so much time on this crap.

Since HCR_EL2.NV is RES0, we never ERET to an L2 running at EL2, and
therefore there is never a case where we fault on a guest provided
VNCR page.

> the host exit handler calls kvm_translate_vncr() or kvm_map_l1_vncr(). Both
> functions unconditionally dereference the unallocated vncr_tlb:
> 
> arch/arm64/kvm/nested.c:kvm_translate_vncr() {
>         struct vncr_tlb *vt = vcpu->arch.vncr_tlb;
>         ...
>         vt->valid = false;
>         ...
> }
> 
> Will this lead to a kernel panic when unprivileged userspace configures a
> vCPU this way?

Don't think so.

	M.

-- 
Jazz isn't dead. It just smells funny.

  reply	other threads:[~2026-07-02 19:59 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-02 16:02 [PATCH 00/28] KVM: arm64: Add support for FEAT_NV2p1 and FEAT_NV3 Marc Zyngier
2026-07-02 16:02 ` [PATCH 01/28] arm64: sysreg: Emit RESx/UNKN values for Mapping definitions Marc Zyngier
2026-07-02 16:19   ` sashiko-bot
2026-07-02 17:41     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 02/28] arm64: Update ID_AA64MMFR4_EL1 description to 2026-03 JSON release Marc Zyngier
2026-07-02 16:02 ` [PATCH 03/28] KVM: arm64: Merge guest's HCRX_EL2 using NV_HCRX_GUEST_EXCLUDE Marc Zyngier
2026-07-02 16:34   ` sashiko-bot
2026-07-02 18:29     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 04/28] KVM: arm64: Drop __HCRX_EL2_* masks Marc Zyngier
2026-07-02 18:34   ` sashiko-bot
2026-07-02 21:10     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 05/28] KVM: arm64: Plumb HCRX_EL2.SRMASKEn in HCRX_EL2 sanitisation Marc Zyngier
2026-07-02 16:28   ` sashiko-bot
2026-07-02 18:18     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 06/28] KVM: arm64: Classify CPTR_EL2 as a SR_LOC_SPECIAL register Marc Zyngier
2026-07-02 16:02 ` [PATCH 07/28] KVM: arm64: Don't evaluate HCR_EL2.NV on ERET fast path Marc Zyngier
2026-07-02 16:24   ` sashiko-bot
2026-07-02 17:57     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 08/28] arm64: Add ARM64_HAS_NV2P1 capability Marc Zyngier
2026-07-02 16:02 ` [PATCH 09/28] KVM: arm64: Relax CPTR_EL2 handling when FEAT_NV2p1 is present Marc Zyngier
2026-07-02 16:02 ` [PATCH 10/28] KVM: arm64: Relax CNTHCTL_EL2 " Marc Zyngier
2026-07-02 16:21   ` sashiko-bot
2026-07-02 17:46     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 11/28] KVM: arm64: Expose FEAT_NV2p1 to NV guests Marc Zyngier
2026-07-02 16:28   ` sashiko-bot
2026-07-02 18:23     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 12/28] arm64: Add FEAT_NV2p1 detection Marc Zyngier
2026-07-02 16:02 ` [PATCH 13/28] arm64: sysreg: Add NVHCR_EL2 description as a mirror of HCR_EL2 Marc Zyngier
2026-07-02 16:02 ` [PATCH 14/28] arm64: sysreg: Add HCRX_EL2 bits related to FEAT_NV3 Marc Zyngier
2026-07-02 16:02 ` [PATCH 15/28] arm64: Add ARM64_HAS_NV3 capability Marc Zyngier
2026-07-02 16:02 ` [PATCH 16/28] KVM: arm64: Split NV-specific exit fixups from the non-NV handling Marc Zyngier
2026-07-02 16:02 ` [PATCH 17/28] KVM: arm64: Add NV3 control bits to HCRX_EL2 sanitisation Marc Zyngier
2026-07-02 16:02 ` [PATCH 18/28] KVM: arm64: Add kvm_has_nv{2,3}() predicates Marc Zyngier
2026-07-02 16:25   ` sashiko-bot
2026-07-02 18:01     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 19/28] KVM: arm64: Make HCR_EL2 a non-VNCR register Marc Zyngier
2026-07-02 16:02 ` [PATCH 20/28] KVM: arm64: Add sanitisation for NVHCR_EL2 Marc Zyngier
2026-07-02 16:02 ` [PATCH 21/28] KVM: arm64: Add NVHCR_EL2 handling to the sysreg array Marc Zyngier
2026-07-02 16:02 ` [PATCH 22/28] KVM: arm64: Add routing for NVHCR_EL2 trap Marc Zyngier
2026-07-02 16:26   ` sashiko-bot
2026-07-02 18:14     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 23/28] KVM: arm64: Add NVHCR_EL2 context switching Marc Zyngier
2026-07-02 16:43   ` sashiko-bot
2026-07-02 20:28     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 24/28] KVM: arm64: Engage NV3 ERET trap elision Marc Zyngier
2026-07-02 16:02 ` [PATCH 25/28] KVM: arm64: Engage NV3 TLBI " Marc Zyngier
2026-07-02 16:45   ` sashiko-bot
2026-07-02 21:04     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 26/28] KVM: arm64: Add FEAT_NV3 detection Marc Zyngier
2026-07-02 16:39   ` sashiko-bot
2026-07-02 20:03     ` Marc Zyngier
2026-07-02 16:02 ` [PATCH 27/28] KVM: arm64: Expose FEAT_NV3 to guests Marc Zyngier
2026-07-02 16:39   ` sashiko-bot
2026-07-02 20:01     ` Marc Zyngier [this message]
2026-07-02 16:02 ` [PATCH 28/28] arm64: Add override for ID_AA64MMFR4_EL1.NV_frac Marc Zyngier

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