From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: Zide Chen <zide.chen@intel.com>,
Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: kvm@vger.kernel.org, Andi Kleen <ak@linux.intel.com>,
Jim Mattson <jmattson@google.com>,
Stephane Eranian <eranian@google.com>,
linux-kernel@vger.kernel.org, Mingwei Zhang <mizhang@google.com>,
Das Sandipan <Sandipan.Das@amd.com>,
Shukla Manali <Manali.Shukla@amd.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: Re: [PATCH v2 14/16] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set
Date: Tue, 1 Sep 2026 16:01:11 +0800 [thread overview]
Message-ID: <89e1cb41-81b6-4f20-9fc2-d436dd77d988@linux.intel.com> (raw)
In-Reply-To: <20260827223755.143247-15-zide.chen@intel.com>
Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
On 8/28/2026 6:37 AM, Zide Chen wrote:
> Intel PerfMon v5 introduces the ANYTHREAD_DEPRECATION capability
> (CPUID.0AH:EDX[15]) to indicate that AnyThread counting is deprecated
> and that writes to the AnyThread bit in IA32_PERFEVTSELx are ignored.
>
> When ANYTHREAD_DEPRECATION is present in the guest CPUID, emulate the
> architectural behavior and silently ignore writes to the AnyThread bit
> instead of injecting #GP.
>
> Continue to inject #GP when ANYTHREAD_DEPRECATION is not present in the
> guest CPUID, e.g. for PerfMon v3/v4 guests or when the capability is
> not configured for a PerfMon v5+ guest.
>
> Advertise CPUID.0AH:EDX[15] only for PMU version 5+ guests, since the
> bit doesn't exist below version 5.
>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
> v2:
> - Advertise anythread_deprecated only if kvm_pmu_cap.version >= 5.
> - Add the missing AnyThr bit handling for IA32_FIXED_CTR_CTRL.
> - Update the comments to be clearer.
> ---
> arch/x86/kvm/cpuid.c | 2 +-
> arch/x86/kvm/vmx/pmu_intel.c | 19 +++++++++++++++++++
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 63201d4ea4a1..ef208906b3ee 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -1542,7 +1542,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
> KVM_MAX_NR_FIXED_COUNTERS);
> edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed;
>
> - if (kvm_pmu_cap.version)
> + if (kvm_pmu_cap.version >= 5)
> edx.split.anythread_deprecated = 1;
>
> entry->eax = eax.full;
> diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
> index c7472778137a..599c69dfa6e3 100644
> --- a/arch/x86/kvm/vmx/pmu_intel.c
> +++ b/arch/x86/kvm/vmx/pmu_intel.c
> @@ -446,6 +446,12 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> if (data & pmu->fixed_ctr_ctrl_rsvd)
> return 1;
>
> + /*
> + * This is to emulate ANYTHREAD_DEPRECATION. Guests without
> + * support for it would have had the write rejected by
> + * pmu->fixed_ctr_ctrl_rsvd above.
> + */
> + data &= ~intel_pmu_fixed_ctrl_bits(pmu, INTEL_FIXED_0_ANYTHREAD);
> if (pmu->fixed_ctr_ctrl != data)
> reprogram_fixed_counters(pmu, data);
> break;
> @@ -494,6 +500,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
> if (data & eventsel_rsvd)
> return 1;
>
> + /* See above comments for MSR_CORE_PERF_FIXED_CTR_CTRL. */
> + data &= ~ARCH_PERFMON_EVENTSEL_ANY;
> if (data != pmc->eventsel) {
> pmc->eventsel = data;
> pmc->eventsel_hw = data;
> @@ -603,6 +611,17 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
> pmu->pmc_exists64 = (BIT_ULL(nr_gp_counters) - 1) &
> kvm_pmu_cap.cntr_mask64;
>
> + /*
> + * AnyThread counting is not supported by KVM due to cross-VM
> + * information leakage concerns on SMT cores. Therefore, AnyThread
> + * remains unavailable for PerfMon v3/v4 guests, where AnyThread
> + * deprecation is not enumerated.
> + */
> + if (pmu->version >= 5 && edx.split.anythread_deprecated) {
> + pmu->eventsel_rsvd &= ~ARCH_PERFMON_EVENTSEL_ANY;
> + fixed_enable_bits |= INTEL_FIXED_0_ANYTHREAD;
> + }
> +
> entry = kvm_find_cpuid_entry_index(vcpu, 7, 0);
> if (entry &&
> (boot_cpu_has(X86_FEATURE_HLE) || boot_cpu_has(X86_FEATURE_RTM)) &&
next prev parent reply other threads:[~2026-09-01 8:01 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-27 22:37 [PATCH] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Zide Chen
2026-08-27 22:37 ` [PATCH v2 01/16] KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions Zide Chen
2026-08-27 22:57 ` sashiko-bot
2026-08-28 13:51 ` Chen, Zide
2026-09-01 2:07 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 02/16] KVM: x86/pmu: Rename all_valid_pmc_idx to pmc_exists Zide Chen
2026-09-01 2:09 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 03/16] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu Zide Chen
2026-09-01 2:17 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 04/16] KVM: x86/pmu: Gate BUFFER_OVF reserved bit on guest DS Zide Chen
2026-09-01 2:30 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 05/16] KVM: x86/pmu: Add PMC bitmap accessor helpers Zide Chen
2026-09-01 2:43 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 06/16] KVM: x86/pmu: Drop nr_arch_{gp,fixed}_counters from kvm_pmu Zide Chen
2026-09-01 3:07 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 07/16] KVM: x86/pmu: Expose kvm_host_pmu to vendor modules Zide Chen
2026-09-01 3:08 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 08/16] perf/x86: Plumb counter bitmap from x86_pmu to x86_pmu_cap Zide Chen
2026-08-27 22:37 ` [PATCH v2 09/16] KVM: x86/pmu: Switch to bitmask-based KVM PMU capabilities Zide Chen
2026-09-01 3:32 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 10/16] perf/x86: Remove num_counters_{gp,fixed} from x86_pmu_capability Zide Chen
2026-08-27 22:37 ` [PATCH v2 11/16] KVM: x86/pmu: Emulate the GLOBAL_STATUS_SET and GLOBAL_INUSE MSRs Zide Chen
2026-08-27 23:05 ` sashiko-bot
2026-08-28 20:22 ` Chen, Zide
2026-09-01 6:45 ` Mi, Dapeng
2026-09-01 14:20 ` Chen, Zide
2026-09-02 0:44 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 12/16] KVM: x86/pmu: Populate CPUID.0AH:ECX fixed-counter bitmap Zide Chen
2026-09-01 6:50 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 13/16] KVM: x86/pmu: Factor out fixed counter control bit calculation Zide Chen
2026-09-01 6:57 ` Mi, Dapeng
2026-08-27 22:37 ` [PATCH v2 14/16] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set Zide Chen
2026-09-01 8:01 ` Mi, Dapeng [this message]
2026-08-27 22:37 ` [PATCH v2 15/16] KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts Zide Chen
2026-08-27 22:37 ` [PATCH v2 16/16] KVM: selftests: Support fixed counters bitmap in pmu_counters_test Zide Chen
2026-08-29 9:30 ` [PATCH] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Peter Zijlstra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=89e1cb41-81b6-4f20-9fc2-d436dd77d988@linux.intel.com \
--to=dapeng1.mi@linux.intel.com \
--cc=Manali.Shukla@amd.com \
--cc=Sandipan.Das@amd.com \
--cc=ak@linux.intel.com \
--cc=eranian@google.com \
--cc=jmattson@google.com \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mizhang@google.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=seanjc@google.com \
--cc=xudong.hao@intel.com \
--cc=zide.chen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox