Re: [PATCH v3 4/9] KVM: x86: Extend CPUID range to include new leaf

[Manali Shukla <manali.shukla@amd.com>]

On 10/8/2026 11:29 PM, Jim Mattson wrote:
> On Tue, Mar 10, 2026 at 06:00:16AM +0000, Manali Shukla wrote:
>> CPUID leaf 0x8000001b (EAX) provides information about Instruction-Based
>> sampling capabilities on AMD Platforms. Add the new leaf to
>> kvm_cpu_cap_init() using F() macros, which automatically gate each
>> capability bits against raw hardware CPUID via raw_cpuid_get().
>>
>> This allows vendor code to simply clear entire leaf when vibs is not
>> enabled, rather than reading hardware CPUID and calling
>> kvm_cpu_cap_set() for each capability bits inidividually in later
>> patches.
>>
>> Signed-off-by: Manali Shukla <manali.shukla@amd.com>
> 
> The shortlog is not accurate. The CPUID range does not change; case
> 0x80000000 already limits the maximum extended leaf to 0x80000022, which
> includes 0x8000001B. Before this patch, leaf 0x8000001B went to the default
> case, which returns all zeros. This patch adds KVM's supported bits for the
> leaf and a case that reports them when X86_FEATURE_IBS is supported. Please
> change the shortlog to say that.
> 

Agreed. I will change the shortlog

Probably something like this ?
KVM: x86: Report supported IBS capabilities in CPUID 0x8000001B

> Also, there are some typos in the changelog:
>   - "Instruction-Based sampling" should be "Instruction-Based Sampling"
>   - "capability bits" should be "capability bit" (twice)
>   - "inidividually" should be "individually"
>   - "vibs" should be "VIBS"
> 

Will fix it in V4.

>> ---
>>  arch/x86/kvm/cpuid.c | 25 +++++++++++++++++++++++++
>>  1 file changed, 25 insertions(+)
>>
>> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
>> index 96a08a556543..4e626e77e6a6 100644
>> --- a/arch/x86/kvm/cpuid.c
>> +++ b/arch/x86/kvm/cpuid.c
> 
> [...]
> 
>> @@ -1848,6 +1864,15 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
>>  		entry->eax = entry->ebx = entry->ecx = 0;
>>  		entry->edx = 0; /* reserved */
>>  		break;
>> +	/* AMD IBS capability */
>> +	case 0x8000001B:
>> +		if (!kvm_cpu_cap_has(X86_FEATURE_IBS))
>> +			entry->eax = 0;
>> +		else
>> +			cpuid_entry_override(entry, CPUID_8000_001B_EAX);
>> +
>> +		entry->ebx = entry->ecx = entry->edx = 0;
>> +		break;
> 
> Please put case 0x8000001b between case 0x8000001a and case 0x8000001e.

Will do in V4.

> 
>>  	case 0x8000001F:
>>  		if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) {
>>  			entry->eax = entry->ebx = entry->ecx = entry->edx = 0;

- Manali