From: Naveen N Rao <naveen@kernel.org>
To: Manali Shukla <manali.shukla@amd.com>
Cc: seanjc@google.com, pbonzini@redhat.com, mingo@redhat.com,
bp@alien8.de, dave.hansen@linux.intel.com, kvm@vger.kernel.org,
x86@kernel.org, santosh.shukla@amd.com, nikunj.dadhania@amd.com,
dapeng1.mi@linux.intel.com
Subject: Re: [PATCH v1 2/9] x86/apic: Add helper to get maximum number of Extended LVT registers
Date: Thu, 14 May 2026 18:20:20 +0530 [thread overview]
Message-ID: <agXEy94sHAwj2r-l@blrnaveerao1> (raw)
In-Reply-To: <20260204074452.55453-3-manali.shukla@amd.com>
On Wed, Feb 04, 2026 at 07:44:45AM +0000, Manali Shukla wrote:
> Add lapic_get_max_extlvt() to retrieve the maximum number of Extended
> LVT registers supported by the local APIC on AMD processors. The count
> is read from APIC_EFEAT[23:16] (offset 0x400), per AMD APM Volume 2.
>
> Extended LVT registers provide additional interrupt vectors beyond
> standard LVT entries, enabling features like Instruction Based Sampling
> (IBS). Current AMD processors support four extended LVT entries, but
> future processors may support up to 255.
>
> Wrap lapic_get_max_extlvt() with kvm_cpu_get_max_extlvt() for use by
> KVM code. Subsequent patches will use this helper to configure the guest's
> extended APIC register space.
>
> Signed-off-by: Manali Shukla <manali.shukla@amd.com>
> ---
> arch/x86/include/asm/apic.h | 1 +
> arch/x86/include/asm/kvm_host.h | 10 ++++++++++
> arch/x86/kernel/apic/apic.c | 17 +++++++++++++++++
> 3 files changed, 28 insertions(+)
This shouldn't be required if we go with:
http://lore.kernel.org/r/78a4c3ddce65e2a79f23aea6fdc05faf4346d290.1778594390.git.naveen@kernel.org
- Naveen
next prev parent reply other threads:[~2026-05-14 12:50 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-04 7:44 [PATCH v1 0/9] KVM: x86: Add support for AMD Extended APIC registers Manali Shukla
2026-02-04 7:44 ` [PATCH v1 1/9] KVM: x86: Refactor APIC register mask handling to support extended " Manali Shukla
2026-05-14 12:48 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 2/9] x86/apic: Add helper to get maximum number of Extended LVT registers Manali Shukla
2026-05-06 11:22 ` Borislav Petkov
2026-05-14 12:50 ` Naveen N Rao [this message]
2026-02-04 7:44 ` [PATCH v1 3/9] KVM: SVM: Set kvm_caps.has_extapic when CPU supports Extended APIC Manali Shukla
2026-05-14 12:58 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 4/9] KVM: x86: Introduce KVM_CAP_LAPIC2 for 4KB APIC register space support Manali Shukla
2026-05-14 13:08 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 5/9] KVM: x86: Refactor APIC state get/set to accept variable-sized buffers Manali Shukla
2026-05-14 14:20 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 6/9] KVM: Add KVM_GET_LAPIC2 and KVM_SET_LAPIC2 for extended APIC Manali Shukla
2026-03-16 13:00 ` Nikunj A. Dadhania
2026-03-23 11:15 ` Manali Shukla
2026-05-14 14:36 ` Naveen N Rao
2026-05-14 14:41 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 7/9] KVM: x86: Emulate Extended LVT registers for AMD guests Manali Shukla
2026-05-14 14:48 ` Naveen N Rao
2026-02-04 7:44 ` [PATCH v1 8/9] x86/cpufeatures: Add CPUID feature bit for Extended LVT AVIC acceleration Manali Shukla
2026-02-04 7:44 ` [PATCH v1 9/9] KVM: SVM: Add AVIC support for extended LVT MSRs Manali Shukla
2026-05-14 15:10 ` Naveen N Rao
2026-03-10 6:17 ` [PATCH v1 0/9] KVM: x86: Add support for AMD Extended APIC registers Manali Shukla
2026-04-27 4:34 ` Shukla, Manali
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