Re: [PATCH v1 9/9] KVM: SVM: Add AVIC support for extended LVT MSRs

[Naveen N Rao <naveen@kernel.org>]

On Wed, Feb 04, 2026 at 07:44:52AM +0000, Manali Shukla wrote:
> Configure MSR intercepts for extended LVT registers when both AVIC and
> AVIC_EXTLVT are supported by hardware.  Extended LVT registers are
> x2APIC MSRs at offsets 0x500-0x530 in the APIC register space.

That sounds a bit weird, since AFAIK the extended LVT registers are also 
present in the MMIO-based xAPIC.

> 
> When AVIC is enabled and MSR intercepts are disabled, allow passthrough
> access to extended LVT MSRs.  Hardware accelerates reads without VM-exits,
> while writes trigger trap-style VM-exits that are handled by the existing
> avic_unaccelerated_access_interception() path.

With Sean's recent changes 
(https://lore.kernel.org/kvm/20260506184746.2719880-1-seanjc@google.com), 
the preference is to intercept all the MSRs that are not 
write-accelerated by AVIC, so the only change for this patch would be 
for AVIC_UNACCELERATED_ACCESS handling for xAVIC.

Also, per the APM Section "15.29.3.1 Virtual APIC Register Accesses":
	"Accesses to any other register locations not explicitly defined 
	in this table are allowed to read and write the backing page."

So, I don't think we need to be too strict about which EILVT registers 
can cause this. It's probably simplest to just list the 4 EILVT 
registers handled by AVIC today:

diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c
index 101ffab48145..b2eececf41e9 100644
--- a/arch/x86/kvm/svm/avic.c
+++ b/arch/x86/kvm/svm/avic.c
@@ -818,6 +818,13 @@ static bool is_avic_unaccelerated_access_trap(u32 offset)
        case APIC_TDCR:
                ret = true;
                break;
+       case APIC_EILVTn(0):
+       case APIC_EILVTn(1):
+       case APIC_EILVTn(2):
+       case APIC_EILVTn(3):
+               if (cpu_feature_enabled(X86_FEATURE_AVIC_EXTLVT))
+                       ret = true;
+               break;
        default:
                break;
        }


- Naveen