Re: [PATCH] KVM: SVM: Do not warn on IGNNE MSR write

[Jerry Lyu <jerry.lyu@open-hieco.net>]

Thanks Sean for the prompt feedback!

On Wed, Jul 08, 2026 at 06:50:50AM -0700, Sean Christopherson wrote:
> On Wed, Jul 08, 2026, Jerry Lyu wrote:
> > Booting windows server 2025 on top of Linux KVM results in host kernel
> > warning logs of "Unhandled WRMSR(0xc0010115) = 0x0", which is due to
> > "IGNNE MSR" write in guest hyper-v. According to AMD APM volume 2,
> > section 15.30.2, the MSR is "only useful if IGNNE emulation has been
> > enabled in the HW_CR MSR", while currently KVM has prevented guests from
> > enabling it. So change the warning to a stronger check.
> 
> Except the APM doesn't say anything about the ordering, and in typical APM

Indeed. I did some experiment on bare metal system to write IGNNE MSR
with it disabled and then write HW_CR to enable it, the written value is
still there. It can be in any order.

> fashion, nor does it actually say what happens if IGNNE emulation is disabled.

Right. I did not find that as well. Since IGNNE MSR and IGNNE emulation
is an incremental feature, it would be reasonable to guess that hardware
will fall back to the IGNNE pin usage relying on external sources to
assert/de-assert it. If the IGNNE pin is not available in hardware,
CR0.NE must not be 0 to use the legacy mode.

> 
> > IGNNE is used in the legacy MS-DOS compatibility sub-mode of X87 FPU
> > exception handling. Intel SDM volume 1, section 8,7.2 describes the
> > details of this mode which applies to AMD CPU as well. The CPU selects
> > this mode when CR0.NE bit is 0, and will rely on two pins (FERR# and
> > IGNNE#) for exception handling. AMD later introduced IGNNE MSR to "set
> > the state of the processor-internal IGNNE signal directly" in order to
> > support the legacy mode without the dependency on IGNNE# pin.
> > 
> > The current KVM implementation does not emulate this feature, not sound
> > necessary as well. The commit 82494028dff648c29e3a ("KVM: SVM: Ignore
> > write of hwcr.ignne") clears the bit-8 value in the guest HWCR MSR
> > write, making such field always zero, then the write to guest IGNNE MSR
> > can always be safely ignored.
> 
> Well, yeah, that's what KVM is doing, ignoring the write.  But KVM is also logging
> that the guest attempted to write an MSR that KVM doesn't support, i.e. this is
> more or less working as intended.
> 
> That said, KVM does effectively support the case where #IGGNE is not asserted, so
> I think we can simply do this to avoid the useless logging?

Yeah, that can work for the current case. However, if another guest
initializes the IGNNE MSR with different value meanwhile never enables
the IGNNE emulation, kvm will again print uselsss logging. How about
adding warning in HW_CR like below?

diff --git a/arch/x86/kvm/msrs.c b/arch/x86/kvm/msrs.c
index c230b18d87e3..cbb743c41276 100644
--- a/arch/x86/kvm/msrs.c
+++ b/arch/x86/kvm/msrs.c
@@ -1564,12 +1564,17 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                u64 valid = BIT_ULL(18) | BIT_ULL(24);
 
                data &= ~(u64)0x40;     /* ignore flush filter disable */
-               data &= ~(u64)0x100;    /* ignore ignne emulation enable */
                data &= ~(u64)0x8;      /* ignore TLB cache disable */
 
                if (guest_cpu_cap_has(vcpu, X86_FEATURE_GP_ON_USER_CPUID))
                        valid |= MSR_K7_HWCR_CPUID_USER_DIS;
 
+               if (data & ~BIT_ULL(8)) {
+                       /* ignore ignne emulation enable with a warning */
+                       data &= ~(u64)0x100;
+                       kvm_pr_unimpl_wrmsr(vcpu, msr, data);
+               }
+
                if (data & ~valid) {
                        kvm_pr_unimpl_wrmsr(vcpu, msr, data);
                        return 1;

Then the IGNNE write can be silently ignored no matter what value to
write. The kvm selftest of hwcr_msr_test.c can keep unchanged. What's
your opinion? Thanks again!

> 
> diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> index e755f43f4376..a7efac3241c2 100644
> --- a/arch/x86/kvm/svm/svm.c
> +++ b/arch/x86/kvm/svm/svm.c
> @@ -3205,7 +3205,8 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
>         case MSR_VM_CR:
>                 return svm_set_vm_cr(vcpu, data);
>         case MSR_VM_IGNNE:
> -               kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
> +               if (data)
> +                       kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
>                 break;
>         case MSR_AMD64_DE_CFG: {
>                 u64 supported_de_cfg;