Re: [PATCH] KVM: SVM: Do not warn on IGNNE MSR write

[Jerry Lyu <jerry.lyu@open-hieco.net>]

On Thu, Jul 09, 2026 at 09:41:06AM +0800, Jerry Lyu wrote:
> Thanks Sean for the prompt feedback!
> 

[trim]

> > 
> > Well, yeah, that's what KVM is doing, ignoring the write.  But KVM is also logging
> > that the guest attempted to write an MSR that KVM doesn't support, i.e. this is
> > more or less working as intended.
> > 
> > That said, KVM does effectively support the case where #IGGNE is not asserted, so
> > I think we can simply do this to avoid the useless logging?
> 
> Yeah, that can work for the current case. However, if another guest
> initializes the IGNNE MSR with different value meanwhile never enables
> the IGNNE emulation, kvm will again print uselsss logging. How about
> adding warning in HW_CR like below?

Did more testing and found that windows did set the
HWCR.IgnneEm (bit-8). The conditonal branch needs to be below to avoid
the warning:

+               if (data & BIT_ULL(8)) {
+                       /* ignore ignne emulation enable with a warning */
+                       if (!(vcpu->arch.cr0 & X86_CR0_NE))
+                               kvm_pr_unimpl_wrmsr(vcpu, msr, data);
+                       data &= ~(u64)0x100;
+               }

This is also not complete as it only checks the current vcpu's cr0 while
the MSR is global, and it cannot capture the case where people enable
IgnneEm before clearing CR0.NE.

I now tend to go with Sean's initial suggestion which is simple and
address the windows issue. Thanks!

Regards,
-Jerry

> 
> diff --git a/arch/x86/kvm/msrs.c b/arch/x86/kvm/msrs.c
> index c230b18d87e3..cbb743c41276 100644
> --- a/arch/x86/kvm/msrs.c
> +++ b/arch/x86/kvm/msrs.c
> @@ -1564,12 +1564,17 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>                 u64 valid = BIT_ULL(18) | BIT_ULL(24);
>  
>                 data &= ~(u64)0x40;     /* ignore flush filter disable */
> -               data &= ~(u64)0x100;    /* ignore ignne emulation enable */
>                 data &= ~(u64)0x8;      /* ignore TLB cache disable */
>  
>                 if (guest_cpu_cap_has(vcpu, X86_FEATURE_GP_ON_USER_CPUID))
>                         valid |= MSR_K7_HWCR_CPUID_USER_DIS;
>  
> +               if (data & BIT_ULL(8)) {
> +                       /* ignore ignne emulation enable with a warning */
> +                       data &= ~(u64)0x100;
> +                       kvm_pr_unimpl_wrmsr(vcpu, msr, data);
> +               }
> +
>                 if (data & ~valid) {
>                         kvm_pr_unimpl_wrmsr(vcpu, msr, data);
>                         return 1;
> 
> Then the IGNNE write can be silently ignored no matter what value to
> write. The kvm selftest of hwcr_msr_test.c can keep unchanged. What's
> your opinion? Thanks again!
> 
> > 
> > diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
> > index e755f43f4376..a7efac3241c2 100644
> > --- a/arch/x86/kvm/svm/svm.c
> > +++ b/arch/x86/kvm/svm/svm.c
> > @@ -3205,7 +3205,8 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
> >         case MSR_VM_CR:
> >                 return svm_set_vm_cr(vcpu, data);
> >         case MSR_VM_IGNNE:
> > -               kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
> > +               if (data)
> > +                       kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
> >                 break;
> >         case MSR_AMD64_DE_CFG: {
> >                 u64 supported_de_cfg;