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From: Zhao Liu <zhao1.liu@intel.com>
To: Tina Zhang <zhang_wei@open-hieco.net>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
	"Michael S . Tsirkin" <mst@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Marcelo Tosatti <mtosatti@redhat.com>,
	Yanjing Zhou <zhouyanjing@hygon.cn>
Subject: Re: [PATCH v2 5/9] target/i386/kvm: Use AMD PMU MSR paths for Hygon
Date: Sun, 23 Aug 2026 17:32:32 +0800	[thread overview]
Message-ID: <aoq+MK8Vbvr1wA2c@intel.com> (raw)
In-Reply-To: <20260810082956.1768042-6-zhang_wei@open-hieco.net>

On Mon, Aug 10, 2026 at 04:29:52PM +0800, Tina Zhang wrote:
> Date: Mon, 10 Aug 2026 16:29:52 +0800
> From: Tina Zhang <zhang_wei@open-hieco.net>
> Subject: [PATCH v2 5/9] target/i386/kvm: Use AMD PMU MSR paths for Hygon
> X-Mailer: git-send-email 2.43.7
> 
> On SVM, KVM uses the AMD PMU implementation and AMD PMU CPUID/MSR
> layout.  Hygon guests that enable PMU and request AMD PMU CPUID
> features such as perfctr-core need QEMU's KVM PMU setup and MSR state
> paths to use that layout too.
> 
> The relevant QEMU KVM PMU paths are currently restricted to
> AuthenticAMD guests: host/guest PMU compatibility checks, AMD PMU
> information initialization, and AMD PMU MSR save/restore.  For a Hygon
> Dhyana guest with pmu=on, the compatibility check reports vPMU as
> unsupported solely because the guest vendor is HygonGenuine rather than
> AuthenticAMD.  If the VM continues, QEMU still skips AMD PMU setup and
> never saves or restores the AMD PMU MSRs for the Hygon guest.
> 
> Treat Hygon as using the AMD PMU CPUID/MSR layout for these KVM PMU
> paths.  Because the PMU MSR layout is shared, accept both AMD and Hygon
> hosts for guests using that layout.  This intentionally allows the PMU
> compatibility check to pass for AMD-host/Hygon-guest and
> Hygon-host/AMD-guest combinations.
> 
> This does not enable PMU, perfctr-core, or perfmon-v2 by default for the
> Dhyana CPU model.  On backward migration to older QEMU, Hygon PMU MSR
> state may still be dropped because older QEMU did not write that state
> back through the AMD PMU MSR KVM paths for Hygon guests.
> 
> Signed-off-by: Tina Zhang <zhang_wei@open-hieco.net>
> ---
>  target/i386/kvm/kvm.c | 73 +++++++++++++++++++++++++++++++++----------
>  1 file changed, 56 insertions(+), 17 deletions(-)

The code looks good to me! It would be even better if this could be
split into two patches - one dedicated to refactoring the vendor checks
first, and another to add Hygon as a new AMD-compatible vendor.

This would make it easier for maintainers to review, and the current
commit message would more directly correspond to the Hygon-specific
changes. :)

Thanks,
Zhao


  reply	other threads:[~2026-08-23  9:32 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-10  8:29 [PATCH v2 0/9] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
2026-08-10  8:29 ` [PATCH v2 1/9] target/i386: Sync AMD CPUID aliases for Hygon Tina Zhang
2026-08-23  8:47   ` Zhao Liu
2026-08-24  5:05     ` Tina Zhang
2026-08-10  8:29 ` [PATCH v2 2/9] target/i386: Hide Intel cache CPUID leaves " Tina Zhang
2026-08-23  8:49   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 3/9] target/i386: Hide ARCH_CAPABILITIES " Tina Zhang
2026-08-23  8:50   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 4/9] target/i386/kvm: Use AMD MCE status encoding " Tina Zhang
2026-08-23  8:51   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 5/9] target/i386/kvm: Use AMD PMU MSR paths " Tina Zhang
2026-08-23  9:32   ` Zhao Liu [this message]
2026-08-10  8:29 ` [PATCH v2 6/9] target/i386: Do not broadcast injected MCEs " Tina Zhang
2026-08-23  8:55   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 7/9] hw/i386: Reserve AMD IOMMU HT GPA range " Tina Zhang
2026-08-23  9:17   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 8/9] target/i386: Use AMD legacy cache fallback " Tina Zhang
2026-08-23  9:18   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 9/9] target/i386: Use AMD ucode-rev default " Tina Zhang
2026-08-23  9:24   ` Zhao Liu

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