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From: Zhao Liu <zhao1.liu@intel.com>
To: Tina Zhang <zhang_wei@open-hieco.net>
Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org,
	"Michael S . Tsirkin" <mst@redhat.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Marcelo Tosatti <mtosatti@redhat.com>,
	Yanjing Zhou <zhouyanjing@hygon.cn>
Subject: Re: [PATCH v2 2/9] target/i386: Hide Intel cache CPUID leaves for Hygon
Date: Sun, 23 Aug 2026 16:49:16 +0800	[thread overview]
Message-ID: <aoq0DKEJTYmfUlAe@intel.com> (raw)
In-Reply-To: <20260810082956.1768042-3-zhang_wei@open-hieco.net>

On Mon, Aug 10, 2026 at 04:29:49PM +0800, Tina Zhang wrote:
> Date: Mon, 10 Aug 2026 16:29:49 +0800
> From: Tina Zhang <zhang_wei@open-hieco.net>
> Subject: [PATCH v2 2/9] target/i386: Hide Intel cache CPUID leaves for Hygon
> X-Mailer: git-send-email 2.43.7
> 
> When x-vendor-cpuid-only is enabled, QEMU suppresses CPUID leaves 2
> and 4 for AuthenticAMD CPUs because those leaves describe Intel cache
> information.  Hygon Dhyana uses the HygonGenuine vendor string, so it
> currently skips that filtering and can expose Intel cache leaves together
> with AMD/Hygon extended cache leaves.
> 
> That is inconsistent guest-visible CPUID: Hygon Dhyana provides cache
> information through the extended cache leaves, so it should not also
> advertise the Intel cache descriptor and deterministic cache parameter
> leaves.
> 
> Apply the same leaf 2 and leaf 4 filtering to Hygon CPUs when the vendor
> CPU ABI compat gate is enabled.  The gate keeps the old CPUID output for
> pc-11.0 and older machine types.

nit: pc-11.1?

Thanks,
Zhao

  reply	other threads:[~2026-08-23  8:49 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-10  8:29 [PATCH v2 0/9] target/i386: Fix Hygon vendor-specific CPU behavior Tina Zhang
2026-08-10  8:29 ` [PATCH v2 1/9] target/i386: Sync AMD CPUID aliases for Hygon Tina Zhang
2026-08-23  8:47   ` Zhao Liu
2026-08-24  5:05     ` Tina Zhang
2026-08-10  8:29 ` [PATCH v2 2/9] target/i386: Hide Intel cache CPUID leaves " Tina Zhang
2026-08-23  8:49   ` Zhao Liu [this message]
2026-08-10  8:29 ` [PATCH v2 3/9] target/i386: Hide ARCH_CAPABILITIES " Tina Zhang
2026-08-23  8:50   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 4/9] target/i386/kvm: Use AMD MCE status encoding " Tina Zhang
2026-08-23  8:51   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 5/9] target/i386/kvm: Use AMD PMU MSR paths " Tina Zhang
2026-08-23  9:32   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 6/9] target/i386: Do not broadcast injected MCEs " Tina Zhang
2026-08-23  8:55   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 7/9] hw/i386: Reserve AMD IOMMU HT GPA range " Tina Zhang
2026-08-23  9:17   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 8/9] target/i386: Use AMD legacy cache fallback " Tina Zhang
2026-08-23  9:18   ` Zhao Liu
2026-08-10  8:29 ` [PATCH v2 9/9] target/i386: Use AMD ucode-rev default " Tina Zhang
2026-08-23  9:24   ` Zhao Liu

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