* [PATCH 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition @ 2015-03-02 16:57 Baptiste Reynal 2015-03-02 17:24 ` Will Deacon 0 siblings, 1 reply; 3+ messages in thread From: Baptiste Reynal @ 2015-03-02 16:57 UTC (permalink / raw) To: iommu, kvmarm Cc: Joerg Roedel, Will Deacon, open list, tech, moderated list:ARM SMMU DRIVER This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys through ATS1PR". According to ARM documentation, translation registers are optional even in SMMUv1, so ID0_S1TS needs to be checked to verify their presence. Signed-off-by: Baptiste Reynal <b.reynal@virtualopensystems.com> --- drivers/iommu/arm-smmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index fc13dd5..d4beca4 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1556,7 +1556,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) return -ENODEV; } - if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) { + if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) { smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; dev_notice(smmu->dev, "\taddress translation ops\n"); } -- 2.3.1 ^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition 2015-03-02 16:57 [PATCH 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition Baptiste Reynal @ 2015-03-02 17:24 ` Will Deacon [not found] ` <20150302172444.GB7919-5wv7dgnIgG8@public.gmane.org> 0 siblings, 1 reply; 3+ messages in thread From: Will Deacon @ 2015-03-02 17:24 UTC (permalink / raw) To: Baptiste Reynal Cc: iommu@lists.linux-foundation.org, kvmarm@lists.cs.columbia.edu, tech@virtualopensystems.com, Joerg Roedel, moderated list:ARM SMMU DRIVER, open list On Mon, Mar 02, 2015 at 04:57:22PM +0000, Baptiste Reynal wrote: > This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys > through ATS1PR". > According to ARM documentation, translation registers are optional even > in SMMUv1, so ID0_S1TS needs to be checked to verify their presence. > > Signed-off-by: Baptiste Reynal <b.reynal@virtualopensystems.com> > --- > drivers/iommu/arm-smmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index fc13dd5..d4beca4 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -1556,7 +1556,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) > return -ENODEV; > } > > - if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) { > + if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) { > smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; > dev_notice(smmu->dev, "\taddress translation ops\n"); I'm not sure this is a complete fix. Shouldn't we also check that the domain is a stage-1 domain in arm_smmu_iova_to_phys? (potential fixup below). Will --->8 diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c index fc13dd56953e..107163295cbc 100644 --- a/drivers/iommu/arm-smmu.c +++ b/drivers/iommu/arm-smmu.c @@ -1288,12 +1288,15 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, return 0; spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); - if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS) + + if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && + smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { ret = arm_smmu_iova_to_phys_hard(domain, iova); - else + } else { ret = ops->iova_to_phys(ops, iova); - spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); + } + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); return ret; } ^ permalink raw reply related [flat|nested] 3+ messages in thread
[parent not found: <20150302172444.GB7919-5wv7dgnIgG8@public.gmane.org>]
* Re: [PATCH 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition [not found] ` <20150302172444.GB7919-5wv7dgnIgG8@public.gmane.org> @ 2015-03-03 8:57 ` Baptiste Reynal 0 siblings, 0 replies; 3+ messages in thread From: Baptiste Reynal @ 2015-03-03 8:57 UTC (permalink / raw) To: Will Deacon Cc: open list, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, tech-lrHrjnjw1UfHK3s98zE1ajGjJy/sRE9J@public.gmane.org, kvmarm-FPEHb7Xf0XXUo1n7N8X6UoWGPAHP3yOg@public.gmane.org, moderated list:ARM SMMU DRIVER [-- Attachment #1.1: Type: text/plain, Size: 2398 bytes --] Good point, I didn't thought about it. I will publish a new version with your modifications. Thanks On Mon, Mar 2, 2015 at 6:24 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: > On Mon, Mar 02, 2015 at 04:57:22PM +0000, Baptiste Reynal wrote: > > This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys > > through ATS1PR". > > According to ARM documentation, translation registers are optional even > > in SMMUv1, so ID0_S1TS needs to be checked to verify their presence. > > > > Signed-off-by: Baptiste Reynal <b.reynal-lrHrjnjw1UfHK3s98zE1ajGjJy/sRE9J@public.gmane.org> > > --- > > drivers/iommu/arm-smmu.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > > index fc13dd5..d4beca4 100644 > > --- a/drivers/iommu/arm-smmu.c > > +++ b/drivers/iommu/arm-smmu.c > > @@ -1556,7 +1556,7 @@ static int arm_smmu_device_cfg_probe(struct > arm_smmu_device *smmu) > > return -ENODEV; > > } > > > > - if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) > { > > + if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & > ID0_ATOSNS))) { > > smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; > > dev_notice(smmu->dev, "\taddress translation ops\n"); > > I'm not sure this is a complete fix. Shouldn't we also check that the > domain > is a stage-1 domain in arm_smmu_iova_to_phys? (potential fixup below). > > Will > > --->8 > > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c > index fc13dd56953e..107163295cbc 100644 > --- a/drivers/iommu/arm-smmu.c > +++ b/drivers/iommu/arm-smmu.c > @@ -1288,12 +1288,15 @@ static phys_addr_t arm_smmu_iova_to_phys(struct > iommu_domain *domain, > return 0; > > spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags); > - if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS) > + > + if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && > + smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { > ret = arm_smmu_iova_to_phys_hard(domain, iova); > - else > + } else { > ret = ops->iova_to_phys(ops, iova); > - spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); > + } > > + spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags); > return ret; > } > > [-- Attachment #1.2: Type: text/html, Size: 3280 bytes --] [-- Attachment #2: Type: text/plain, Size: 0 bytes --] ^ permalink raw reply [flat|nested] 3+ messages in thread
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2015-03-02 16:57 [PATCH 1/1] iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition Baptiste Reynal
2015-03-02 17:24 ` Will Deacon
[not found] ` <20150302172444.GB7919-5wv7dgnIgG8@public.gmane.org>
2015-03-03 8:57 ` Baptiste Reynal
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