From: James Morse <james.morse@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Julien Thierry <julien.thierry@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
wangxiongfeng2@huawei.com, kvmarm@lists.cs.columbia.edu
Subject: [RESEND PATCH v4 8/9] arm64: entry.S: convert elX_irq
Date: Thu, 2 Nov 2017 12:12:41 +0000 [thread overview]
Message-ID: <20171102121242.8925-9-james.morse@arm.com> (raw)
In-Reply-To: <20171102121242.8925-1-james.morse@arm.com>
Following our 'dai' order, irqs should be processed with debug and
serror exceptions unmasked.
Add a helper to unmask these two, (and fiq for good measure).
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
==
Changes since v3:
* Added comment against enable_da_f
---
arch/arm64/include/asm/assembler.h | 5 +++++
arch/arm64/kernel/entry.S | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index c2a37e2f733c..e4ac505b7b3d 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -54,6 +54,11 @@
msr daif, \tmp
.endm
+ /* IRQ is the lowest priority flag, unconditionally unmask the rest. */
+ .macro enable_da_f
+ msr daifclr, #(8 | 4 | 1)
+ .endm
+
/*
* Enable and disable interrupts.
*/
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index f7dfe5d2b1fb..df085ec003b0 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -557,7 +557,7 @@ ENDPROC(el1_sync)
.align 6
el1_irq:
kernel_entry 1
- enable_dbg
+ enable_da_f
#ifdef CONFIG_TRACE_IRQFLAGS
bl trace_hardirqs_off
#endif
@@ -766,7 +766,7 @@ ENDPROC(el0_sync)
el0_irq:
kernel_entry 0
el0_irq_naked:
- enable_dbg
+ enable_da_f
#ifdef CONFIG_TRACE_IRQFLAGS
bl trace_hardirqs_off
#endif
--
2.15.0.rc2
next prev parent reply other threads:[~2017-11-02 12:13 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-02 12:12 [RESEND PATCH v4 0/9] SError rework (- RAS & IESB for firmware first support) James Morse
2017-11-02 12:12 ` [RESEND PATCH v4 1/9] arm64: explicitly mask all exceptions James Morse
2017-11-02 12:12 ` [RESEND PATCH v4 2/9] arm64: introduce an order for exceptions James Morse
2017-11-02 12:12 ` [RESEND PATCH v4 3/9] arm64: Move the async/fiq helpers to explicitly set process context flags James Morse
2017-11-02 12:12 ` [RESEND PATCH v4 4/9] arm64: Mask all exceptions during kernel_exit James Morse
2017-11-02 12:12 ` [RESEND PATCH v4 5/9] arm64: entry.S: Remove disable_dbg James Morse
2017-11-02 12:12 ` [RESEND PATCH v4 6/9] arm64: entry.S: convert el1_sync James Morse
2017-11-02 12:12 ` [RESEND PATCH v4 7/9] arm64: entry.S convert el0_sync James Morse
2017-11-02 12:12 ` James Morse [this message]
2017-11-02 12:12 ` [RESEND PATCH v4 9/9] arm64: entry.S: move SError handling into a C function for future expansion James Morse
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20171102121242.8925-9-james.morse@arm.com \
--to=james.morse@arm.com \
--cc=catalin.marinas@arm.com \
--cc=julien.thierry@arm.com \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=wangxiongfeng2@huawei.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox