Re: [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields

[Marc Zyngier <maz@kernel.org>]

On Fri, 24 Jul 2026 12:14:04 +0100,
sashiko-bot@kernel.org wrote:
> 
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> 
> Pre-existing issues:
> - [High] Missing Context Synchronization Event (`isb()`) immediately following writes to `ICC_*_EL1` control registers.
> - [High] CONSTRAINED UNPREDICTABLE behavior risk in `GIC CDEOI` system instruction encoding.
> --

[...]

>
> [Severity: High]
> This is a pre-existing issue, but while reviewing the GICv5 interactions,
> does the CDEOI instruction encoding rely on compiler constraints instead of
> hardcoding the required register?
> 
> In drivers/irqchip/irq-gic-v5.c:gicv5_handle_irq(), the instruction is
> emitted using:
> 
> drivers/irqchip/irq-gic-v5.c:gicv5_handle_irq() {
> 	gic_insn(0, CDEOI);
> }
> 
> If the compiler allocates a general-purpose register containing 0 instead of
> explicitly using XZR (register 31), could this lead to a misencoded system
> instruction and CONSTRAINED UNPREDICTABLE behavior?

and I thought AI was good at digging a bit deeper... What a nonsense
(see write_sysreg_s()).

	M.

-- 
Jazz isn't dead. It just smells funny.