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From: Marc Zyngier <maz@kernel.org>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
	"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
	Joey Gouly <Joey.Gouly@arm.com>,
	Suzuki Poulose <Suzuki.Poulose@arm.com>,
	"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
	"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
	Timothy Hayes <Timothy.Hayes@arm.com>,
	"fuad.tabba@linux.dev" <fuad.tabba@linux.dev>
Subject: Re: [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain
Date: Sat, 25 Jul 2026 11:56:54 +0100	[thread overview]
Message-ID: <87y0ezpcax.wl-maz@kernel.org> (raw)
In-Reply-To: <20260724104819.1296803-9-sascha.bischoff@arm.com>

On Fri, 24 Jul 2026 11:50:28 +0100,
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
> 
> VPE doorbells allow the GICv5 hardware to notify KVM when an SPI or LPI
> can be signalled to a non-resident VPE. This provides the mechanism used
> to wake blocked vcpus once the hardware determines that the interrupt is
> eligible to be delivered.
> 
> Add support for a per-VM VPE doorbell irq domain. The domain is created
> under the GICv5 LPI domain, with one doorbell allocated per VPE. Store
> the allocated doorbell base in the VM's GICv5 state so that later
> patches can request per-vcpu doorbell IRQs and use them for IRS
> commands and wakeups.
> 
> Add the per-VPE doorbell state to the GICv5 CPU interface state. The
> doorbell IRQ number is populated when the IRQs are requested, and the
> db_fired state is used by later patches once doorbell delivery is wired
> up.
> 
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> ---
>  arch/arm64/kvm/vgic/vgic-init.c    |  18 ++--
>  arch/arm64/kvm/vgic/vgic-v5.c      | 139 +++++++++++++++++++++++++++++
>  arch/arm64/kvm/vgic/vgic.h         |   1 +
>  include/kvm/arm_vgic.h             |   4 +
>  include/linux/irqchip/arm-gic-v5.h |   2 +
>  5 files changed, 158 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
> index 907057881b26a..625d352756fcf 100644
> --- a/arch/arm64/kvm/vgic/vgic-init.c
> +++ b/arch/arm64/kvm/vgic/vgic-init.c
> @@ -492,16 +492,22 @@ static void kvm_vgic_dist_destroy(struct kvm *kvm)
>  	dist->nr_spis = 0;
>  	dist->vgic_dist_base = VGIC_ADDR_UNDEF;
>  
> -	if (dist->vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) {
> +	switch (dist->vgic_model) {
> +	case KVM_DEV_TYPE_ARM_VGIC_V2:
> +		dist->vgic_cpu_base = VGIC_ADDR_UNDEF;
> +		break;
> +	case KVM_DEV_TYPE_ARM_VGIC_V3:
>  		list_for_each_entry_safe(rdreg, next, &dist->rd_regions, list)
>  			vgic_v3_free_redist_region(kvm, rdreg);
>  		INIT_LIST_HEAD(&dist->rd_regions);
> -	} else {
> -		dist->vgic_cpu_base = VGIC_ADDR_UNDEF;
> -	}
>  
> -	if (vgic_supports_direct_irqs(kvm))
> -		vgic_v4_teardown(kvm);
> +		if (vgic_supports_direct_irqs(kvm))
> +			vgic_v4_teardown(kvm);
> +		break;
> +	case KVM_DEV_TYPE_ARM_VGIC_V5:
> +		vgic_v5_teardown(kvm);
> +		break;
> +	}
>  
>  	xa_destroy(&dist->lpi_xa);
>  }
> diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
> index 3f7b132110114..ebd7c3ede975f 100644
> --- a/arch/arm64/kvm/vgic/vgic-v5.c
> +++ b/arch/arm64/kvm/vgic/vgic-v5.c
> @@ -7,6 +7,7 @@
>  
>  #include <linux/bitops.h>
>  #include <linux/irqchip/arm-vgic-info.h>
> +#include <linux/irqdomain.h>
>  
>  #include "vgic.h"
>  
> @@ -152,6 +153,134 @@ int vgic_v5_probe(const struct gic_kvm_info *info)
>  	return 0;
>  }
>  
> +/*
> + * This set of irq_chip functions is specific for doorbells.
> + */
> +static const struct irq_chip vgic_v5_db_irq_chip = {
> +	.name = "GICv5-DB",
> +	.irq_mask = irq_chip_mask_parent,
> +	.irq_unmask = irq_chip_unmask_parent,
> +	.irq_eoi = irq_chip_eoi_parent,
> +	.irq_set_affinity = irq_chip_set_affinity_parent,
> +	.irq_get_irqchip_state = irq_chip_get_parent_state,
> +	.irq_set_irqchip_state = irq_chip_set_parent_state,
> +	.flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_SKIP_SET_WAKE |
> +		 IRQCHIP_MASK_ON_SUSPEND,
> +};
> +
> +static void vgic_v5_irq_db_domain_free(struct irq_domain *domain,
> +				       unsigned int virq, unsigned int nr_irqs)
> +{
> +	int i;
> +
> +	for (i = 0; i < nr_irqs; i++) {
> +		struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
> +
> +		irq_set_handler(virq + i, NULL);
> +		irq_domain_reset_irq_data(d);
> +	}
> +
> +	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
> +}
> +
> +static int vgic_v5_irq_db_domain_alloc(struct irq_domain *domain,
> +				       unsigned int virq, unsigned int nr_irqs,
> +				       void *arg)
> +{
> +	const struct irq_chip *chip = &vgic_v5_db_irq_chip;
> +	struct vgic_v5_vm *vm = arg;
> +	struct irq_data *irqd;
> +	int ret;
> +
> +	if (!vm) {
> +		kvm_err("invalid parameter for doorbell irq allocation\n");
> +		return -EINVAL;
> +	}

How can this happen?

> +
> +	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, NULL);
> +	if (ret)
> +		return ret;
> +
> +	for (int i = 0; i < nr_irqs; i++) {
> +		irq_domain_set_hwirq_and_chip(domain, virq + i, i, chip,
> +					      domain->host_data);
> +		irqd = irq_desc_get_irq_data(irq_to_desc(virq + i));
> +		irqd_set_single_target(irqd);
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct irq_domain_ops vgic_v5_irq_db_domain_ops = {
> +	.alloc = vgic_v5_irq_db_domain_alloc,
> +	.free = vgic_v5_irq_db_domain_free,
> +};
> +
> +static int vgic_v5_create_per_vm_domain(struct kvm *kvm)
> +{
> +	struct vgic_v5_vm *vm = &kvm->arch.vgic.gicv5_vm;
> +	int nr_vcpus = atomic_read(&kvm->online_vcpus);
> +	int id = task_pid_nr(current);
> +	int ret, db_virq = 0;
> +
> +	if (!gicv5_global_data.lpi_domain) {
> +		kvm_err("LPI domain uninitialized, can't set up KVM Doorbells\n");
> +		return -ENODEV;
> +	}

Surely we should fail KVM's initialisation if we don't have the LPI
domain, rather than checking this at the point of creating the
doorbells. I can't imagine how we'd run on GICv5 without LPIs
anyway...

> +
> +	vm->fwnode = irq_domain_alloc_named_id_fwnode("GICv5-vpe-db", id);
> +	if (!vm->fwnode)
> +		return -ENOMEM;
> +
> +	/*
> +	 * KVM per-VM VPE DB domain; child of LPI domain; only ever handles
> +	 * doorbells. We know how many doorbells we have, and therefore we
> +	 * create a linear domain.

The linear domain thing is an irqdomain implementation detail. We
don't need to capture this here.

> +	 */
> +	vm->domain = irq_domain_create_hierarchy(gicv5_global_data.lpi_domain,
> +						 0, nr_vcpus, vm->fwnode,
> +						 &vgic_v5_irq_db_domain_ops, vm);
> +	if (!vm->domain) {
> +		ret = -ENOMEM;
> +		goto err;
> +	}
> +
> +	db_virq = irq_domain_alloc_irqs(vm->domain, nr_vcpus, NUMA_NO_NODE, vm);
> +	if (db_virq <= 0) {
> +		ret = db_virq;
> +		goto err;
> +	}
> +
> +	kvm->arch.vgic.gicv5_vm.vpe_db_base = db_virq;
> +
> +	return 0;
> +
> +err:
> +	if (db_virq > 0)
> +		irq_domain_free_irqs(db_virq, nr_vcpus);
> +	if (vm->domain)
> +		irq_domain_remove(vm->domain);
> +	if (vm->fwnode)
> +		irq_domain_free_fwnode(vm->fwnode);
> +
> +	kvm->arch.vgic.gicv5_vm.vpe_db_base = 0;
> +	vm->domain = NULL;
> +	vm->fwnode = NULL;
> +
> +	return ret;
> +}
> +
> +static void vgic_v5_teardown_per_vm_domain(struct vgic_v5_vm *vm)
> +{
> +	if (!vm->domain)
> +		return;
> +
> +	irq_domain_remove(vm->domain);
> +	irq_domain_free_fwnode(vm->fwnode);
> +	vm->domain = NULL;
> +	vm->fwnode = NULL;
> +}
> +
>  void vgic_v5_reset(struct kvm_vcpu *vcpu)
>  {
>  	/*
> @@ -167,10 +296,16 @@ void vgic_v5_reset(struct kvm_vcpu *vcpu)
>  	vcpu->arch.vgic_cpu.num_pri_bits = 5;
>  }
>  
> +void vgic_v5_teardown(struct kvm *kvm)
> +{
> +	vgic_v5_teardown_per_vm_domain(&kvm->arch.vgic.gicv5_vm);
> +}

Since this is a global symbol, I'd like to make sure this is never
called concurrently with anything related. Could you please add

	lockdep_assert_held(&kvm->arch.config_lock);

here?

> +
>  int vgic_v5_init(struct kvm *kvm)
>  {
>  	struct kvm_vcpu *vcpu;
>  	unsigned long idx;
> +	int ret;

and here?

>  
>  	if (vgic_initialized(kvm))
>  		return 0;
> @@ -182,6 +317,10 @@ int vgic_v5_init(struct kvm *kvm)
>  		}
>  	}
>  
> +	ret = vgic_v5_create_per_vm_domain(kvm);
> +	if (ret)
> +		return ret;
> +
>  	/* We only allow userspace to drive the SW_PPI, if it is implemented. */
>  	bitmap_zero(kvm->arch.vgic.gicv5_vm.userspace_ppis,
>  		    VGIC_V5_NR_PRIVATE_IRQS);
> diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h
> index f45f7e3ec4d6e..f2f5fdc3211d7 100644
> --- a/arch/arm64/kvm/vgic/vgic.h
> +++ b/arch/arm64/kvm/vgic/vgic.h
> @@ -366,6 +366,7 @@ void vgic_debug_destroy(struct kvm *kvm);
>  int vgic_v5_probe(const struct gic_kvm_info *info);
>  void vgic_v5_reset(struct kvm_vcpu *vcpu);
>  int vgic_v5_init(struct kvm *kvm);
> +void vgic_v5_teardown(struct kvm *kvm);
>  int vgic_v5_map_resources(struct kvm *kvm);
>  void vgic_v5_set_ppi_ops(struct kvm_vcpu *vcpu, u32 vintid);
>  bool vgic_v5_has_pending_ppi(struct kvm_vcpu *vcpu);
> diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
> index 8d65a18fefb80..bff2b7c896d55 100644
> --- a/include/kvm/arm_vgic.h
> +++ b/include/kvm/arm_vgic.h
> @@ -392,6 +392,10 @@ struct vgic_v5_vm {
>  	 * convenient way to do that).
>  	 */
>  	DECLARE_BITMAP(vgic_ppi_hmr, VGIC_V5_NR_PRIVATE_IRQS);
> +
> +	struct fwnode_handle	*fwnode;
> +	struct irq_domain	*domain;
> +	int			vpe_db_base;
>  };
>  
>  struct vgic_dist {
> diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h
> index 83cfcd056b250..21c8a69f99bb6 100644
> --- a/include/linux/irqchip/arm-gic-v5.h
> +++ b/include/linux/irqchip/arm-gic-v5.h
> @@ -613,6 +613,8 @@ void gicv5_irs_syncr(void);
>  
>  /* Embedded in kvm.arch */
>  struct gicv5_vpe {
> +	int			db;
> +	bool			db_fired;
>  	bool			resident;
>  };

Thanks,

	M.

-- 
Jazz isn't dead. It just smells funny.

  parent reply	other threads:[~2026-07-25 10:55 UTC|newest]

Thread overview: 125+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-31  9:20     ` Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10   ` sashiko-bot
2026-07-31  9:29     ` Sascha Bischoff
2026-07-25  9:06   ` Marc Zyngier
2026-07-25  9:18     ` Marc Zyngier
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-25 10:08     ` Marc Zyngier
2026-07-28 12:14       ` Fuad Tabba
2026-07-31  7:18       ` Sascha Bischoff
2026-07-25  9:35   ` Marc Zyngier
2026-07-31  7:21     ` Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14   ` sashiko-bot
2026-07-25 10:10     ` Marc Zyngier
2026-07-31  9:32     ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-31  9:35     ` Sascha Bischoff
2026-07-25 10:40   ` Marc Zyngier
2026-07-31  7:24     ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11   ` sashiko-bot
2026-07-31  9:33     ` Sascha Bischoff
2026-07-25 10:56   ` Marc Zyngier [this message]
2026-07-31  8:35     ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19   ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22   ` sashiko-bot
2026-07-27 16:39     ` Fuad Tabba
2026-07-27 17:55   ` Fuad Tabba
2026-07-31  9:11     ` Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20   ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21   ` sashiko-bot
2026-07-31 13:15     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27   ` sashiko-bot
2026-07-31 10:17     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26   ` sashiko-bot
2026-07-31 13:16     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-31 10:20     ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30   ` sashiko-bot
2026-07-31 10:22     ` Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45   ` sashiko-bot
2026-07-27 18:34   ` Fuad Tabba
2026-07-30 16:06     ` Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33   ` sashiko-bot
2026-07-31 13:05     ` Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41   ` sashiko-bot
2026-07-31 13:32     ` Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34   ` sashiko-bot
2026-07-31 13:18     ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39   ` sashiko-bot
2026-07-31 13:37     ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48   ` sashiko-bot
2026-07-31 13:49     ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-07-24 10:56 ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-07-24 12:09   ` sashiko-bot
2026-07-31 14:27     ` Sascha Bischoff
2026-07-24 10:56 ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-07-24 12:05   ` sashiko-bot
2026-07-31 14:42     ` Sascha Bischoff
2026-07-24 10:56 ` [PATCH v4 33/48] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-07-24 11:46   ` sashiko-bot
2026-07-31 14:35     ` Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-07-24 12:02   ` sashiko-bot
2026-07-31 16:43     ` Sascha Bischoff
2026-07-27 18:56   ` Fuad Tabba
2026-07-31  8:55     ` Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 36/48] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-07-24 12:19   ` sashiko-bot
2026-07-31 14:46     ` Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 38/48] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-07-27 19:26   ` Fuad Tabba
2026-07-31  9:19     ` Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 39/48] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 40/48] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-07-24 12:02   ` sashiko-bot
2026-07-31 16:24     ` Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-07-24 12:06   ` sashiko-bot
2026-07-31 15:52     ` Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 43/48] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 44/48] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 45/48] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-07-24 12:15   ` sashiko-bot
2026-07-31 14:54     ` Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-07-24 12:18   ` sashiko-bot
2026-07-31 14:49     ` Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 48/48] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
     [not found] ` <20260724104819.1296803-31-sascha.bischoff@arm.com>
2026-07-24 11:52   ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() sashiko-bot
2026-07-31 14:21     ` Sascha Bischoff
     [not found] ` <20260724104819.1296803-30-sascha.bischoff@arm.com>
2026-07-24 12:19   ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd sashiko-bot
2026-07-31 14:13     ` Sascha Bischoff

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