From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "sashiko-reviews@lists.linux.dev" <sashiko-reviews@lists.linux.dev>
Cc: "maz@kernel.org" <maz@kernel.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"oupton@kernel.org" <oupton@kernel.org>, nd <nd@arm.com>
Subject: Re: [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI
Date: Fri, 31 Jul 2026 10:20:00 +0000 [thread overview]
Message-ID: <faebdbb14014c073941e76beee7ae42376b9e077.camel@arm.com> (raw)
In-Reply-To: <20260724114111.E44D51F000E9@smtp.kernel.org>
On Fri, 2026-07-24 at 11:41 +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential
> issue(s) to consider:
> - [High] Stale `db_fired` state causes an infinite loop bypassing WFI
> sleep, pegging the host CPU to 100%.
> - [High] Incorrect GICv5 doorbell priority mask (DBPM) calculation
> drops preempting interrupts and vNMIs.
> --
>
> --- Patch [16]: [PATCH v4 16/48] KVM: arm64: gic-v5: Request
> doorbells when VPEs enter WFI ---
> commit 4c69e1e71f915cfc6ba78559fe449983dee20dd6
> Author: Sascha Bischoff <Sascha.Bischoff@arm.com>
>
> KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI
>
> This commit requests a GICv5 VPE doorbell when a vcpu enters WFI,
> allowing
> KVM to be notified when an SPI or LPI becomes pending. It also
> calculates
> a doorbell priority mask (DBPM) from the virtual priority state to
> avoid
> waking the guest for masked interrupts.
>
> > diff --git a/arch/arm64/kvm/vgic/vgic-v5.c
> > b/arch/arm64/kvm/vgic/vgic-v5.c
> > --- a/arch/arm64/kvm/vgic/vgic-v5.c
> > +++ b/arch/arm64/kvm/vgic/vgic-v5.c
> [ ... ]
> > + /*
> > + * Request a doorbell *unless* the priority is 0,
> > indicating
> > + * that no interrupt can wake the CPU up.
> > + */
> > + if (priority_mask) {
>
> [Severity: High]
> Does skipping the doorbell request when the priority is 0 break vNMI
> wakeups?
>
> Architectural semantics dictate that vNMIs have superpriority and
> must wake
> a vCPU even when the running priority is 0.
KVM does not expose FEAT_NMI to a guest, so this is not an issue.
>
> > + int db_irq = vgic_v5_vpe_db(vcpu);
> > + struct irq_data *d =
> > irq_get_irq_data(db_irq);
> > + const struct cpumask *aff =
> > irq_data_get_effective_affinity_mask(d);
> > + int cpu = smp_processor_id();
> > +
> > + dbpm = priority_mask - 1;
>
> [Severity: High]
> Does subtracting 1 from the priority mask drop valid preempting
> interrupts?
No. We discussed this last time. This is correct for GICv5, but
wouldn't be for GICv3.
>
> The hardware doorbell condition triggers when the pending priority is
> less
> than the threshold. If the highest active priority is 5, the vCPU
> should
> be woken by any interrupt with a priority less than 5, for example,
> 4.
>
> If the priority mask is 5, this code sets the DBPM to 4. The hardware
> condition then becomes priority < 4. An interrupt with priority 4
> will
> not signal the doorbell, despite having a higher priority than the
> active
> interrupt, causing missed wakeups and guest hangs.
>
> > + cpu_if->vgic_contextr =
> > FIELD_PREP(ICH_CONTEXTR_EL2_DB, 1) |
> > + FIELD_PREP(ICH_CON
> > TEXTR_EL2_DBPM, dbpm);
> [ ... ]
> > diff --git a/arch/arm64/kvm/vgic/vgic.c
> > b/arch/arm64/kvm/vgic/vgic.c
> > --- a/arch/arm64/kvm/vgic/vgic.c
> > +++ b/arch/arm64/kvm/vgic/vgic.c
> [ ... ]
> > @@ -1227,8 +1227,12 @@ int kvm_vgic_vcpu_pending_irq(struct
> > kvm_vcpu *vcpu)
> > unsigned long flags;
> > struct vgic_vmcr vmcr;
> >
> > - if (vgic_is_v5(vcpu->kvm))
> > + if (vgic_is_v5(vcpu->kvm)) {
> > + if (READ_ONCE(vcpu-
> > >arch.vgic_cpu.vgic_v5.gicv5_vpe.db_fired))
> > + return true;
>
> [Severity: High]
> Can a stale db_fired state cause an infinite loop bypassing WFI
> sleep?
>
> The db_fired flag is cleared only in __vgic_v5_make_non_resident(),
> which
> executes during schedule-out.
>
> If a doorbell fires, db_fired becomes true and the vCPU wakes up to
> enter
> the guest. When the vCPU subsequently re-enters WFI without a
> schedule-out,
> kvm_vcpu_block() evaluates kvm_vgic_vcpu_pending_irq(). Because
> db_fired
> remains true, this instantly returns without sleeping.
>
> This leaves the vCPU in an infinite loop returning from WFI and
> pegging
> the host CPU at 100% until a host timer tick forces preemption.
Entering WFI (when it is trapped to KVM) results in a vgic_v5_put()
which makes the VPE non-resident. At this point, it would be cleared.
In the event that we sleep in the guest, then we indeed won't call
vgic_v5_put() until we schedule out - but that is by design. We've
already chosen to sleep in the guest context at this point, but will
return to the host on a scheduler tick, at which point we take whatever
action is appropriate, such as making the VPE non-resident.
>
> > +
> > return vgic_v5_has_pending_ppi(vcpu);
> > + }
> >
> > if (!vcpu->kvm->arch.vgic.enabled)
> > return false;
>
Thanks,
Sascha
next prev parent reply other threads:[~2026-07-31 10:21 UTC|newest]
Thread overview: 125+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-24 10:48 [PATCH v4 00/48] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 01/48] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-07-24 11:21 ` sashiko-bot
2026-07-31 9:20 ` Sascha Bischoff
2026-07-24 10:48 ` [PATCH v4 02/48] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-07-24 11:10 ` sashiko-bot
2026-07-31 9:29 ` Sascha Bischoff
2026-07-25 9:06 ` Marc Zyngier
2026-07-25 9:18 ` Marc Zyngier
2026-07-24 10:49 ` [PATCH v4 03/48] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-25 10:08 ` Marc Zyngier
2026-07-28 12:14 ` Fuad Tabba
2026-07-31 7:18 ` Sascha Bischoff
2026-07-25 9:35 ` Marc Zyngier
2026-07-31 7:21 ` Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 04/48] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 05/48] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-07-24 10:49 ` [PATCH v4 06/48] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-07-24 11:14 ` sashiko-bot
2026-07-25 10:10 ` Marc Zyngier
2026-07-31 9:32 ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 07/48] KVM: arm64: gic-v5: Extract host IRS caps from IRS config frame Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-31 9:35 ` Sascha Bischoff
2026-07-25 10:40 ` Marc Zyngier
2026-07-31 7:24 ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 08/48] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-07-24 11:11 ` sashiko-bot
2026-07-31 9:33 ` Sascha Bischoff
2026-07-25 10:56 ` Marc Zyngier
2026-07-31 8:35 ` Sascha Bischoff
2026-07-24 10:50 ` [PATCH v4 09/48] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-07-24 11:19 ` sashiko-bot
2026-07-24 10:50 ` [PATCH v4 10/48] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-07-24 11:22 ` sashiko-bot
2026-07-27 16:39 ` Fuad Tabba
2026-07-27 17:55 ` Fuad Tabba
2026-07-31 9:11 ` Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 11/48] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-07-24 11:20 ` sashiko-bot
2026-07-24 10:51 ` [PATCH v4 12/48] KVM: arm64: gic-v5: Keep GICv5 vCPU limit model-specific Sascha Bischoff
2026-07-24 10:51 ` [PATCH v4 13/48] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-07-24 11:21 ` sashiko-bot
2026-07-31 13:15 ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 14/48] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-07-24 11:27 ` sashiko-bot
2026-07-31 10:17 ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 15/48] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-07-24 11:26 ` sashiko-bot
2026-07-31 13:16 ` Sascha Bischoff
2026-07-24 10:52 ` [PATCH v4 16/48] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-07-24 11:41 ` sashiko-bot
2026-07-31 10:20 ` Sascha Bischoff [this message]
2026-07-24 10:52 ` [PATCH v4 17/48] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 18/48] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 19/48] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-07-24 11:30 ` sashiko-bot
2026-07-31 10:22 ` Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 20/48] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-07-24 11:45 ` sashiko-bot
2026-07-27 18:34 ` Fuad Tabba
2026-07-30 16:06 ` Sascha Bischoff
2026-07-24 10:53 ` [PATCH v4 21/48] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 22/48] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-07-24 11:33 ` sashiko-bot
2026-07-31 13:05 ` Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 23/48] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-07-24 11:41 ` sashiko-bot
2026-07-31 13:32 ` Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 24/48] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-07-24 10:54 ` [PATCH v4 25/48] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-07-24 11:34 ` sashiko-bot
2026-07-31 13:18 ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 26/48] KVM: arm64: gic: Introduce set_pending_state() to irq_op Sascha Bischoff
2026-07-24 11:39 ` sashiko-bot
2026-07-31 13:37 ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 27/48] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-07-24 11:48 ` sashiko-bot
2026-07-31 13:49 ` Sascha Bischoff
2026-07-24 10:55 ` [PATCH v4 28/48] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-07-24 10:56 ` [PATCH v4 31/48] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-07-24 12:09 ` sashiko-bot
2026-07-31 14:27 ` Sascha Bischoff
2026-07-24 10:56 ` [PATCH v4 32/48] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-07-24 12:05 ` sashiko-bot
2026-07-31 14:42 ` Sascha Bischoff
2026-07-24 10:56 ` [PATCH v4 33/48] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 34/48] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI Sascha Bischoff
2026-07-24 11:46 ` sashiko-bot
2026-07-31 14:35 ` Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 35/48] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-07-24 12:02 ` sashiko-bot
2026-07-31 16:43 ` Sascha Bischoff
2026-07-27 18:56 ` Fuad Tabba
2026-07-31 8:55 ` Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 36/48] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-07-24 10:57 ` [PATCH v4 37/48] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-07-24 12:19 ` sashiko-bot
2026-07-31 14:46 ` Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 38/48] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-07-27 19:26 ` Fuad Tabba
2026-07-31 9:19 ` Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 39/48] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 40/48] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-07-24 10:58 ` [PATCH v4 41/48] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-07-24 12:02 ` sashiko-bot
2026-07-31 16:24 ` Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 42/48] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-07-24 12:06 ` sashiko-bot
2026-07-31 15:52 ` Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 43/48] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-07-24 10:59 ` [PATCH v4 44/48] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 45/48] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 46/48] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-07-24 12:15 ` sashiko-bot
2026-07-31 14:54 ` Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 47/48] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-07-24 12:18 ` sashiko-bot
2026-07-31 14:49 ` Sascha Bischoff
2026-07-24 11:00 ` [PATCH v4 48/48] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
[not found] ` <20260724104819.1296803-31-sascha.bischoff@arm.com>
2026-07-24 11:52 ` [PATCH v4 30/48] KVM: arm64: gic-v5: Mask per-vcpu PPI state in vgic_v5_finalize_ppi_state() sashiko-bot
2026-07-31 14:21 ` Sascha Bischoff
[not found] ` <20260724104819.1296803-30-sascha.bischoff@arm.com>
2026-07-24 12:19 ` [PATCH v4 29/48] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd sashiko-bot
2026-07-31 14:13 ` Sascha Bischoff
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