[PATCH 0/3] Add the missing mpll3 clock and clock controller nodes

[PATCH 0/3] Add the missing mpll3 clock and clock controller nodes

[Jian Hu]

- Fix a typo for gp1 pll
- Add the missing mpll3 parent clock definition to t7-peripherals-clkc.yaml
- Add Amlogic T7 SoC clock controller nodes

I have discussed with Ronald and agreed that I will first submit the T7 clock DTS,
and then he can proceed with his work.

Thanks to Ronald for pointing out the gp1 pll typo.

Jian Hu (3):
  dt-bindings: clock: amlogic: Fix a typo
  dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock
  arm64: dts: amlogic: t7: Add clock controller nodes

 .../clock/amlogic,t7-peripherals-clkc.yaml    |   8 +-
 .../bindings/clock/amlogic,t7-pll-clkc.yaml   |   2 +-
 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi   | 125 ++++++++++++++++++
 3 files changed, 132 insertions(+), 3 deletions(-)

-- 
2.47.1


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[PATCH 1/3] dt-bindings: clock: amlogic: Fix a typo

[Jian Hu]

Fix a typo for T7 gp1 pll.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
 .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
index 49c61f65deff..b488d92b7984 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
@@ -72,7 +72,7 @@ allOf:
           contains:
             enum:
               - amlogic,t7-gp0-pll
-              - amlogic,t7-gp1--pll
+              - amlogic,t7-gp1-pll
               - amlogic,t7-hifi-pll
               - amlogic,t7-pcie-pll
               - amlogic,t7-mpll
-- 
2.47.1


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[PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Jian Hu]

The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
Add it to enable proper clock parent configuration for these peripherals.

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
 .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
index 55bb73707d58..27cc1f331587 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
+++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
@@ -24,7 +24,7 @@ properties:
     const: 1
 
   clocks:
-    minItems: 14
+    minItems: 15
     items:
       - description: input oscillator
       - description: input sys clk
@@ -40,12 +40,13 @@ properties:
       - description: input gp1 pll
       - description: input mpll1
       - description: input mpll2
+      - description: input mpll3
       - description: external input rmii oscillator (optional)
       - description: input video pll0 (optional)
       - description: external pad input for rtc (optional)
 
   clock-names:
-    minItems: 14
+    minItems: 15
     items:
       - const: xtal
       - const: sys
@@ -61,6 +62,7 @@ properties:
       - const: gp1
       - const: mpll1
       - const: mpll2
+      - const: mpll3
       - const: ext_rmii
       - const: vid_pll0
       - const: ext_rtc
@@ -98,6 +100,7 @@ examples:
                      <&gp1 1>,
                      <&mpll 4>,
                      <&mpll 6>;
+                     <&mpll 8>;
             clock-names = "xtal",
                           "sys",
                           "fix",
@@ -112,5 +115,6 @@ examples:
                           "gp1",
                           "mpll1",
                           "mpll2";
+                          "mpll3";
         };
     };
-- 
2.47.1


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[PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Jian Hu]

Add the required clock controller nodes for Amlogic T7 SoC family:
- SCMI clock controller
- PLL clock controller
- Peripheral clock controller

Signed-off-by: Jian Hu <jian.hu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
 1 file changed, 125 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index 6510068bcff9..6ea1b583b13d 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -6,6 +6,9 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/amlogic,t7-pwrc.h>
 #include "amlogic-t7-reset.h"
+#include <dt-bindings/clock/amlogic,t7-scmi.h>
+#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -201,6 +204,33 @@ pwrc: power-controller {
 		};
 	};
 
+	sram@f7042000 {
+		compatible = "mmio-sram";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0xf7042000 0x100>;
+
+		scmi_shmem: sram@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x100>;
+		};
+	};
+
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x820000c1>;
+			shmem = <&scmi_shmem>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -224,6 +254,42 @@ apb4: bus@fe000000 {
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
 
+			clkc_periphs:clock-controller@0 {
+				compatible = "amlogic,t7-peripherals-clkc";
+				reg = <0x0 0x0 0x0 0x1c8>;
+				#clock-cells = <1>;
+				clocks = <&xtal>,
+					 <&scmi_clk CLKID_SYS_CLK>,
+					 <&scmi_clk CLKID_FIXED_PLL>,
+					 <&scmi_clk CLKID_FCLK_DIV2>,
+					 <&scmi_clk CLKID_FCLK_DIV2P5>,
+					 <&scmi_clk CLKID_FCLK_DIV3>,
+					 <&scmi_clk CLKID_FCLK_DIV4>,
+					 <&scmi_clk CLKID_FCLK_DIV5>,
+					 <&scmi_clk CLKID_FCLK_DIV7>,
+					 <&hifi CLKID_HIFI_PLL>,
+					 <&gp0 CLKID_GP0_PLL>,
+					 <&gp1 CLKID_GP1_PLL>,
+					 <&mpll CLKID_MPLL1>,
+					 <&mpll CLKID_MPLL2>,
+					 <&mpll CLKID_MPLL3>;
+				clock-names = "xtal",
+					      "sys",
+					      "fix",
+					      "fdiv2",
+					      "fdiv2p5",
+					      "fdiv3",
+					      "fdiv4",
+					      "fdiv5",
+					      "fdiv7",
+					      "hifi",
+					      "gp0",
+					      "gp1",
+					      "mpll1",
+					      "mpll2",
+					      "mpll3";
+			};
+
 			reset: reset-controller@2000 {
 				compatible = "amlogic,t7-reset";
 				reg = <0x0 0x2000 0x0 0x98>;
@@ -234,6 +300,7 @@ watchdog@2100 {
 				compatible = "amlogic,t7-wdt";
 				reg = <0x0 0x2100 0x0 0x10>;
 				clocks = <&xtal>;
+
 			};
 
 			periphs_pinctrl: pinctrl@4000 {
@@ -269,6 +336,64 @@ uart_a: serial@78000 {
 				status = "disabled";
 			};
 
+			gp0:clock-controller@8080 {
+				compatible = "amlogic,t7-gp0-pll";
+				reg = <0x0 0x8080 0x0 0x20>;
+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			gp1:clock-controller@80c0 {
+				compatible = "amlogic,t7-gp1-pll";
+				reg = <0x0 0x80c0 0x0 0x14>;
+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			hifi:clock-controller@8100 {
+				compatible = "amlogic,t7-hifi-pll";
+				reg = <0x0 0x8100 0x0 0x20>;
+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			pcie:clock-controller@8140 {
+				compatible = "amlogic,t7-pcie-pll";
+				reg = <0x0 0x8140 0x0 0x1c>;
+				clocks = <&scmi_clk CLKID_PCIE_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			mpll:clock-controller@8180 {
+				compatible = "amlogic,t7-mpll";
+				reg = <0x0 0x8180 0x0 0x28>;
+				clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			hdmi:clock-controller@81c0 {
+				compatible = "amlogic,t7-hdmi-pll";
+				reg = <0x0 0x81c0 0x0 0x20>;
+				clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			mclk:clock-controller@8300 {
+				compatible = "amlogic,t7-mclk-pll";
+				reg = <0x0 0x8300 0x0 0x18>;
+				clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
+					 <&xtal>,
+					 <&scmi_clk CLKID_FCLK_50M>;
+				clock-names = "in0", "in1", "in2";
+				#clock-cells = <1>;
+			};
+
 			sec_ao: ao-secure@10220 {
 				compatible = "amlogic,t7-ao-secure",
 					     "amlogic,meson-gx-ao-secure",
-- 
2.47.1


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Re: [PATCH 1/3] dt-bindings: clock: amlogic: Fix a typo

[Jerome Brunet]

On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:

> Fix a typo for T7 gp1 pll.

Patch title is too vague

Credit is due to Ronald for finding and reporting the issue initially.
This can be viewed as a clean of his original patch so the change should
have his Signed-off-by IMO.

>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml          | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> index 49c61f65deff..b488d92b7984 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> @@ -72,7 +72,7 @@ allOf:
>            contains:
>              enum:
>                - amlogic,t7-gp0-pll
> -              - amlogic,t7-gp1--pll
> +              - amlogic,t7-gp1-pll
>                - amlogic,t7-hifi-pll
>                - amlogic,t7-pcie-pll
>                - amlogic,t7-mpll

-- 
Jerome

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Jerome Brunet]

On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:

> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
> Add it to enable proper clock parent configuration for these peripherals.

... but this changes the index of the clocks after this mpll3, and those
index are supposed to be stable if I'm not mistaken.

It is indeed more convenient to have the optional clocks at the end
as it avoids writing multiple <0> in DT when we do not have them.

At the very least, your commit description should say that this change
will not break any existing DT because these bindings are not used yet.

I leave it to the DT folks to say if the change is OK in such case.

>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
> index 55bb73707d58..27cc1f331587 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
> @@ -24,7 +24,7 @@ properties:
>      const: 1
>  
>    clocks:
> -    minItems: 14
> +    minItems: 15
>      items:
>        - description: input oscillator
>        - description: input sys clk
> @@ -40,12 +40,13 @@ properties:
>        - description: input gp1 pll
>        - description: input mpll1
>        - description: input mpll2
> +      - description: input mpll3
>        - description: external input rmii oscillator (optional)
>        - description: input video pll0 (optional)
>        - description: external pad input for rtc (optional)
>  
>    clock-names:
> -    minItems: 14
> +    minItems: 15
>      items:
>        - const: xtal
>        - const: sys
> @@ -61,6 +62,7 @@ properties:
>        - const: gp1
>        - const: mpll1
>        - const: mpll2
> +      - const: mpll3
>        - const: ext_rmii
>        - const: vid_pll0
>        - const: ext_rtc
> @@ -98,6 +100,7 @@ examples:
>                       <&gp1 1>,
>                       <&mpll 4>,
>                       <&mpll 6>;
> +                     <&mpll 8>;
>              clock-names = "xtal",
>                            "sys",
>                            "fix",
> @@ -112,5 +115,6 @@ examples:
>                            "gp1",
>                            "mpll1",
>                            "mpll2";
> +                          "mpll3";
>          };
>      };

-- 
Jerome

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Jerome Brunet]

On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:

> Add the required clock controller nodes for Amlogic T7 SoC family:
> - SCMI clock controller
> - PLL clock controller
> - Peripheral clock controller
>

Again I think you should credit Ronald.

> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
>  1 file changed, 125 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> index 6510068bcff9..6ea1b583b13d 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> @@ -6,6 +6,9 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/amlogic,t7-pwrc.h>
>  #include "amlogic-t7-reset.h"
> +#include <dt-bindings/clock/amlogic,t7-scmi.h>
> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
> +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
>  
>  / {
>  	interrupt-parent = <&gic>;
> @@ -201,6 +204,33 @@ pwrc: power-controller {
>  		};
>  	};
>  
> +	sram@f7042000 {
> +		compatible = "mmio-sram";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x0 0xf7042000 0x100>;
> +
> +		scmi_shmem: sram@0 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0x100>;
> +		};
> +	};
> +
> +	firmware {
> +		scmi: scmi {
> +			compatible = "arm,scmi-smc";
> +			arm,smc-id = <0x820000c1>;
> +			shmem = <&scmi_shmem>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			scmi_clk: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +	};
> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;
> @@ -224,6 +254,42 @@ apb4: bus@fe000000 {
>  			#size-cells = <2>;
>  			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>  
> +			clkc_periphs:clock-controller@0 {
> +				compatible = "amlogic,t7-peripherals-clkc";
> +				reg = <0x0 0x0 0x0 0x1c8>;
> +				#clock-cells = <1>;
> +				clocks = <&xtal>,
> +					 <&scmi_clk CLKID_SYS_CLK>,
> +					 <&scmi_clk CLKID_FIXED_PLL>,
> +					 <&scmi_clk CLKID_FCLK_DIV2>,
> +					 <&scmi_clk CLKID_FCLK_DIV2P5>,
> +					 <&scmi_clk CLKID_FCLK_DIV3>,
> +					 <&scmi_clk CLKID_FCLK_DIV4>,
> +					 <&scmi_clk CLKID_FCLK_DIV5>,
> +					 <&scmi_clk CLKID_FCLK_DIV7>,
> +					 <&hifi CLKID_HIFI_PLL>,
> +					 <&gp0 CLKID_GP0_PLL>,
> +					 <&gp1 CLKID_GP1_PLL>,
> +					 <&mpll CLKID_MPLL1>,
> +					 <&mpll CLKID_MPLL2>,
> +					 <&mpll CLKID_MPLL3>;
> +				clock-names = "xtal",
> +					      "sys",
> +					      "fix",
> +					      "fdiv2",
> +					      "fdiv2p5",
> +					      "fdiv3",
> +					      "fdiv4",
> +					      "fdiv5",
> +					      "fdiv7",
> +					      "hifi",
> +					      "gp0",
> +					      "gp1",
> +					      "mpll1",
> +					      "mpll2",
> +					      "mpll3";
> +			};
> +
>  			reset: reset-controller@2000 {
>  				compatible = "amlogic,t7-reset";
>  				reg = <0x0 0x2000 0x0 0x98>;
> @@ -234,6 +300,7 @@ watchdog@2100 {
>  				compatible = "amlogic,t7-wdt";
>  				reg = <0x0 0x2100 0x0 0x10>;
>  				clocks = <&xtal>;
> +
>  			};
>  
>  			periphs_pinctrl: pinctrl@4000 {
> @@ -269,6 +336,64 @@ uart_a: serial@78000 {
>  				status = "disabled";
>  			};
>  
> +			gp0:clock-controller@8080 {
> +				compatible = "amlogic,t7-gp0-pll";
> +				reg = <0x0 0x8080 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			gp1:clock-controller@80c0 {
> +				compatible = "amlogic,t7-gp1-pll";
> +				reg = <0x0 0x80c0 0x0 0x14>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			hifi:clock-controller@8100 {
> +				compatible = "amlogic,t7-hifi-pll";
> +				reg = <0x0 0x8100 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			pcie:clock-controller@8140 {
> +				compatible = "amlogic,t7-pcie-pll";
> +				reg = <0x0 0x8140 0x0 0x1c>;
> +				clocks = <&scmi_clk CLKID_PCIE_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			mpll:clock-controller@8180 {
> +				compatible = "amlogic,t7-mpll";
> +				reg = <0x0 0x8180 0x0 0x28>;
> +				clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			hdmi:clock-controller@81c0 {
> +				compatible = "amlogic,t7-hdmi-pll";
> +				reg = <0x0 0x81c0 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			mclk:clock-controller@8300 {
> +				compatible = "amlogic,t7-mclk-pll";
> +				reg = <0x0 0x8300 0x0 0x18>;
> +				clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
> +					 <&xtal>,
> +					 <&scmi_clk CLKID_FCLK_50M>;
> +				clock-names = "in0", "in1", "in2";
> +				#clock-cells = <1>;
> +			};
> +
>  			sec_ao: ao-secure@10220 {
>  				compatible = "amlogic,t7-ao-secure",
>  					     "amlogic,meson-gx-ao-secure",

-- 
Jerome

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Rob Herring (Arm)]

On Thu, 05 Mar 2026 15:43:26 +0800, Jian Hu wrote:
> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
> Add it to enable proper clock parent configuration for these peripherals.
> 
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.example.dts:40.26-27 syntax error
FATAL ERROR: Unable to parse input tree
make[2]: *** [scripts/Makefile.dtbs:140: Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.example.dtb] Error 1
make[2]: *** Waiting for unfinished jobs....
make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1597: dt_binding_check] Error 2
make: *** [Makefile:248: __sub-make] Error 2

doc reference errors (make refcheckdocs):

See https://patchwork.kernel.org/project/devicetree/patch/20260305074328.639993-3-jian.hu@amlogic.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


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Re: [PATCH 1/3] dt-bindings: clock: amlogic: Fix a typo

[Jian Hu]

Hi, Jerome


Thanks for your review.

On 3/5/2026 4:57 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:
>
>> Fix a typo for T7 gp1 pll.
> Patch title is too vague
>
> Credit is due to Ronald for finding and reporting the issue initially.
> This can be viewed as a clean of his original patch so the change should
> have his Signed-off-by IMO.


OK, I will update the patch title to:

Fix redundant hyphen in "amlogic,t7-gp1--pll" string.

Thanks to Ronald for finding and reporting this issue.

I had obtained his consent before submitting this patch.

I agree with you and will add his Signed-off-by in the next version.

>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml          | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> index 49c61f65deff..b488d92b7984 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> @@ -72,7 +72,7 @@ allOf:
>>             contains:
>>               enum:
>>                 - amlogic,t7-gp0-pll
>> -              - amlogic,t7-gp1--pll
>> +              - amlogic,t7-gp1-pll
>>                 - amlogic,t7-hifi-pll
>>                 - amlogic,t7-pcie-pll
>>                 - amlogic,t7-mpll
> --
> Jerome

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Jian Hu]

On 3/5/2026 5:03 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:
>
>> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
>> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
>> Add it to enable proper clock parent configuration for these peripherals.
> ... but this changes the index of the clocks after this mpll3, and those
> index are supposed to be stable if I'm not mistaken.
>
> It is indeed more convenient to have the optional clocks at the end
> as it avoids writing multiple <0> in DT when we do not have them.
>
> At the very least, your commit description should say that this change
> will not break any existing DT because these bindings are not used yet.
>
> I leave it to the DT folks to say if the change is OK in such case.

You are right. I will add a commit description to explain this.

The clock controller node for amlogic,t7-peripherals-clkc has not been 
merged upstream yet.

This change modifies the clock index order, but it will not break any 
existing device tree

since the amlogic,t7-peripherals-clkc bindings are not used by any 
upstream or downstream DT yet.

I will send a v2 with an updated commit message.

>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>>   1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>> index 55bb73707d58..27cc1f331587 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>> @@ -24,7 +24,7 @@ properties:
>>       const: 1
>>
>>     clocks:
>> -    minItems: 14
>> +    minItems: 15
>>       items:
>>         - description: input oscillator
>>         - description: input sys clk
>> @@ -40,12 +40,13 @@ properties:
>>         - description: input gp1 pll
>>         - description: input mpll1
>>         - description: input mpll2
>> +      - description: input mpll3
>>         - description: external input rmii oscillator (optional)
>>         - description: input video pll0 (optional)
>>         - description: external pad input for rtc (optional)
>>
>>     clock-names:
>> -    minItems: 14
>> +    minItems: 15
>>       items:
>>         - const: xtal
>>         - const: sys
>> @@ -61,6 +62,7 @@ properties:
>>         - const: gp1
>>         - const: mpll1
>>         - const: mpll2
>> +      - const: mpll3
>>         - const: ext_rmii
>>         - const: vid_pll0
>>         - const: ext_rtc
>> @@ -98,6 +100,7 @@ examples:
>>                        <&gp1 1>,
>>                        <&mpll 4>,
>>                        <&mpll 6>;
>> +                     <&mpll 8>;
>>               clock-names = "xtal",
>>                             "sys",
>>                             "fix",
>> @@ -112,5 +115,6 @@ examples:
>>                             "gp1",
>>                             "mpll1",
>>                             "mpll2";
>> +                          "mpll3";
>>           };
>>       };
> --
> Jerome

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Jian Hu]

On 3/5/2026 5:04 PM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:
>
>> Add the required clock controller nodes for Amlogic T7 SoC family:
>> - SCMI clock controller
>> - PLL clock controller
>> - Peripheral clock controller
>>
> Again I think you should credit Ronald.


Sure, I will add Ronald's Signed-off-by for this patch in v2. Thanks for 
the reminder.

>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
>>   1 file changed, 125 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> index 6510068bcff9..6ea1b583b13d 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
[...]
> --
> Jerome

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Ronald Claveau]

On 3/5/26 8:43 AM, Jian Hu wrote:
> Add the required clock controller nodes for Amlogic T7 SoC family:
> - SCMI clock controller
> - PLL clock controller
> - Peripheral clock controller
> 
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
>  1 file changed, 125 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> index 6510068bcff9..6ea1b583b13d 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> @@ -6,6 +6,9 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/amlogic,t7-pwrc.h>
>  #include "amlogic-t7-reset.h"
> +#include <dt-bindings/clock/amlogic,t7-scmi.h>
> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
> +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
>  
>  / {
>  	interrupt-parent = <&gic>;
> @@ -201,6 +204,33 @@ pwrc: power-controller {
>  		};
>  	};
>  
> +	sram@f7042000 {
> +		compatible = "mmio-sram";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x0 0xf7042000 0x100>;
> +
> +		scmi_shmem: sram@0 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0x100>;
> +		};
> +	};
> +
> +	firmware {
> +		scmi: scmi {
> +			compatible = "arm,scmi-smc";
> +			arm,smc-id = <0x820000c1>;
> +			shmem = <&scmi_shmem>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			scmi_clk: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +	};
> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;
> @@ -224,6 +254,42 @@ apb4: bus@fe000000 {
>  			#size-cells = <2>;
>  			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>  
> +			clkc_periphs:clock-controller@0 {
> +				compatible = "amlogic,t7-peripherals-clkc";
> +				reg = <0x0 0x0 0x0 0x1c8>;
> +				#clock-cells = <1>;
> +				clocks = <&xtal>,
> +					 <&scmi_clk CLKID_SYS_CLK>,
> +					 <&scmi_clk CLKID_FIXED_PLL>,
> +					 <&scmi_clk CLKID_FCLK_DIV2>,
> +					 <&scmi_clk CLKID_FCLK_DIV2P5>,
> +					 <&scmi_clk CLKID_FCLK_DIV3>,
> +					 <&scmi_clk CLKID_FCLK_DIV4>,
> +					 <&scmi_clk CLKID_FCLK_DIV5>,
> +					 <&scmi_clk CLKID_FCLK_DIV7>,
> +					 <&hifi CLKID_HIFI_PLL>,
> +					 <&gp0 CLKID_GP0_PLL>,
> +					 <&gp1 CLKID_GP1_PLL>,
> +					 <&mpll CLKID_MPLL1>,
> +					 <&mpll CLKID_MPLL2>,
> +					 <&mpll CLKID_MPLL3>;
> +				clock-names = "xtal",
> +					      "sys",
> +					      "fix",
> +					      "fdiv2",
> +					      "fdiv2p5",
> +					      "fdiv3",
> +					      "fdiv4",
> +					      "fdiv5",
> +					      "fdiv7",
> +					      "hifi",
> +					      "gp0",
> +					      "gp1",
> +					      "mpll1",
> +					      "mpll2",
> +					      "mpll3";
> +			};
> +
>  			reset: reset-controller@2000 {
>  				compatible = "amlogic,t7-reset";
>  				reg = <0x0 0x2000 0x0 0x98>;
> @@ -234,6 +300,7 @@ watchdog@2100 {
>  				compatible = "amlogic,t7-wdt";
>  				reg = <0x0 0x2100 0x0 0x10>;
>  				clocks = <&xtal>;
> +
>  			};

Did you forget to add something here for watchdog ?
If not I think you can remove that blank line.

>  
>  			periphs_pinctrl: pinctrl@4000 {
> @@ -269,6 +336,64 @@ uart_a: serial@78000 {
>  				status = "disabled";
>  			};
>  
> +			gp0:clock-controller@8080 {
> +				compatible = "amlogic,t7-gp0-pll";
> +				reg = <0x0 0x8080 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			gp1:clock-controller@80c0 {
> +				compatible = "amlogic,t7-gp1-pll";
> +				reg = <0x0 0x80c0 0x0 0x14>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			hifi:clock-controller@8100 {
> +				compatible = "amlogic,t7-hifi-pll";
> +				reg = <0x0 0x8100 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			pcie:clock-controller@8140 {
> +				compatible = "amlogic,t7-pcie-pll";
> +				reg = <0x0 0x8140 0x0 0x1c>;
> +				clocks = <&scmi_clk CLKID_PCIE_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			mpll:clock-controller@8180 {
> +				compatible = "amlogic,t7-mpll";
> +				reg = <0x0 0x8180 0x0 0x28>;
> +				clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			hdmi:clock-controller@81c0 {
> +				compatible = "amlogic,t7-hdmi-pll";
> +				reg = <0x0 0x81c0 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			mclk:clock-controller@8300 {
> +				compatible = "amlogic,t7-mclk-pll";
> +				reg = <0x0 0x8300 0x0 0x18>;
> +				clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
> +					 <&xtal>,
> +					 <&scmi_clk CLKID_FCLK_50M>;
> +				clock-names = "in0", "in1", "in2";
> +				#clock-cells = <1>;
> +			};
> +
>  			sec_ao: ao-secure@10220 {
>  				compatible = "amlogic,t7-ao-secure",
>  					     "amlogic,meson-gx-ao-secure",


-- 
Best regards,
Ronald

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Jian Hu]

Hi, rob


Thanks for your review.

On 3/5/2026 9:45 PM, Rob Herring (Arm) wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, 05 Mar 2026 15:43:26 +0800, Jian Hu wrote:
>> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
>> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
>> Add it to enable proper clock parent configuration for these peripherals.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>>   1 file changed, 6 insertions(+), 2 deletions(-)
>>
> My bot found errors running 'make dt_binding_check' on your patch:
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> Error: Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.example.dts:40.26-27 syntax error
> FATAL ERROR: Unable to parse input tree
> make[2]: *** [scripts/Makefile.dtbs:140: Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.example.dtb] Error 1
> make[2]: *** Waiting for unfinished jobs....
> make[1]: *** [/builds/robherring/dt-review-ci/linux/Makefile:1597: dt_binding_check] Error 2
> make: *** [Makefile:248: __sub-make] Error 2


I will fix the DTS syntax issue in 
Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.example.dts 
(line 40)

and include this fix in the v2 patch, along with the previously 
discussed updated commit description.

> doc reference errors (make refcheckdocs):
>
> See https://patchwork.kernel.org/project/devicetree/patch/20260305074328.639993-3-jian.hu@amlogic.com
>
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
>

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Jian Hu]

Hi, Ronald


Thanks for you review.

On 3/6/2026 3:47 PM, Ronald Claveau wrote:
> [ EXTERNAL EMAIL ]
>
> On 3/5/26 8:43 AM, Jian Hu wrote:
>> Add the required clock controller nodes for Amlogic T7 SoC family:
>> - SCMI clock controller
>> - PLL clock controller
>> - Peripheral clock controller
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
>>   1 file changed, 125 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> index 6510068bcff9..6ea1b583b13d 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -6,6 +6,9 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/power/amlogic,t7-pwrc.h>
>>   #include "amlogic-t7-reset.h"
>> +#include <dt-bindings/clock/amlogic,t7-scmi.h>
>> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
>> +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
>>
>>   / {
>>        interrupt-parent = <&gic>;
>> @@ -201,6 +204,33 @@ pwrc: power-controller {
>>                };
>>        };
>>
>> +     sram@f7042000 {
>> +             compatible = "mmio-sram";
>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             ranges = <0 0x0 0xf7042000 0x100>;
>> +
>> +             scmi_shmem: sram@0 {
>> +                     compatible = "arm,scmi-shmem";
>> +                     reg = <0x0 0x100>;
>> +             };
>> +     };
>> +
>> +     firmware {
>> +             scmi: scmi {
>> +                     compatible = "arm,scmi-smc";
>> +                     arm,smc-id = <0x820000c1>;
>> +                     shmem = <&scmi_shmem>;
>> +                     #address-cells = <1>;
>> +                     #size-cells = <0>;
>> +
>> +                     scmi_clk: protocol@14 {
>> +                             reg = <0x14>;
>> +                             #clock-cells = <1>;
>> +                     };
>> +             };
>> +     };
>> +
>>        soc {
>>                compatible = "simple-bus";
>>                #address-cells = <2>;
>> @@ -224,6 +254,42 @@ apb4: bus@fe000000 {
>>                        #size-cells = <2>;
>>                        ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>>
>> +                     clkc_periphs:clock-controller@0 {
>> +                             compatible = "amlogic,t7-peripherals-clkc";
>> +                             reg = <0x0 0x0 0x0 0x1c8>;
>> +                             #clock-cells = <1>;
>> +                             clocks = <&xtal>,
>> +                                      <&scmi_clk CLKID_SYS_CLK>,
>> +                                      <&scmi_clk CLKID_FIXED_PLL>,
>> +                                      <&scmi_clk CLKID_FCLK_DIV2>,
>> +                                      <&scmi_clk CLKID_FCLK_DIV2P5>,
>> +                                      <&scmi_clk CLKID_FCLK_DIV3>,
>> +                                      <&scmi_clk CLKID_FCLK_DIV4>,
>> +                                      <&scmi_clk CLKID_FCLK_DIV5>,
>> +                                      <&scmi_clk CLKID_FCLK_DIV7>,
>> +                                      <&hifi CLKID_HIFI_PLL>,
>> +                                      <&gp0 CLKID_GP0_PLL>,
>> +                                      <&gp1 CLKID_GP1_PLL>,
>> +                                      <&mpll CLKID_MPLL1>,
>> +                                      <&mpll CLKID_MPLL2>,
>> +                                      <&mpll CLKID_MPLL3>;
>> +                             clock-names = "xtal",
>> +                                           "sys",
>> +                                           "fix",
>> +                                           "fdiv2",
>> +                                           "fdiv2p5",
>> +                                           "fdiv3",
>> +                                           "fdiv4",
>> +                                           "fdiv5",
>> +                                           "fdiv7",
>> +                                           "hifi",
>> +                                           "gp0",
>> +                                           "gp1",
>> +                                           "mpll1",
>> +                                           "mpll2",
>> +                                           "mpll3";
>> +                     };
>> +
>>                        reset: reset-controller@2000 {
>>                                compatible = "amlogic,t7-reset";
>>                                reg = <0x0 0x2000 0x0 0x98>;
>> @@ -234,6 +300,7 @@ watchdog@2100 {
>>                                compatible = "amlogic,t7-wdt";
>>                                reg = <0x0 0x2100 0x0 0x10>;
>>                                clocks = <&xtal>;
>> +
>>                        };
> Did you forget to add something here for watchdog ?
> If not I think you can remove that blank line.

It's an accidental addition (no missing content for the watchdog), so 
I'll remove it in v2.

Thanks for pointing it out!

>>                        periphs_pinctrl: pinctrl@4000 {
>> @@ -269,6 +336,64 @@ uart_a: serial@78000 {
>>                                status = "disabled";
>>                        };
>>
>> +                     gp0:clock-controller@8080 {
>> +                             compatible = "amlogic,t7-gp0-pll";
>> +                             reg = <0x0 0x8080 0x0 0x20>;
>> +                             clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>> +                             clock-names = "in0";
>> +                             #clock-cells = <1>;
>> +                     };
>> +
>> +                     gp1:clock-controller@80c0 {
>> +                             compatible = "amlogic,t7-gp1-pll";
>> +                             reg = <0x0 0x80c0 0x0 0x14>;
>> +                             clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>> +                             clock-names = "in0";
>> +                             #clock-cells = <1>;
>> +                     };
>> +
>> +                     hifi:clock-controller@8100 {
>> +                             compatible = "amlogic,t7-hifi-pll";
>> +                             reg = <0x0 0x8100 0x0 0x20>;
>> +                             clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>> +                             clock-names = "in0";
>> +                             #clock-cells = <1>;
>> +                     };
>> +
>> +                     pcie:clock-controller@8140 {
>> +                             compatible = "amlogic,t7-pcie-pll";
>> +                             reg = <0x0 0x8140 0x0 0x1c>;
>> +                             clocks = <&scmi_clk CLKID_PCIE_OSC>;
>> +                             clock-names = "in0";
>> +                             #clock-cells = <1>;
>> +                     };
>> +
>> +                     mpll:clock-controller@8180 {
>> +                             compatible = "amlogic,t7-mpll";
>> +                             reg = <0x0 0x8180 0x0 0x28>;
>> +                             clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
>> +                             clock-names = "in0";
>> +                             #clock-cells = <1>;
>> +                     };
>> +
>> +                     hdmi:clock-controller@81c0 {
>> +                             compatible = "amlogic,t7-hdmi-pll";
>> +                             reg = <0x0 0x81c0 0x0 0x20>;
>> +                             clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
>> +                             clock-names = "in0";
>> +                             #clock-cells = <1>;
>> +                     };
>> +
>> +                     mclk:clock-controller@8300 {
>> +                             compatible = "amlogic,t7-mclk-pll";
>> +                             reg = <0x0 0x8300 0x0 0x18>;
>> +                             clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
>> +                                      <&xtal>,
>> +                                      <&scmi_clk CLKID_FCLK_50M>;
>> +                             clock-names = "in0", "in1", "in2";
>> +                             #clock-cells = <1>;
>> +                     };
>> +
>>                        sec_ao: ao-secure@10220 {
>>                                compatible = "amlogic,t7-ao-secure",
>>                                             "amlogic,meson-gx-ao-secure",
>
> --
> Best regards,
> Ronald

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Re: [PATCH 1/3] dt-bindings: clock: amlogic: Fix a typo

[Krzysztof Kozlowski]

On Thu, Mar 05, 2026 at 03:43:25PM +0800, Jian Hu wrote:
> Fix a typo for T7 gp1 pll.
> 

And also Fixes tag.

> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml          | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> index 49c61f65deff..b488d92b7984 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
> @@ -72,7 +72,7 @@ allOf:
>            contains:
>              enum:
>                - amlogic,t7-gp0-pll
> -              - amlogic,t7-gp1--pll
> +              - amlogic,t7-gp1-pll
>                - amlogic,t7-hifi-pll
>                - amlogic,t7-pcie-pll
>                - amlogic,t7-mpll
> -- 
> 2.47.1
> 

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Krzysztof Kozlowski]

On Thu, Mar 05, 2026 at 03:43:26PM +0800, Jian Hu wrote:
> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
> Add it to enable proper clock parent configuration for these peripherals.
> 
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
> index 55bb73707d58..27cc1f331587 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
> @@ -24,7 +24,7 @@ properties:
>      const: 1
>  
>    clocks:
> -    minItems: 14
> +    minItems: 15
>      items:
>        - description: input oscillator
>        - description: input sys clk
> @@ -40,12 +40,13 @@ properties:
>        - description: input gp1 pll
>        - description: input mpll1
>        - description: input mpll2
> +      - description: input mpll3

Nah, ABI break. You add it to the end of the list or provide arguments
on ABI impact.

Best regards,
Krzysztof


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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Krzysztof Kozlowski]

On Thu, Mar 05, 2026 at 10:03:32AM +0100, Jerome Brunet wrote:
> On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:
> 
> > The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
> > the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
> > Add it to enable proper clock parent configuration for these peripherals.
> 
> ... but this changes the index of the clocks after this mpll3, and those
> index are supposed to be stable if I'm not mistaken.
> 
> It is indeed more convenient to have the optional clocks at the end
> as it avoids writing multiple <0> in DT when we do not have them.
> 
> At the very least, your commit description should say that this change
> will not break any existing DT because these bindings are not used yet.
> 
> I leave it to the DT folks to say if the change is OK in such case.

Based on commit msg it is not OK, that's why we ask about explaining
true problem and actual impact, IOW whether this did not work in the
first place and authors did not bother to test it...

Best regards,
Krzysztof


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Re: [PATCH 1/3] dt-bindings: clock: amlogic: Fix a typo

[Jian Hu]

Hi, Krzysztof


Thanks for your review.

On 3/6/2026 4:11 PM, Krzysztof Kozlowski wrote:
> [You don't often get email from krzk@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> [ EXTERNAL EMAIL ]
>
> On Thu, Mar 05, 2026 at 03:43:25PM +0800, Jian Hu wrote:
>> Fix a typo for T7 gp1 pll.
>>
> And also Fixes tag.


Ok, I will add the Fixes tag:

Fixes: 5437753728ac ("dt-bindings: clock: add Amlogic T7 PLL clock 
controller")

>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   .../devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml          | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> index 49c61f65deff..b488d92b7984 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml
>> @@ -72,7 +72,7 @@ allOf:
>>             contains:
>>               enum:
>>                 - amlogic,t7-gp0-pll
>> -              - amlogic,t7-gp1--pll
>> +              - amlogic,t7-gp1-pll
>>                 - amlogic,t7-hifi-pll
>>                 - amlogic,t7-pcie-pll
>>                 - amlogic,t7-mpll
>> --
>> 2.47.1
>>

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Jian Hu]

On 3/6/2026 4:12 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, Mar 05, 2026 at 03:43:26PM +0800, Jian Hu wrote:
>> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
>> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
>> Add it to enable proper clock parent configuration for these peripherals.
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>>   1 file changed, 6 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>> index 55bb73707d58..27cc1f331587 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>> @@ -24,7 +24,7 @@ properties:
>>       const: 1
>>
>>     clocks:
>> -    minItems: 14
>> +    minItems: 15
>>       items:
>>         - description: input oscillator
>>         - description: input sys clk
>> @@ -40,12 +40,13 @@ properties:
>>         - description: input gp1 pll
>>         - description: input mpll1
>>         - description: input mpll2
>> +      - description: input mpll3
> Nah, ABI break. You add it to the end of the list or provide arguments
> on ABI impact.

The third patch in this series enables the DT for the Amlogic T7 clock 
controller.

The clock controller node for amlogic,t7-peripherals-clkc has not been 
merged upstream yet.
This change modifies the clock index order, but it will not break any 
existing device tree since the
amlogic,t7-peripherals-clkc bindings are not used by any upstream or 
downstream DT at this time.

Therefore, it does NOT break the ABI.

The last clock entry is an external pad input for RTC and it is optional.
For logical consistency, it is better to place the required mpll3 entry 
before the optional entry.

If this change does not break the ABI, could I keep it in its original 
logical order right after mpll2?
> Best regards,
> Krzysztof
>

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Krzysztof Kozlowski]

On 10/03/2026 07:51, Jian Hu wrote:
> 
> On 3/6/2026 4:12 PM, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On Thu, Mar 05, 2026 at 03:43:26PM +0800, Jian Hu wrote:
>>> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
>>> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
>>> Add it to enable proper clock parent configuration for these peripherals.
>>>
>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>> ---
>>>   .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>>>   1 file changed, 6 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>>> index 55bb73707d58..27cc1f331587 100644
>>> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>>> @@ -24,7 +24,7 @@ properties:
>>>       const: 1
>>>
>>>     clocks:
>>> -    minItems: 14
>>> +    minItems: 15
>>>       items:
>>>         - description: input oscillator
>>>         - description: input sys clk
>>> @@ -40,12 +40,13 @@ properties:
>>>         - description: input gp1 pll
>>>         - description: input mpll1
>>>         - description: input mpll2
>>> +      - description: input mpll3
>> Nah, ABI break. You add it to the end of the list or provide arguments
>> on ABI impact.
> 
> The third patch in this series enables the DT for the Amlogic T7 clock 
> controller.
> 
> The clock controller node for amlogic,t7-peripherals-clkc has not been 
> merged upstream yet.
> This change modifies the clock index order, but it will not break any 
> existing device tree since the
> amlogic,t7-peripherals-clkc bindings are not used by any upstream or 
> downstream DT at this time.
> 
> Therefore, it does NOT break the ABI.

It does. Clearly visible from the diff above, because the order is the ABI.

> 
> The last clock entry is an external pad input for RTC and it is optional.
> For logical consistency, it is better to place the required mpll3 entry 
> before the optional entry.
> 
> If this change does not break the ABI, could I keep it in its original 
> logical order right after mpll2?

Change breaks the ABI and commit must explain why and the impact.


Best regards,
Krzysztof

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Jian Hu]

On 3/6/2026 4:14 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On Thu, Mar 05, 2026 at 10:03:32AM +0100, Jerome Brunet wrote:
>> On jeu. 05 mars 2026 at 15:43, Jian Hu <jian.hu@amlogic.com> wrote:
>>
>>> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
>>> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
>>> Add it to enable proper clock parent configuration for these peripherals.
>> ... but this changes the index of the clocks after this mpll3, and those
>> index are supposed to be stable if I'm not mistaken.
>>
>> It is indeed more convenient to have the optional clocks at the end
>> as it avoids writing multiple <0> in DT when we do not have them.
>>
>> At the very least, your commit description should say that this change
>> will not break any existing DT because these bindings are not used yet.
>>
>> I leave it to the DT folks to say if the change is OK in such case.
> Based on commit msg it is not OK, that's why we ask about explaining
> true problem and actual impact, IOW whether this did not work in the
> first place and authors did not bother to test it...


Thank you for the clarification and explanation.

mpll3 is one of the clock sources for sd_emmc, and this use case was 
indeed not verified in the initial version.

mpll3 is typically used by the audio module and is one of the required 
clock sources for the audio clock driver.

In practice, sd_emmc does not use mpll3.
During testing, only the other clock sources of sd_emmc were verified: 
fdivx, gp0, hifi.
I apologize for this oversight.

Even though sd_emmc does not use mpll3, the clock driver should still 
support it as a valid clock source.

Additionally, I have confirmed that all required clock sources are 
defined in the T7 peripheral device tree.

I will update the commit message to state that this change does not 
affect the ABI.
> Best regards,
> Krzysztof
>

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Re: [PATCH 2/3] dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock

[Jian Hu]

On 3/10/2026 3:08 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 10/03/2026 07:51, Jian Hu wrote:
>> On 3/6/2026 4:12 PM, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Thu, Mar 05, 2026 at 03:43:26PM +0800, Jian Hu wrote:
>>>> The mpll3 clock is a valid parent clock for sd_emmc and mipi_isp on
>>>> the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
>>>> Add it to enable proper clock parent configuration for these peripherals.
>>>>
>>>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>>>> ---
>>>>    .../bindings/clock/amlogic,t7-peripherals-clkc.yaml       | 8 ++++++--
>>>>    1 file changed, 6 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>>>> index 55bb73707d58..27cc1f331587 100644
>>>> --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml
>>>> @@ -24,7 +24,7 @@ properties:
>>>>        const: 1
>>>>
>>>>      clocks:
>>>> -    minItems: 14
>>>> +    minItems: 15
>>>>        items:
>>>>          - description: input oscillator
>>>>          - description: input sys clk
>>>> @@ -40,12 +40,13 @@ properties:
>>>>          - description: input gp1 pll
>>>>          - description: input mpll1
>>>>          - description: input mpll2
>>>> +      - description: input mpll3
>>> Nah, ABI break. You add it to the end of the list or provide arguments
>>> on ABI impact.
>> The third patch in this series enables the DT for the Amlogic T7 clock
>> controller.
>>
>> The clock controller node for amlogic,t7-peripherals-clkc has not been
>> merged upstream yet.
>> This change modifies the clock index order, but it will not break any
>> existing device tree since the
>> amlogic,t7-peripherals-clkc bindings are not used by any upstream or
>> downstream DT at this time.
>>
>> Therefore, it does NOT break the ABI.
> It does. Clearly visible from the diff above, because the order is the ABI.


Got it, I understand your point that changing the order break the ABI 
(since index order is part of the ABI).

>> The last clock entry is an external pad input for RTC and it is optional.
>> For logical consistency, it is better to place the required mpll3 entry
>> before the optional entry.
>>
>> If this change does not break the ABI, could I keep it in its original
>> logical order right after mpll2?
> Change breaks the ABI and commit must explain why and the impact.
>

It does break the ABI.

The mpll3 clock is one parent clock of sd_emmc and mipi_isp clock on
the Amlogic T7 SoC, but was missing from t7-peripherals-clkc.yaml.
Add the mpll3 clock source for the T7 peripherals clock controller.
so that sd_emmc and mipi_isp can use mpll3. That's why this patch is added.

While the amlogic,t7-peripherals-clkc bindings have been merged upstream,
the corresponding device tree (DT) that uses these bindings has not been 
merged yet.
As a result, there are no real-world users or systems
that would be broken by this change.

So could I update the commit message like:

The mpll3 clock is one parent clock of sd_emmc and mipi_isp clock on the 
Amlogic T7 SoC,
but was missing from t7-peripherals-clkc.yaml.
Add the mpll3 clock source for the T7 peripherals clock controller.
so that sd_emmc and mipi_isp can use it.

For logical consistency, place the required mpll3 entry before the 
optional entry.

This change will break the ABI, but while the 
amlogic,t7-peripherals-clkc bindings
have been merged upstream, the corresponding DT has not been merged yet.
Thus, no real users or systems are broken by this change.
> Best regards,
> Krzysztof

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Ferass El Hafidi]

On Thu, 05 Mar 2026 07:43, Jian Hu <jian.hu@amlogic.com> wrote:
>Add the required clock controller nodes for Amlogic T7 SoC family:
>- SCMI clock controller
>- PLL clock controller
>- Peripheral clock controller
>
>Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>---
> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
> 1 file changed, 125 insertions(+)
>
>diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>index 6510068bcff9..6ea1b583b13d 100644
>--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>@@ -6,6 +6,9 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/amlogic,t7-pwrc.h>
> #include "amlogic-t7-reset.h"
>+#include <dt-bindings/clock/amlogic,t7-scmi.h>
>+#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
>+#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
> 
> / {
> 	interrupt-parent = <&gic>;
>@@ -201,6 +204,33 @@ pwrc: power-controller {
> 		};
> 	};
> 
>+	sram@f7042000 {
>+		compatible = "mmio-sram";
>+		#address-cells = <1>;
>+		#size-cells = <1>;
>+		ranges = <0 0x0 0xf7042000 0x100>;
>+
>+		scmi_shmem: sram@0 {
>+			compatible = "arm,scmi-shmem";
>+			reg = <0x0 0x100>;
>+		};
>+	};
>+
>+	firmware {
>+		scmi: scmi {
>+			compatible = "arm,scmi-smc";
>+			arm,smc-id = <0x820000c1>;
>+			shmem = <&scmi_shmem>;
>+			#address-cells = <1>;
>+			#size-cells = <0>;
>+
>+			scmi_clk: protocol@14 {
>+				reg = <0x14>;
>+				#clock-cells = <1>;
>+			};
>+		};
>+	};
>+
> 	soc {
> 		compatible = "simple-bus";
> 		#address-cells = <2>;
>@@ -224,6 +254,42 @@ apb4: bus@fe000000 {
> 			#size-cells = <2>;
> 			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
> 
>+			clkc_periphs:clock-controller@0 {
>+				compatible = "amlogic,t7-peripherals-clkc";
>+				reg = <0x0 0x0 0x0 0x1c8>;
>+				#clock-cells = <1>;
>+				clocks = <&xtal>,
>+					 <&scmi_clk CLKID_SYS_CLK>,
>+					 <&scmi_clk CLKID_FIXED_PLL>,
>+					 <&scmi_clk CLKID_FCLK_DIV2>,
>+					 <&scmi_clk CLKID_FCLK_DIV2P5>,
>+					 <&scmi_clk CLKID_FCLK_DIV3>,
>+					 <&scmi_clk CLKID_FCLK_DIV4>,
>+					 <&scmi_clk CLKID_FCLK_DIV5>,
>+					 <&scmi_clk CLKID_FCLK_DIV7>,
>+					 <&hifi CLKID_HIFI_PLL>,
>+					 <&gp0 CLKID_GP0_PLL>,
>+					 <&gp1 CLKID_GP1_PLL>,
>+					 <&mpll CLKID_MPLL1>,
>+					 <&mpll CLKID_MPLL2>,
>+					 <&mpll CLKID_MPLL3>;
>+				clock-names = "xtal",
>+					      "sys",
>+					      "fix",
>+					      "fdiv2",
>+					      "fdiv2p5",
>+					      "fdiv3",
>+					      "fdiv4",
>+					      "fdiv5",
>+					      "fdiv7",
>+					      "hifi",
>+					      "gp0",
>+					      "gp1",
>+					      "mpll1",
>+					      "mpll2",
>+					      "mpll3";
>+			};
>+
> 			reset: reset-controller@2000 {
> 				compatible = "amlogic,t7-reset";
> 				reg = <0x0 0x2000 0x0 0x98>;
>@@ -234,6 +300,7 @@ watchdog@2100 {
> 				compatible = "amlogic,t7-wdt";
> 				reg = <0x0 0x2100 0x0 0x10>;
> 				clocks = <&xtal>;
>+
> 			};
> 
> 			periphs_pinctrl: pinctrl@4000 {
>@@ -269,6 +336,64 @@ uart_a: serial@78000 {
> 				status = "disabled";
> 			};
> 
>+			gp0:clock-controller@8080 {
>+				compatible = "amlogic,t7-gp0-pll";
>+				reg = <0x0 0x8080 0x0 0x20>;
>+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>+				clock-names = "in0";
>+				#clock-cells = <1>;
>+			};

I would separate `gp0:` and `clock-controller@8080` with a space, like so:

			gp0: clock-controller@8080 {

Same for the others below (and `clkc_periphs:clock-controller@0` above).

>+
>+			gp1:clock-controller@80c0 {
>+				compatible = "amlogic,t7-gp1-pll";
>+				reg = <0x0 0x80c0 0x0 0x14>;
>+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>+				clock-names = "in0";
>+				#clock-cells = <1>;
>+			};
>+
>+			hifi:clock-controller@8100 {
>+				compatible = "amlogic,t7-hifi-pll";
>+				reg = <0x0 0x8100 0x0 0x20>;
>+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>+				clock-names = "in0";
>+				#clock-cells = <1>;
>+			};
>+
>+			pcie:clock-controller@8140 {
>+				compatible = "amlogic,t7-pcie-pll";
>+				reg = <0x0 0x8140 0x0 0x1c>;
>+				clocks = <&scmi_clk CLKID_PCIE_OSC>;
>+				clock-names = "in0";
>+				#clock-cells = <1>;
>+			};
>+
>+			mpll:clock-controller@8180 {
>+				compatible = "amlogic,t7-mpll";
>+				reg = <0x0 0x8180 0x0 0x28>;
>+				clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
>+				clock-names = "in0";
>+				#clock-cells = <1>;
>+			};
>+
>+			hdmi:clock-controller@81c0 {
>+				compatible = "amlogic,t7-hdmi-pll";
>+				reg = <0x0 0x81c0 0x0 0x20>;
>+				clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
>+				clock-names = "in0";
>+				#clock-cells = <1>;
>+			};
>+
>+			mclk:clock-controller@8300 {
>+				compatible = "amlogic,t7-mclk-pll";
>+				reg = <0x0 0x8300 0x0 0x18>;
>+				clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
>+					 <&xtal>,
>+					 <&scmi_clk CLKID_FCLK_50M>;
>+				clock-names = "in0", "in1", "in2";
>+				#clock-cells = <1>;
>+			};
>+
> 			sec_ao: ao-secure@10220 {
> 				compatible = "amlogic,t7-ao-secure",
> 					     "amlogic,meson-gx-ao-secure",
>-- 
>2.47.1
>
>

Best regards,
Ferass

>_______________________________________________
>linux-amlogic mailing list
>linux-amlogic@lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-amlogic

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Jian Hu]

Hi, ferass


Thanks for your review.


On 3/11/2026 1:30 AM, Ferass El Hafidi wrote:
> [You don't often get email from funderscore@postmarketos.org. Learn 
> why this is important at https://aka.ms/LearnAboutSenderIdentification ]
>
> [ EXTERNAL EMAIL ]
>
> On Thu, 05 Mar 2026 07:43, Jian Hu <jian.hu@amlogic.com> wrote:
>> Add the required clock controller nodes for Amlogic T7 SoC family:
>> - SCMI clock controller
>> - PLL clock controller
>> - Peripheral clock controller
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
>> 1 file changed, 125 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi 
>> b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> index 6510068bcff9..6ea1b583b13d 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -6,6 +6,9 @@
>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>> #include <dt-bindings/power/amlogic,t7-pwrc.h>
>> #include "amlogic-t7-reset.h"
>> +#include <dt-bindings/clock/amlogic,t7-scmi.h>
>> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
>> +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
>>
>> / {
>>       interrupt-parent = <&gic>;
>> @@ -201,6 +204,33 @@ pwrc: power-controller {
>>               };
>>       };
>>
>> +      sram@f7042000 {
>> +              compatible = "mmio-sram";
>> +              #address-cells = <1>;
>> +              #size-cells = <1>;
>> +              ranges = <0 0x0 0xf7042000 0x100>;
>> +
>> +              scmi_shmem: sram@0 {
>> +                      compatible = "arm,scmi-shmem";
>> +                      reg = <0x0 0x100>;
>> +              };
>> +      };
>> +
>> +      firmware {
>> +              scmi: scmi {
>> +                      compatible = "arm,scmi-smc";
>> +                      arm,smc-id = <0x820000c1>;
>> +                      shmem = <&scmi_shmem>;
>> +                      #address-cells = <1>;
>> +                      #size-cells = <0>;
>> +
>> +                      scmi_clk: protocol@14 {
>> +                              reg = <0x14>;
>> +                              #clock-cells = <1>;
>> +                      };
>> +              };
>> +      };
>> +
>>       soc {
>>               compatible = "simple-bus";
>>               #address-cells = <2>;
>> @@ -224,6 +254,42 @@ apb4: bus@fe000000 {
>>                       #size-cells = <2>;
>>                       ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>>
>> +                      clkc_periphs:clock-controller@0 {
>> +                              compatible = 
>> "amlogic,t7-peripherals-clkc";
>> +                              reg = <0x0 0x0 0x0 0x1c8>;
>> +                              #clock-cells = <1>;
>> +                              clocks = <&xtal>,
>> +                                       <&scmi_clk CLKID_SYS_CLK>,
>> +                                       <&scmi_clk CLKID_FIXED_PLL>,
>> +                                       <&scmi_clk CLKID_FCLK_DIV2>,
>> +                                       <&scmi_clk CLKID_FCLK_DIV2P5>,
>> +                                       <&scmi_clk CLKID_FCLK_DIV3>,
>> +                                       <&scmi_clk CLKID_FCLK_DIV4>,
>> +                                       <&scmi_clk CLKID_FCLK_DIV5>,
>> +                                       <&scmi_clk CLKID_FCLK_DIV7>,
>> +                                       <&hifi CLKID_HIFI_PLL>,
>> +                                       <&gp0 CLKID_GP0_PLL>,
>> +                                       <&gp1 CLKID_GP1_PLL>,
>> +                                       <&mpll CLKID_MPLL1>,
>> +                                       <&mpll CLKID_MPLL2>,
>> +                                       <&mpll CLKID_MPLL3>;
>> +                              clock-names = "xtal",
>> +                                            "sys",
>> +                                            "fix",
>> +                                            "fdiv2",
>> +                                            "fdiv2p5",
>> +                                            "fdiv3",
>> +                                            "fdiv4",
>> +                                            "fdiv5",
>> +                                            "fdiv7",
>> +                                            "hifi",
>> +                                            "gp0",
>> +                                            "gp1",
>> +                                            "mpll1",
>> +                                            "mpll2",
>> +                                            "mpll3";
>> +                      };
>> +
>>                       reset: reset-controller@2000 {
>>                               compatible = "amlogic,t7-reset";
>>                               reg = <0x0 0x2000 0x0 0x98>;
>> @@ -234,6 +300,7 @@ watchdog@2100 {
>>                               compatible = "amlogic,t7-wdt";
>>                               reg = <0x0 0x2100 0x0 0x10>;
>>                               clocks = <&xtal>;
>> +
>>                       };
>>
>>                       periphs_pinctrl: pinctrl@4000 {
>> @@ -269,6 +336,64 @@ uart_a: serial@78000 {
>>                               status = "disabled";
>>                       };
>>
>> +                      gp0:clock-controller@8080 {
>> +                              compatible = "amlogic,t7-gp0-pll";
>> +                              reg = <0x0 0x8080 0x0 0x20>;
>> +                              clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>> +                              clock-names = "in0";
>> +                              #clock-cells = <1>;
>> +                      };
>
> I would separate `gp0:` and `clock-controller@8080` with a space, like 
> so:
>
>                        gp0: clock-controller@8080 {
>
> Same for the others below (and `clkc_periphs:clock-controller@0` above).


Thanks for the great suggestion! I completely agree that consistent 
spacing improves readability.
I'll update the format to add a space for `gp0: clock-controller@8080`, 
`clkc_periphs: clock-controller@0`
and all other related entries in v2.

>
>> +
>> +                      gp1:clock-controller@80c0 {
>> +                              compatible = "amlogic,t7-gp1-pll";
>> +                              reg = <0x0 0x80c0 0x0 0x14>;
>> +                              clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>> +                              clock-names = "in0";
>> +                              #clock-cells = <1>;
>> +                      };
>> +
>> +                      hifi:clock-controller@8100 {
>> +                              compatible = "amlogic,t7-hifi-pll";
>> +                              reg = <0x0 0x8100 0x0 0x20>;
>> +                              clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
>> +                              clock-names = "in0";
>> +                              #clock-cells = <1>;
>> +                      };
>> +
>> +                      pcie:clock-controller@8140 {
>> +                              compatible = "amlogic,t7-pcie-pll";
>> +                              reg = <0x0 0x8140 0x0 0x1c>;
>> +                              clocks = <&scmi_clk CLKID_PCIE_OSC>;
>> +                              clock-names = "in0";
>> +                              #clock-cells = <1>;
>> +                      };
>> +
>> +                      mpll:clock-controller@8180 {
>> +                              compatible = "amlogic,t7-mpll";
>> +                              reg = <0x0 0x8180 0x0 0x28>;
>> +                              clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
>> +                              clock-names = "in0";
>> +                              #clock-cells = <1>;
>> +                      };
>> +
>> +                      hdmi:clock-controller@81c0 {
>> +                              compatible = "amlogic,t7-hdmi-pll";
>> +                              reg = <0x0 0x81c0 0x0 0x20>;
>> +                              clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
>> +                              clock-names = "in0";
>> +                              #clock-cells = <1>;
>> +                      };
>> +
>> +                      mclk:clock-controller@8300 {
>> +                              compatible = "amlogic,t7-mclk-pll";
>> +                              reg = <0x0 0x8300 0x0 0x18>;
>> +                              clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
>> +                                       <&xtal>,
>> +                                       <&scmi_clk CLKID_FCLK_50M>;
>> +                              clock-names = "in0", "in1", "in2";
>> +                              #clock-cells = <1>;
>> +                      };
>> +
>>                       sec_ao: ao-secure@10220 {
>>                               compatible = "amlogic,t7-ao-secure",
>> "amlogic,meson-gx-ao-secure",
>> -- 
>> 2.47.1
>>
>>
>
> Best regards,
> Ferass
>
>> _______________________________________________
>> linux-amlogic mailing list
>> linux-amlogic@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-amlogic

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Ronald Claveau]

On 3/5/26 8:43 AM, Jian Hu wrote:
> Add the required clock controller nodes for Amlogic T7 SoC family:
> - SCMI clock controller
> - PLL clock controller
> - Peripheral clock controller
> 
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> ---
>  arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
>  1 file changed, 125 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> index 6510068bcff9..6ea1b583b13d 100644
> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
> @@ -6,6 +6,9 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/power/amlogic,t7-pwrc.h>
>  #include "amlogic-t7-reset.h"
> +#include <dt-bindings/clock/amlogic,t7-scmi.h>
> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
> +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
>  
>  / {
>  	interrupt-parent = <&gic>;
> @@ -201,6 +204,33 @@ pwrc: power-controller {
>  		};
>  	};
>  
> +	sram@f7042000 {
> +		compatible = "mmio-sram";

Applying your patches shows the following errors


[    0.019608] sram sram@f7042000: error -EINVAL: invalid resource (null)
[    0.019622] sram sram@f7042000: could not map SRAM registers
[    0.019627] sram sram@f7042000: probe with driver sram failed with
error -22

Adding a reg remove those errors on kernel logs
reg = <0x0 0xf7042000 0x0 0x100>;

Can you have a look on this ?

> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0 0x0 0xf7042000 0x100>;
> +
> +		scmi_shmem: sram@0 {
> +			compatible = "arm,scmi-shmem";
> +			reg = <0x0 0x100>;
> +		};
> +	};
> +
> +	firmware {
> +		scmi: scmi {
> +			compatible = "arm,scmi-smc";
> +			arm,smc-id = <0x820000c1>;
> +			shmem = <&scmi_shmem>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			scmi_clk: protocol@14 {
> +				reg = <0x14>;
> +				#clock-cells = <1>;
> +			};
> +		};
> +	};
> +
>  	soc {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;
> @@ -224,6 +254,42 @@ apb4: bus@fe000000 {
>  			#size-cells = <2>;
>  			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
>  
> +			clkc_periphs:clock-controller@0 {
> +				compatible = "amlogic,t7-peripherals-clkc";
> +				reg = <0x0 0x0 0x0 0x1c8>;
> +				#clock-cells = <1>;
> +				clocks = <&xtal>,
> +					 <&scmi_clk CLKID_SYS_CLK>,
> +					 <&scmi_clk CLKID_FIXED_PLL>,
> +					 <&scmi_clk CLKID_FCLK_DIV2>,
> +					 <&scmi_clk CLKID_FCLK_DIV2P5>,
> +					 <&scmi_clk CLKID_FCLK_DIV3>,
> +					 <&scmi_clk CLKID_FCLK_DIV4>,
> +					 <&scmi_clk CLKID_FCLK_DIV5>,
> +					 <&scmi_clk CLKID_FCLK_DIV7>,
> +					 <&hifi CLKID_HIFI_PLL>,
> +					 <&gp0 CLKID_GP0_PLL>,
> +					 <&gp1 CLKID_GP1_PLL>,
> +					 <&mpll CLKID_MPLL1>,
> +					 <&mpll CLKID_MPLL2>,
> +					 <&mpll CLKID_MPLL3>;
> +				clock-names = "xtal",
> +					      "sys",
> +					      "fix",
> +					      "fdiv2",
> +					      "fdiv2p5",
> +					      "fdiv3",
> +					      "fdiv4",
> +					      "fdiv5",
> +					      "fdiv7",
> +					      "hifi",
> +					      "gp0",
> +					      "gp1",
> +					      "mpll1",
> +					      "mpll2",
> +					      "mpll3";
> +			};
> +
>  			reset: reset-controller@2000 {
>  				compatible = "amlogic,t7-reset";
>  				reg = <0x0 0x2000 0x0 0x98>;
> @@ -234,6 +300,7 @@ watchdog@2100 {
>  				compatible = "amlogic,t7-wdt";
>  				reg = <0x0 0x2100 0x0 0x10>;
>  				clocks = <&xtal>;
> +
>  			};
>  
>  			periphs_pinctrl: pinctrl@4000 {
> @@ -269,6 +336,64 @@ uart_a: serial@78000 {
>  				status = "disabled";
>  			};
>  
> +			gp0:clock-controller@8080 {
> +				compatible = "amlogic,t7-gp0-pll";
> +				reg = <0x0 0x8080 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			gp1:clock-controller@80c0 {
> +				compatible = "amlogic,t7-gp1-pll";
> +				reg = <0x0 0x80c0 0x0 0x14>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			hifi:clock-controller@8100 {
> +				compatible = "amlogic,t7-hifi-pll";
> +				reg = <0x0 0x8100 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			pcie:clock-controller@8140 {
> +				compatible = "amlogic,t7-pcie-pll";
> +				reg = <0x0 0x8140 0x0 0x1c>;
> +				clocks = <&scmi_clk CLKID_PCIE_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			mpll:clock-controller@8180 {
> +				compatible = "amlogic,t7-mpll";
> +				reg = <0x0 0x8180 0x0 0x28>;
> +				clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			hdmi:clock-controller@81c0 {
> +				compatible = "amlogic,t7-hdmi-pll";
> +				reg = <0x0 0x81c0 0x0 0x20>;
> +				clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
> +				clock-names = "in0";
> +				#clock-cells = <1>;
> +			};
> +
> +			mclk:clock-controller@8300 {
> +				compatible = "amlogic,t7-mclk-pll";
> +				reg = <0x0 0x8300 0x0 0x18>;
> +				clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
> +					 <&xtal>,
> +					 <&scmi_clk CLKID_FCLK_50M>;
> +				clock-names = "in0", "in1", "in2";
> +				#clock-cells = <1>;
> +			};
> +
>  			sec_ao: ao-secure@10220 {
>  				compatible = "amlogic,t7-ao-secure",
>  					     "amlogic,meson-gx-ao-secure",


-- 
Best regards,
Ronald

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Re: [PATCH 3/3] arm64: dts: amlogic: t7: Add clock controller nodes

[Jian Hu]

On 3/11/2026 3:53 PM, Ronald Claveau wrote:
> [ EXTERNAL EMAIL ]
>
> On 3/5/26 8:43 AM, Jian Hu wrote:
>> Add the required clock controller nodes for Amlogic T7 SoC family:
>> - SCMI clock controller
>> - PLL clock controller
>> - Peripheral clock controller
>>
>> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
>> ---
>>   arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 125 ++++++++++++++++++++
>>   1 file changed, 125 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> index 6510068bcff9..6ea1b583b13d 100644
>> --- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
>> @@ -6,6 +6,9 @@
>>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>>   #include <dt-bindings/power/amlogic,t7-pwrc.h>
>>   #include "amlogic-t7-reset.h"
>> +#include <dt-bindings/clock/amlogic,t7-scmi.h>
>> +#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
>> +#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
>>
>>   / {
>>        interrupt-parent = <&gic>;
>> @@ -201,6 +204,33 @@ pwrc: power-controller {
>>                };
>>        };
>>
>> +     sram@f7042000 {
>> +             compatible = "mmio-sram";
> Applying your patches shows the following errors
>
>
> [    0.019608] sram sram@f7042000: error -EINVAL: invalid resource (null)
> [    0.019622] sram sram@f7042000: could not map SRAM registers
> [    0.019627] sram sram@f7042000: probe with driver sram failed with
> error -22
>
> Adding a reg remove those errors on kernel logs
> reg = <0x0 0xf7042000 0x0 0x100>;
>
> Can you have a look on this ?


Thanks for your feedback!

The -EINVAL error is caused by the missing 'reg' property in the sram node.
The SRAM driver requires this property to get the physical address range 
for MMIO mapping.

The 'ranges' property remains correct, and the 'reg' in the sram@0 
subnode is correct.
The SCMI clock driver works fine.

I will add the 'reg' property to the sram node to fix the kernel error 
logs in v2.

>> +             #address-cells = <1>;
>> +             #size-cells = <1>;
>> +             ranges = <0 0x0 0xf7042000 0x100>;
>> +
>> +             scmi_shmem: sram@0 {
>> +                     compatible = "arm,scmi-shmem";
>> +                     reg = <0x0 0x100>;
>> +             };
>> +     };
>> +
[...]
>>
>> --
>> Best regards,
>> Ronald
>>

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