[PATCH 0/3] Add mt8196 SMI support

[PATCH 0/3] Add mt8196 SMI support

[Xueqi Zhang]

Add mt8196 SMI support

This patchset add mt8196 SMI support. 8196 SMI has several differences
compared to previous ICs. MT8196 SMI has more than 32 SMI larbs.
It connects with SMMUv3, rather than MTK_IOMMU.MT8196 SMI commons is
backed up/restored by RTFF HW.

Xueqi Zhang (3):
  dt-bindings: memory: mediatek: Add mt8196 support
  memory: mtk-smi: Add a flag skip_rpm
  memory: mtk-smi: mt8196: Add smi support

 .../mediatek,smi-common.yaml                  |   4 +-
 .../memory-controllers/mediatek,smi-larb.yaml |   4 +-
 drivers/memory/mtk-smi.c                      | 145 +++++-
 .../dt-bindings/memory/mt8196-memory-port.h   | 460 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h  |   4 +-
 5 files changed, 609 insertions(+), 8 deletions(-)
 create mode 100644 include/dt-bindings/memory/mt8196-memory-port.h

-- 
2.46.0

[PATCH 1/3] dt-bindings: memory: mediatek: Add mt8196 support

[Xueqi Zhang]

Add mt8196 smi support in the bindings.
Since mt8196 has more than 32 SMI larbs, update 'mediatek,larb-id'
maximum to 63.

Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
---
 .../mediatek,smi-common.yaml                  |   4 +-
 .../memory-controllers/mediatek,smi-larb.yaml |   4 +-
 .../dt-bindings/memory/mt8196-memory-port.h   | 460 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h  |   4 +-
 4 files changed, 468 insertions(+), 4 deletions(-)
 create mode 100644 include/dt-bindings/memory/mt8196-memory-port.h

diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index 2f36ac23604c..70418c3a227c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -16,7 +16,7 @@ description: |
   MediaTek SMI have two generations of HW architecture, here is the list
   which generation the SoCs use:
   generation 1: mt2701 and mt7623.
-  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192 and mt8195.
+  generation 2: mt2712, mt6779, mt8167, mt8173, mt8183, mt8186, mt8188, mt8192, mt8195 and mt8196.
 
   There's slight differences between the two SMI, for generation 2, the
   register which control the iommu port is at each larb's register base. But
@@ -43,6 +43,8 @@ properties:
           - mediatek,mt8195-smi-common-vdo
           - mediatek,mt8195-smi-common-vpp
           - mediatek,mt8195-smi-sub-common
+          - mediatek,mt8196-smi-common
+          - mediatek,mt8196-smi-sub-common
           - mediatek,mt8365-smi-common
 
       - description: for mt7623
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index 2381660b324c..a6b561ba217b 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -28,6 +28,7 @@ properties:
           - mediatek,mt8188-smi-larb
           - mediatek,mt8192-smi-larb
           - mediatek,mt8195-smi-larb
+          - mediatek,mt8196-smi-larb
 
       - description: for mt7623
         items:
@@ -65,7 +66,7 @@ properties:
   mediatek,larb-id:
     $ref: /schemas/types.yaml#/definitions/uint32
     minimum: 0
-    maximum: 31
+    maximum: 63
     description: the hardware id of this larb. It's only required when this
       hardware id is not consecutive from its M4U point of view.
 
@@ -120,6 +121,7 @@ allOf:
               - mediatek,mt8188-smi-larb
               - mediatek,mt8192-smi-larb
               - mediatek,mt8195-smi-larb
+              - mediatek,mt8196-smi-larb
 
     then:
       required:
diff --git a/include/dt-bindings/memory/mt8196-memory-port.h b/include/dt-bindings/memory/mt8196-memory-port.h
new file mode 100644
index 000000000000..8fd29780311b
--- /dev/null
+++ b/include/dt-bindings/memory/mt8196-memory-port.h
@@ -0,0 +1,460 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025 MediaTek Inc.
+ * Author: Mingyuan Ma <mingyuan.ma@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MEMORY_MT8196_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8196_LARB_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+/* Larb0 -- 13 */
+#define MT8196_SMI_L0_P0_OVL_RDMA2_HDR                  MTK_M4U_ID(0, 0)
+#define MT8196_SMI_L0_P1_OVL_RDMA7_HDR		        MTK_M4U_ID(0, 1)
+#define MT8196_SMI_L0_P2_OVL_RDMA2			MTK_M4U_ID(0, 2)
+#define MT8196_SMI_L0_P3_OVL_RDMA7			MTK_M4U_ID(0, 3)
+#define MT8196_SMI_L0_P4_RESERVED			MTK_M4U_ID(0, 4)
+#define MT8196_SMI_L0_P5_RESERVED			MTK_M4U_ID(0, 5)
+#define MT8196_SMI_L0_P6_OVL_RDMA2_HDR_STASH		MTK_M4U_ID(0, 6)
+#define MT8196_SMI_L0_P7_OVL_RDMA7_HDR_STASH		MTK_M4U_ID(0, 7)
+#define MT8196_SMI_L0_P8_OVL_RDMA2_STASH		MTK_M4U_ID(0, 8)
+#define MT8196_SMI_L0_P9_OVL_RDMA7_STASH		MTK_M4U_ID(0, 9)
+#define MT8196_SMI_L0_P10_RESERVED			MTK_M4U_ID(0, 10)
+#define MT8196_SMI_L0_P11_RESERVED			MTK_M4U_ID(0, 11)
+#define MT8196_SMI_L0_P12_DISP_FAKE0			MTK_M4U_ID(0, 12)
+
+/* Larb1 -- 16 */
+#define MT8196_SMI_L1_P0_OVL_RDMA3_HDR		        MTK_M4U_ID(1, 0)
+#define MT8196_SMI_L1_P1_OVL_RDMA6_HDR		        MTK_M4U_ID(1, 1)
+#define MT8196_SMI_L1_P2_OVL_RDMA3			MTK_M4U_ID(1, 2)
+#define MT8196_SMI_L1_P3_OVL_RDMA6			MTK_M4U_ID(1, 3)
+#define MT8196_SMI_L1_P4_MDP_RDMA1			MTK_M4U_ID(1, 4)
+#define MT8196_SMI_L1_P5_RESERVED			MTK_M4U_ID(1, 5)
+#define MT8196_SMI_L1_P6_DISP_WDMA1			MTK_M4U_ID(1, 6)
+#define MT8196_SMI_L1_P7_OVL_RDMA3_HDR_STASH		MTK_M4U_ID(1, 7)
+#define MT8196_SMI_L1_P8_OVL_RDMA6_HDR_STASH		MTK_M4U_ID(1, 8)
+#define MT8196_SMI_L1_P9_OVL_RDMA3_STASH		MTK_M4U_ID(1, 9)
+#define MT8196_SMI_L1_P10_OVL_RDMA6_STASH		MTK_M4U_ID(1, 10)
+#define MT8196_SMI_L1_P11_MDP_RDMA1_STASH		MTK_M4U_ID(1, 11)
+#define MT8196_SMI_L1_P12_DISP_BWM0			MTK_M4U_ID(1, 12)
+#define MT8196_SMI_L1_P13_DISP_BWM0_STASH		MTK_M4U_ID(1, 13)
+#define MT8196_SMI_L1_P14_RESERVED			MTK_M4U_ID(1, 14)
+#define MT8196_SMI_L1_P15_DISP_FAKE1			MTK_M4U_ID(1, 15)
+
+/* Larb2 -- 18 */
+#define MT8196_SMI_L2_P0_MDP_RDMA2			MTK_M4U_ID(2, 0)
+#define MT8196_SMI_L2_P1_MDP_WROT2			MTK_M4U_ID(2, 1)
+#define MT8196_SMI_L2_P2_MDP_RDMA1			MTK_M4U_ID(2, 2)
+#define MT8196_SMI_L2_P3_MDP_WROT1			MTK_M4U_ID(2, 3)
+#define MT8196_SMI_L2_P4_MDP_RDMA0			MTK_M4U_ID(2, 4)
+#define MT8196_SMI_L2_P5_MDP_WROT0			MTK_M4U_ID(2, 5)
+#define MT8196_SMI_L2_P6_MDP_RROT0			MTK_M4U_ID(2, 6)
+#define MT8196_SMI_L2_P7_MDP_FG0			MTK_M4U_ID(2, 7)
+#define MT8196_SMI_L2_P8_RESERVED			MTK_M4U_ID(2, 8)
+#define MT8196_SMI_L2_P9_MDP_WROT2_STASH		MTK_M4U_ID(2, 9)
+#define MT8196_SMI_L2_P10_MDP_RDMA1_STASH		MTK_M4U_ID(2, 10)
+#define MT8196_SMI_L2_P11_MDP_WROT1_STASH		MTK_M4U_ID(2, 11)
+#define MT8196_SMI_L2_P12_MDP_RDMA0_STASH		MTK_M4U_ID(2, 12)
+#define MT8196_SMI_L2_P13_MDP_WROT0_STASH		MTK_M4U_ID(2, 13)
+#define MT8196_SMI_L2_P14_MDP_RROT0_STASH		MTK_M4U_ID(2, 14)
+#define MT8196_SMI_L2_P15_MDP_RDMA2_STASH		MTK_M4U_ID(2, 15)
+#define MT8196_SMI_L2_P16_RESERVED			MTK_M4U_ID(2, 16)
+#define MT8196_SMI_L2_P17_MDP_FAKE_ENG0		        MTK_M4U_ID(2, 17)
+
+/* Larb3 -- 18 */
+#define MT8196_SMI_L3_P0_MDP_RDMA2			MTK_M4U_ID(3, 0)
+#define MT8196_SMI_L3_P1_MDP_WROT2			MTK_M4U_ID(3, 1)
+#define MT8196_SMI_L3_P2_MDP_RDMA1			MTK_M4U_ID(3, 2)
+#define MT8196_SMI_L3_P3_MDP_WROT1			MTK_M4U_ID(3, 3)
+#define MT8196_SMI_L3_P4_MDP_RDMA0			MTK_M4U_ID(3, 4)
+#define MT8196_SMI_L3_P5_MDP_WROT0			MTK_M4U_ID(3, 5)
+#define MT8196_SMI_L3_P6_MDP_RROT0			MTK_M4U_ID(3, 6)
+#define MT8196_SMI_L3_P7_MDP_FG0			MTK_M4U_ID(3, 7)
+#define MT8196_SMI_L3_P8_RESERVED			MTK_M4U_ID(3, 8)
+#define MT8196_SMI_L3_P9_MDP_RDMA0_STASH		MTK_M4U_ID(3, 9)
+#define MT8196_SMI_L3_P10_MDP_WROT0_STASH		MTK_M4U_ID(3, 10)
+#define MT8196_SMI_L3_P11_MDP_RROT0_STASH		MTK_M4U_ID(3, 11)
+#define MT8196_SMI_L3_P12_MDP_RDMA2_STASH		MTK_M4U_ID(3, 12)
+#define MT8196_SMI_L3_P13_MDP_WROT2_STASH		MTK_M4U_ID(3, 13)
+#define MT8196_SMI_L3_P14_MDP_RDMA1_STASH		MTK_M4U_ID(3, 14)
+#define MT8196_SMI_L3_P15_MDP_WROT1_STASH		MTK_M4U_ID(3, 15)
+#define MT8196_SMI_L3_P16_RESERVED			MTK_M4U_ID(3, 16)
+#define MT8196_SMI_L3_P17_MDP_FAKE_ENG0		        MTK_M4U_ID(3, 17)
+
+/* Larb4 -- 8 */
+#define MT8196_SMI_L4_P0_VDEC_MC_C			MTK_M4U_ID(4, 0)
+#define MT8196_SMI_L4_P1_VDEC_UFO			MTK_M4U_ID(4, 1)
+#define MT8196_SMI_L4_P2_VDEC_PP			MTK_M4U_ID(4, 2)
+#define MT8196_SMI_L4_P3_VDEC_UFO_C			MTK_M4U_ID(4, 3)
+#define MT8196_SMI_L4_P4_VDEC_TILE			MTK_M4U_ID(4, 4)
+#define MT8196_SMI_L4_P5_VDEC_VLD			MTK_M4U_ID(4, 5)
+#define MT8196_SMI_L4_P6_VDEC_VLD2			MTK_M4U_ID(4, 6)
+#define MT8196_SMI_L4_P7_VDEC_AVC_MV			MTK_M4U_ID(4, 7)
+
+/* Larb5 -- 8 */
+#define MT8196_SMI_L5_P0_VDEC_LAT0_VLD		        MTK_M4U_ID(5, 0)
+#define MT8196_SMI_L5_P1_VDEC_LAT0_VLD2		        MTK_M4U_ID(5, 1)
+#define MT8196_SMI_L5_P2_VDEC_MC			MTK_M4U_ID(5, 2)
+#define MT8196_SMI_L5_P3_VDEC_UFO_ENC			MTK_M4U_ID(5, 3)
+#define MT8196_SMI_L5_P4_VDEC_LAT0_WDMA		        MTK_M4U_ID(5, 4)
+#define MT8196_SMI_L5_P5_VDEC_LAT0_AVC_MV		MTK_M4U_ID(5, 5)
+#define MT8196_SMI_L5_P6_VDEC_LAT0_TILE		        MTK_M4U_ID(5, 6)
+#define MT8196_SMI_L5_P7_VDEC_LAT0_UNIWRAP		MTK_M4U_ID(5, 7)
+
+/* Larb6 -- 3 */
+#define MT8196_SMI_L6_P0_VDEC_MC_PORT2		        MTK_M4U_ID(6, 0)
+#define MT8196_SMI_L6_P1_VDEC_UFO_ENC_C		        MTK_M4U_ID(6, 1)
+#define MT8196_SMI_L6_P2_VDEC_UNIWRAP			MTK_M4U_ID(6, 2)
+
+/* Larb7 -- 32 */
+#define MT8196_SMI_L7_P0_RCPU				MTK_M4U_ID(7, 0)
+#define MT8196_SMI_L7_P1_REC_FRM			MTK_M4U_ID(7, 1)
+#define MT8196_SMI_L7_P2_BS				MTK_M4U_ID(7, 2)
+#define MT8196_SMI_L7_P3_SVCOMV			        MTK_M4U_ID(7, 3)
+#define MT8196_SMI_L7_P4_RDCOMV			        MTK_M4U_ID(7, 4)
+#define MT8196_SMI_L7_P5_NBM_R			        MTK_M4U_ID(7, 5)
+#define MT8196_SMI_L7_P6_NBM_R_LITE			MTK_M4U_ID(7, 6)
+#define MT8196_SMI_L7_P7_JPGENC_YRD			MTK_M4U_ID(7, 7)
+#define MT8196_SMI_L7_P8_JPGENC_CRD			MTK_M4U_ID(7, 8)
+#define MT8196_SMI_L7_P9_JPGENC_QT			MTK_M4U_ID(7, 9)
+#define MT8196_SMI_L7_P10_FCS_SUB_W			MTK_M4U_ID(7, 10)
+#define MT8196_SMI_L7_P11_FCS_NBM_R			MTK_M4U_ID(7, 11)
+#define MT8196_SMI_L7_P12_WPP_BS			MTK_M4U_ID(7, 12)
+#define MT8196_SMI_L7_P13_WPP_RDMA			MTK_M4U_ID(7, 13)
+#define MT8196_SMI_L7_P14_DB_SYSRAM_W			MTK_M4U_ID(7, 14)
+#define MT8196_SMI_L7_P15_DB_SYSRAM_R			MTK_M4U_ID(7, 15)
+#define MT8196_SMI_L7_P16_JPGENC_BS			MTK_M4U_ID(7, 16)
+#define MT8196_SMI_L7_P17_JPGDEC_W			MTK_M4U_ID(7, 17)
+#define MT8196_SMI_L7_P18_JPGDEC_BS			MTK_M4U_ID(7, 18)
+#define MT8196_SMI_L7_P19_NBM_W			        MTK_M4U_ID(7, 19)
+#define MT8196_SMI_L7_P20_NBM_W_LITE			MTK_M4U_ID(7, 20)
+#define MT8196_SMI_L7_P21_CUR_LUMA			MTK_M4U_ID(7, 21)
+#define MT8196_SMI_L7_P22_CUR_CHROMA			MTK_M4U_ID(7, 22)
+#define MT8196_SMI_L7_P23_REF_LUMA			MTK_M4U_ID(7, 23)
+#define MT8196_SMI_L7_P24_REF_CHROMA			MTK_M4U_ID(7, 24)
+#define MT8196_SMI_L7_P25_FCS_SUB_R			MTK_M4U_ID(7, 25)
+#define MT8196_SMI_L7_P26_FCS_NBM_W			MTK_M4U_ID(7, 26)
+#define MT8196_SMI_L7_P27_JPGDEC_W_1			MTK_M4U_ID(7, 27)
+#define MT8196_SMI_L7_P28_JPGDEC_BS_1			MTK_M4U_ID(7, 28)
+#define MT8196_SMI_L7_P29_JPGDEC_HUF_1		        MTK_M4U_ID(7, 29)
+#define MT8196_SMI_L7_P30_JPGDEC_HUF			MTK_M4U_ID(7, 30)
+#define MT8196_SMI_L7_P31_EC_SYSRAM			MTK_M4U_ID(7, 31)
+
+/* Larb8 -- 32 */
+#define MT8196_SMI_L8_P0_RCPU				MTK_M4U_ID(8, 0)
+#define MT8196_SMI_L8_P1_REC_FRM			MTK_M4U_ID(8, 1)
+#define MT8196_SMI_L8_P2_BS				MTK_M4U_ID(8, 2)
+#define MT8196_SMI_L8_P3_SVCOMV			        MTK_M4U_ID(8, 3)
+#define MT8196_SMI_L8_P4_RDCOMV			        MTK_M4U_ID(8, 4)
+#define MT8196_SMI_L8_P5_NBM_R			        MTK_M4U_ID(8, 5)
+#define MT8196_SMI_L8_P6_NBM_R_LITE			MTK_M4U_ID(8, 6)
+#define MT8196_SMI_L8_P7_JPGENC_YRD			MTK_M4U_ID(8, 7)
+#define MT8196_SMI_L8_P8_JPGENC_CRD			MTK_M4U_ID(8, 8)
+#define MT8196_SMI_L8_P9_JPGENC_QT			MTK_M4U_ID(8, 9)
+#define MT8196_SMI_L8_P10_FCS_SUB_W			MTK_M4U_ID(8, 10)
+#define MT8196_SMI_L8_P11_FCS_NBM_R			MTK_M4U_ID(8, 11)
+#define MT8196_SMI_L8_P12_WPP_BS			MTK_M4U_ID(8, 12)
+#define MT8196_SMI_L8_P13_WPP_RDMA			MTK_M4U_ID(8, 13)
+#define MT8196_SMI_L8_P14_DB_SYSRAM_W			MTK_M4U_ID(8, 14)
+#define MT8196_SMI_L8_P15_DB_SYSRAM_R			MTK_M4U_ID(8, 15)
+#define MT8196_SMI_L8_P16_JPGENC_BS			MTK_M4U_ID(8, 16)
+#define MT8196_SMI_L8_P17_JPGDEC_W			MTK_M4U_ID(8, 17)
+#define MT8196_SMI_L8_P18_JPGDEC_BS			MTK_M4U_ID(8, 18)
+#define MT8196_SMI_L8_P19_NBM_W			        MTK_M4U_ID(8, 19)
+#define MT8196_SMI_L8_P20_NBM_W_LITE			MTK_M4U_ID(8, 20)
+#define MT8196_SMI_L8_P21_CUR_LUMA			MTK_M4U_ID(8, 21)
+#define MT8196_SMI_L8_P22_CUR_CHROMA			MTK_M4U_ID(8, 22)
+#define MT8196_SMI_L8_P23_REF_LUMA			MTK_M4U_ID(8, 23)
+#define MT8196_SMI_L8_P24_REF_CHROMA			MTK_M4U_ID(8, 24)
+#define MT8196_SMI_L8_P25_FCS_SUB_R			MTK_M4U_ID(8, 25)
+#define MT8196_SMI_L8_P26_FCS_NBM_W			MTK_M4U_ID(8, 26)
+#define MT8196_SMI_L8_P27_JPGDEC_W_1			MTK_M4U_ID(8, 27)
+#define MT8196_SMI_L8_P28_JPGDEC_BS_1			MTK_M4U_ID(8, 28)
+#define MT8196_SMI_L8_P29_JPGDEC_HUF_1		        MTK_M4U_ID(8, 29)
+#define MT8196_SMI_L8_P30_JPGDEC_HUF			MTK_M4U_ID(8, 30)
+#define MT8196_SMI_L8_P31_EC_SYSRAM			MTK_M4U_ID(8, 31)
+
+/* Larb20 -- 15 */
+#define MT8196_SMI_L20_P0_OVL_RDMA4_HDR		        MTK_M4U_ID(20, 0)
+#define MT8196_SMI_L20_P1_OVL_RDMA9_HDR		        MTK_M4U_ID(20, 1)
+#define MT8196_SMI_L20_P2_OVL_RDMA0_HDR		        MTK_M4U_ID(20, 2)
+#define MT8196_SMI_L20_P3_OVL_RDMA4			MTK_M4U_ID(20, 3)
+#define MT8196_SMI_L20_P4_OVL_RDMA9			MTK_M4U_ID(20, 4)
+#define MT8196_SMI_L20_P5_OVL_RDMA0			MTK_M4U_ID(20, 5)
+#define MT8196_SMI_L20_P6_RESERVED			MTK_M4U_ID(20, 6)
+#define MT8196_SMI_L20_P7_OVL_RDMA4_HDR_STASH		MTK_M4U_ID(20, 7)
+#define MT8196_SMI_L20_P8_OVL_RDMA9_HDR_STASH		MTK_M4U_ID(20, 8)
+#define MT8196_SMI_L20_P9_OVL_RDMA0_HDR_STASH		MTK_M4U_ID(20, 9)
+#define MT8196_SMI_L20_P10_OVL_RDMA4_STASH		MTK_M4U_ID(20, 10)
+#define MT8196_SMI_L20_P11_OVL_RDMA9_STASH		MTK_M4U_ID(20, 11)
+#define MT8196_SMI_L20_P12_OVL_RDMA0_STASH		MTK_M4U_ID(20, 12)
+#define MT8196_SMI_L20_P13_RESERVED			MTK_M4U_ID(20, 13)
+#define MT8196_SMI_L20_P14_RESERVED			MTK_M4U_ID(20, 14)
+
+/* Larb21 -- 18 */
+#define MT8196_SMI_L21_P0_OVL_RDMA5_HDR		        MTK_M4U_ID(21, 0)
+#define MT8196_SMI_L21_P1_OVL_RDMA8_HDR		        MTK_M4U_ID(21, 1)
+#define MT8196_SMI_L21_P2_OVL_RDMA1_HDR		        MTK_M4U_ID(21, 2)
+#define MT8196_SMI_L21_P3_OVL_RDMA5			MTK_M4U_ID(21, 3)
+#define MT8196_SMI_L21_P4_OVL_RDMA8			MTK_M4U_ID(21, 4)
+#define MT8196_SMI_L21_P5_OVL_RDMA1			MTK_M4U_ID(21, 5)
+#define MT8196_SMI_L21_P6_RESERVED			MTK_M4U_ID(21, 6)
+#define MT8196_SMI_L21_P7_MDP_RDMA0			MTK_M4U_ID(21, 7)
+#define MT8196_SMI_L21_P8_DISP_WDMA0			MTK_M4U_ID(21, 8)
+#define MT8196_SMI_L21_P9_DISP_UFBC_WDMA0		MTK_M4U_ID(21, 9)
+#define MT8196_SMI_L21_P10_OVL_RDMA5_HDR_STASH	        MTK_M4U_ID(21, 10)
+#define MT8196_SMI_L21_P11_OVL_RDMA8_HDR_STASH	        MTK_M4U_ID(21, 11)
+#define MT8196_SMI_L21_P12_OVL_RDMA1_HDR_STASH	        MTK_M4U_ID(21, 12)
+#define MT8196_SMI_L21_P13_OVL_RDMA5_STASH		MTK_M4U_ID(21, 13)
+#define MT8196_SMI_L21_P14_OVL_RDMA8_STASH		MTK_M4U_ID(21, 14)
+#define MT8196_SMI_L21_P15_OVL_RDMA1_STASH		MTK_M4U_ID(21, 15)
+#define MT8196_SMI_L21_P16_MDP_RDMA0_STASH		MTK_M4U_ID(21, 16)
+#define MT8196_SMI_L21_P17_RESERVED			MTK_M4U_ID(21, 17)
+
+/* Larb24 -- 32 */
+#define MT8196_SMI_L24_P0_RCPU			        MTK_M4U_ID(24, 0)
+#define MT8196_SMI_L24_P1_REC_FRM			MTK_M4U_ID(24, 1)
+#define MT8196_SMI_L24_P2_BS				MTK_M4U_ID(24, 2)
+#define MT8196_SMI_L24_P3_SVCOMV			MTK_M4U_ID(24, 3)
+#define MT8196_SMI_L24_P4_RDCOMV			MTK_M4U_ID(24, 4)
+#define MT8196_SMI_L24_P5_NBM_R			        MTK_M4U_ID(24, 5)
+#define MT8196_SMI_L24_P6_NBM_R_LITE			MTK_M4U_ID(24, 6)
+#define MT8196_SMI_L24_P7_JPGENC_YRD			MTK_M4U_ID(24, 7)
+#define MT8196_SMI_L24_P8_JPGENC_CRD			MTK_M4U_ID(24, 8)
+#define MT8196_SMI_L24_P9_JPGENC_QT			MTK_M4U_ID(24, 9)
+#define MT8196_SMI_L24_P10_FCS_SUB_W			MTK_M4U_ID(24, 10)
+#define MT8196_SMI_L24_P11_FCS_NBM_R			MTK_M4U_ID(24, 11)
+#define MT8196_SMI_L24_P12_WPP_BS			MTK_M4U_ID(24, 12)
+#define MT8196_SMI_L24_P13_WPP_RDMA			MTK_M4U_ID(24, 13)
+#define MT8196_SMI_L24_P14_DB_SYSRAM_W		        MTK_M4U_ID(24, 14)
+#define MT8196_SMI_L24_P15_DB_SYSRAM_R		        MTK_M4U_ID(24, 15)
+#define MT8196_SMI_L24_P16_JPGENC_BS			MTK_M4U_ID(24, 16)
+#define MT8196_SMI_L24_P17_JPGDEC_W			MTK_M4U_ID(24, 17)
+#define MT8196_SMI_L24_P18_JPGDEC_BS			MTK_M4U_ID(24, 18)
+#define MT8196_SMI_L24_P19_NBM_W			MTK_M4U_ID(24, 19)
+#define MT8196_SMI_L24_P20_NBM_W_LITE			MTK_M4U_ID(24, 20)
+#define MT8196_SMI_L24_P21_CUR_LUMA			MTK_M4U_ID(24, 21)
+#define MT8196_SMI_L24_P22_CUR_CHROMA			MTK_M4U_ID(24, 22)
+#define MT8196_SMI_L24_P23_REF_LUMA			MTK_M4U_ID(24, 23)
+#define MT8196_SMI_L24_P24_REF_CHROMA			MTK_M4U_ID(24, 24)
+#define MT8196_SMI_L24_P25_FCS_SUB_R			MTK_M4U_ID(24, 25)
+#define MT8196_SMI_L24_P26_FCS_NBM_W			MTK_M4U_ID(24, 26)
+#define MT8196_SMI_L24_P27_JPGDEC_W_1			MTK_M4U_ID(24, 27)
+#define MT8196_SMI_L24_P28_JPGDEC_BS_1		        MTK_M4U_ID(24, 28)
+#define MT8196_SMI_L24_P29_JPGDEC_HUF_1		        MTK_M4U_ID(24, 29)
+#define MT8196_SMI_L24_P30_JPGDEC_HUF			MTK_M4U_ID(24, 30)
+#define MT8196_SMI_L24_P31_EC_SYSRAM			MTK_M4U_ID(24, 31)
+
+/* Larb32 -- 10 */
+#define MT8196_SMI_L32_P0_DISP_RESERVED_0		MTK_M4U_ID(32, 0)
+#define MT8196_SMI_L32_P1_DISP_RESERVED_1		MTK_M4U_ID(32, 1)
+#define MT8196_SMI_L32_P2_DISP_RESERVED_2		MTK_M4U_ID(32, 2)
+#define MT8196_SMI_L32_P3_DISP_RESERVED_3		MTK_M4U_ID(32, 3)
+#define MT8196_SMI_L32_P4_DISP_POSTMASK0		MTK_M4U_ID(32, 4)
+#define MT8196_SMI_L32_P5_DISP_POSTMASK1		MTK_M4U_ID(32, 5)
+#define MT8196_SMI_L32_P6_DISP_MDP_RDMA0		MTK_M4U_ID(32, 6)
+#define MT8196_SMI_L32_P7_DISP_WDMA0			MTK_M4U_ID(32, 7)
+#define MT8196_SMI_L32_P8_DISP_FAKE_ENG0		MTK_M4U_ID(32, 8)
+#define MT8196_SMI_L32_P9_DISP_MDP_RDMA0_STASH	        MTK_M4U_ID(32, 9)
+
+/* Larb33 -- 16 */
+#define MT8196_SMI_L33_P0_DISP1_ODDMR0_DMRR0		MTK_M4U_ID(33, 0)
+#define MT8196_SMI_L33_P1_RESERVED			MTK_M4U_ID(33, 1)
+#define MT8196_SMI_L33_P2_RESERVED			MTK_M4U_ID(33, 2)
+#define MT8196_SMI_L33_P3_RESERVED			MTK_M4U_ID(33, 3)
+#define MT8196_SMI_L33_P4_DISP1_ODDMR0_DBIR		MTK_M4U_ID(33, 4)
+#define MT8196_SMI_L33_P5_DISP1_ODDMR0_ODR		MTK_M4U_ID(33, 5)
+#define MT8196_SMI_L33_P6_DISP1_ODDMR0_ODW		MTK_M4U_ID(33, 6)
+#define MT8196_SMI_L33_P7_RESERVED			MTK_M4U_ID(33, 7)
+#define MT8196_SMI_L33_P8_DISP1_GDMA0			MTK_M4U_ID(33, 8)
+#define MT8196_SMI_L33_P9_DISP1_MDP_RDMA1		MTK_M4U_ID(33, 9)
+#define MT8196_SMI_L33_P10_DISP1_WDMA1		        MTK_M4U_ID(33, 10)
+#define MT8196_SMI_L33_P11_DISP1_WDMA2		        MTK_M4U_ID(33, 11)
+#define MT8196_SMI_L33_P12_DISP1_WDMA3		        MTK_M4U_ID(33, 12)
+#define MT8196_SMI_L33_P13_DISP1_WDMA4		        MTK_M4U_ID(33, 13)
+#define MT8196_SMI_L33_P14_DISP1_MDP_RDMA1_STASH	MTK_M4U_ID(33, 14)
+#define MT8196_SMI_L33_P15_RESERVED			MTK_M4U_ID(33, 15)
+
+/* Larb34 -- 13 */
+#define MT8196_SMI_L34_P0_OVL_RDMA2_HDR		        MTK_M4U_ID(34, 0)
+#define MT8196_SMI_L34_P1_OVL_RDMA7_HDR		        MTK_M4U_ID(34, 1)
+#define MT8196_SMI_L34_P2_OVL_RDMA2			MTK_M4U_ID(34, 2)
+#define MT8196_SMI_L34_P3_OVL_RDMA7			MTK_M4U_ID(34, 3)
+#define MT8196_SMI_L34_P4_RESERVED			MTK_M4U_ID(34, 4)
+#define MT8196_SMI_L34_P5_RESERVED			MTK_M4U_ID(34, 5)
+#define MT8196_SMI_L34_P6_OVL_RDMA2_HDR_STASH		MTK_M4U_ID(34, 6)
+#define MT8196_SMI_L34_P7_OVL_RDMA7_HDR_STASH		MTK_M4U_ID(34, 7)
+#define MT8196_SMI_L34_P8_OVL_RDMA2_STASH		MTK_M4U_ID(34, 8)
+#define MT8196_SMI_L34_P9_OVL_RDMA7_STASH		MTK_M4U_ID(34, 9)
+#define MT8196_SMI_L34_P10_RESERVED			MTK_M4U_ID(34, 10)
+#define MT8196_SMI_L34_P11_RESERVED			MTK_M4U_ID(34, 11)
+#define MT8196_SMI_L34_P12_DISP_FAKE0			MTK_M4U_ID(34, 12)
+
+/* Larb35 -- 16 */
+#define MT8196_SMI_L35_P0_OVL_RDMA3_HDR		        MTK_M4U_ID(35, 0)
+#define MT8196_SMI_L35_P1_OVL_RDMA6_HDR		        MTK_M4U_ID(35, 1)
+#define MT8196_SMI_L35_P2_OVL_RDMA3			MTK_M4U_ID(35, 2)
+#define MT8196_SMI_L35_P3_OVL_RDMA6			MTK_M4U_ID(35, 3)
+#define MT8196_SMI_L35_P4_MDP_RDMA1			MTK_M4U_ID(35, 4)
+#define MT8196_SMI_L35_P5_RESERVED			MTK_M4U_ID(35, 5)
+#define MT8196_SMI_L35_P6_DISP_WDMA1			MTK_M4U_ID(35, 6)
+#define MT8196_SMI_L35_P7_OVL_RDMA3_HDR_STASH		MTK_M4U_ID(35, 7)
+#define MT8196_SMI_L35_P8_OVL_RDMA6_HDR_STASH		MTK_M4U_ID(35, 8)
+#define MT8196_SMI_L35_P9_OVL_RDMA3_STASH		MTK_M4U_ID(35, 9)
+#define MT8196_SMI_L35_P10_OVL_RDMA6_STASH		MTK_M4U_ID(35, 10)
+#define MT8196_SMI_L35_P11_MDP_RDMA1_STASH		MTK_M4U_ID(35, 11)
+#define MT8196_SMI_L35_P12_DISP_BWM0			MTK_M4U_ID(35, 12)
+#define MT8196_SMI_L35_P13_DISP_BWM0_STASH		MTK_M4U_ID(35, 13)
+#define MT8196_SMI_L35_P14_RESERVED			MTK_M4U_ID(35, 14)
+#define MT8196_SMI_L35_P15_DISP_FAKE1			MTK_M4U_ID(35, 15)
+
+/* Larb36 -- 15 */
+#define MT8196_SMI_L36_P0_OVL_RDMA4_HDR		        MTK_M4U_ID(36, 0)
+#define MT8196_SMI_L36_P1_OVL_RDMA9_HDR		        MTK_M4U_ID(36, 1)
+#define MT8196_SMI_L36_P2_OVL_RDMA0_HDR		        MTK_M4U_ID(36, 2)
+#define MT8196_SMI_L36_P3_OVL_RDMA4			MTK_M4U_ID(36, 3)
+#define MT8196_SMI_L36_P4_OVL_RDMA9			MTK_M4U_ID(36, 4)
+#define MT8196_SMI_L36_P5_OVL_RDMA0			MTK_M4U_ID(36, 5)
+#define MT8196_SMI_L36_P6_RESERVED			MTK_M4U_ID(36, 6)
+#define MT8196_SMI_L36_P7_OVL_RDMA4_HDR_STASH		MTK_M4U_ID(36, 7)
+#define MT8196_SMI_L36_P8_OVL_RDMA9_HDR_STASH		MTK_M4U_ID(36, 8)
+#define MT8196_SMI_L36_P9_OVL_RDMA0_HDR_STASH		MTK_M4U_ID(36, 9)
+#define MT8196_SMI_L36_P10_OVL_RDMA4_STASH		MTK_M4U_ID(36, 10)
+#define MT8196_SMI_L36_P11_OVL_RDMA9_STASH		MTK_M4U_ID(36, 11)
+#define MT8196_SMI_L36_P12_OVL_RDMA0_STASH		MTK_M4U_ID(36, 12)
+#define MT8196_SMI_L36_P13_RESERVED			MTK_M4U_ID(36, 13)
+#define MT8196_SMI_L36_P14_RESERVED			MTK_M4U_ID(36, 14)
+
+/* Larb37 -- 18 */
+#define MT8196_SMI_L37_P0_OVL_RDMA5_HDR		        MTK_M4U_ID(37, 0)
+#define MT8196_SMI_L37_P1_OVL_RDMA8_HDR		        MTK_M4U_ID(37, 1)
+#define MT8196_SMI_L37_P2_OVL_RDMA1_HDR		        MTK_M4U_ID(37, 2)
+#define MT8196_SMI_L37_P3_OVL_RDMA5			MTK_M4U_ID(37, 3)
+#define MT8196_SMI_L37_P4_OVL_RDMA8			MTK_M4U_ID(37, 4)
+#define MT8196_SMI_L37_P5_OVL_RDMA1			MTK_M4U_ID(37, 5)
+#define MT8196_SMI_L37_P6_RESERVED			MTK_M4U_ID(37, 6)
+#define MT8196_SMI_L37_P7_MDP_RDMA0			MTK_M4U_ID(37, 7)
+#define MT8196_SMI_L37_P8_DISP_WDMA0			MTK_M4U_ID(37, 8)
+#define MT8196_SMI_L37_P9_DISP_UFBC_WDMA0		MTK_M4U_ID(37, 9)
+#define MT8196_SMI_L37_P10_OVL_RDMA5_HDR_STASH	        MTK_M4U_ID(37, 10)
+#define MT8196_SMI_L37_P11_OVL_RDMA8_HDR_STASH	        MTK_M4U_ID(37, 11)
+#define MT8196_SMI_L37_P12_OVL_RDMA1_HDR_STASH	        MTK_M4U_ID(37, 12)
+#define MT8196_SMI_L37_P13_OVL_RDMA5_STASH		MTK_M4U_ID(37, 13)
+#define MT8196_SMI_L37_P14_OVL_RDMA8_STASH		MTK_M4U_ID(37, 14)
+#define MT8196_SMI_L37_P15_OVL_RDMA1_STASH		MTK_M4U_ID(37, 15)
+#define MT8196_SMI_L37_P16_MDP_RDMA0_STASH		MTK_M4U_ID(37, 16)
+#define MT8196_SMI_L37_P17_RESERVED			MTK_M4U_ID(37, 17)
+
+/* Larb41 -- 32 */
+#define MT8196_SMI_L41_P0_ADAB_FORMATTER_R		MTK_M4U_ID(41, 0)
+#define MT8196_SMI_L41_P1_REC_FRM			MTK_M4U_ID(41, 1)
+#define MT8196_SMI_L41_P2_ADAB_FORMATTER_W		MTK_M4U_ID(41, 2)
+#define MT8196_SMI_L41_P3_ADAB_CUR_LUMA_R		MTK_M4U_ID(41, 3)
+#define MT8196_SMI_L41_P4_ADAB_REF_LUMA_R		MTK_M4U_ID(41, 4)
+#define MT8196_SMI_L41_P5_NBM_R			        MTK_M4U_ID(41, 5)
+#define MT8196_SMI_L41_P6_NBM_R_LITE			MTK_M4U_ID(41, 6)
+#define MT8196_SMI_L41_P7_JPGENC_YRD			MTK_M4U_ID(41, 7)
+#define MT8196_SMI_L41_P8_JPGENC_CRD			MTK_M4U_ID(41, 8)
+#define MT8196_SMI_L41_P9_JPGENC_QT			MTK_M4U_ID(41, 9)
+#define MT8196_SMI_L41_P10_FCS_SUB_W			MTK_M4U_ID(41, 10)
+#define MT8196_SMI_L41_P11_FCS_NBM_R			MTK_M4U_ID(41, 11)
+#define MT8196_SMI_L41_P12_WPP_BS			MTK_M4U_ID(41, 12)
+#define MT8196_SMI_L41_P13_WPP_RDMA			MTK_M4U_ID(41, 13)
+#define MT8196_SMI_L41_P14_DB_SYSRAM_W		        MTK_M4U_ID(41, 14)
+#define MT8196_SMI_L41_P15_DB_SYSRAM_R		        MTK_M4U_ID(41, 15)
+#define MT8196_SMI_L41_P16_JPGENC_BS			MTK_M4U_ID(41, 16)
+#define MT8196_SMI_L41_P17_JPGDEC_W			MTK_M4U_ID(41, 17)
+#define MT8196_SMI_L41_P18_JPGDEC_BS			MTK_M4U_ID(41, 18)
+#define MT8196_SMI_L41_P19_NBM_W			MTK_M4U_ID(41, 19)
+#define MT8196_SMI_L41_P20_NBM_W_LITE			MTK_M4U_ID(41, 20)
+#define MT8196_SMI_L41_P21_CUR_LUMA			MTK_M4U_ID(41, 21)
+#define MT8196_SMI_L41_P22_CUR_CHROMA			MTK_M4U_ID(41, 22)
+#define MT8196_SMI_L41_P23_REF_LUMA			MTK_M4U_ID(41, 23)
+#define MT8196_SMI_L41_P24_REF_CHROMA			MTK_M4U_ID(41, 24)
+#define MT8196_SMI_L41_P25_FCS_SUB_R			MTK_M4U_ID(41, 25)
+#define MT8196_SMI_L41_P26_FCS_NBM_W			MTK_M4U_ID(41, 26)
+#define MT8196_SMI_L41_P27_JPGDEC_W_1			MTK_M4U_ID(41, 27)
+#define MT8196_SMI_L41_P28_JPGDEC_BS_1		        MTK_M4U_ID(41, 28)
+#define MT8196_SMI_L41_P29_JPGDEC_HUF_1		        MTK_M4U_ID(41, 29)
+#define MT8196_SMI_L41_P30_JPGDEC_HUF			MTK_M4U_ID(41, 30)
+#define MT8196_SMI_L41_P31_EC_SYSRAM			MTK_M4U_ID(41, 31)
+
+/* Larb42 -- 32 */
+#define MT8196_SMI_L42_P0_RCPU			        MTK_M4U_ID(42, 0)
+#define MT8196_SMI_L42_P1_REC_FRM			MTK_M4U_ID(42, 1)
+#define MT8196_SMI_L42_P2_BS				MTK_M4U_ID(42, 2)
+#define MT8196_SMI_L42_P3_SVCOMV			MTK_M4U_ID(42, 3)
+#define MT8196_SMI_L42_P4_RDCOMV			MTK_M4U_ID(42, 4)
+#define MT8196_SMI_L42_P5_NBM_R			        MTK_M4U_ID(42, 5)
+#define MT8196_SMI_L42_P6_NBM_R_LITE			MTK_M4U_ID(42, 6)
+#define MT8196_SMI_L42_P7_JPGENC_YRD			MTK_M4U_ID(42, 7)
+#define MT8196_SMI_L42_P8_JPGENC_CRD			MTK_M4U_ID(42, 8)
+#define MT8196_SMI_L42_P9_JPGENC_QT			MTK_M4U_ID(42, 9)
+#define MT8196_SMI_L42_P10_FCS_SUB_W			MTK_M4U_ID(42, 10)
+#define MT8196_SMI_L42_P11_FCS_NBM_R			MTK_M4U_ID(42, 11)
+#define MT8196_SMI_L42_P12_WPP_BS			MTK_M4U_ID(42, 12)
+#define MT8196_SMI_L42_P13_WPP_RDMA			MTK_M4U_ID(42, 13)
+#define MT8196_SMI_L42_P14_DB_SYSRAM_W		        MTK_M4U_ID(42, 14)
+#define MT8196_SMI_L42_P15_DB_SYSRAM_R		        MTK_M4U_ID(42, 15)
+#define MT8196_SMI_L42_P16_JPGENC_BS			MTK_M4U_ID(42, 16)
+#define MT8196_SMI_L42_P17_JPGDEC_W			MTK_M4U_ID(42, 17)
+#define MT8196_SMI_L42_P18_JPGDEC_BS			MTK_M4U_ID(42, 18)
+#define MT8196_SMI_L42_P19_NBM_W			MTK_M4U_ID(42, 19)
+#define MT8196_SMI_L42_P20_NBM_W_LITE			MTK_M4U_ID(42, 20)
+#define MT8196_SMI_L42_P21_CUR_LUMA			MTK_M4U_ID(42, 21)
+#define MT8196_SMI_L42_P22_CUR_CHROMA			MTK_M4U_ID(42, 22)
+#define MT8196_SMI_L42_P23_REF_LUMA			MTK_M4U_ID(42, 23)
+#define MT8196_SMI_L42_P24_REF_CHROMA			MTK_M4U_ID(42, 24)
+#define MT8196_SMI_L42_P25_FCS_SUB_R			MTK_M4U_ID(42, 25)
+#define MT8196_SMI_L42_P26_FCS_NBM_W			MTK_M4U_ID(42, 26)
+#define MT8196_SMI_L42_P27_JPGDEC_W_1			MTK_M4U_ID(42, 27)
+#define MT8196_SMI_L42_P28_JPGDEC_BS_1		        MTK_M4U_ID(42, 28)
+#define MT8196_SMI_L42_P29_JPGDEC_HUF_1		        MTK_M4U_ID(42, 29)
+#define MT8196_SMI_L42_P30_JPGDEC_HUF			MTK_M4U_ID(42, 30)
+#define MT8196_SMI_L42_P31_EC_SYSRAM			MTK_M4U_ID(42, 31)
+
+/* Larb47 -- 32 */
+#define MT8196_SMI_L47_P0_RCPU			        MTK_M4U_ID(47, 0)
+#define MT8196_SMI_L47_P1_REC_FRM			MTK_M4U_ID(47, 1)
+#define MT8196_SMI_L47_P2_BS				MTK_M4U_ID(47, 2)
+#define MT8196_SMI_L47_P3_SVCOMV			MTK_M4U_ID(47, 3)
+#define MT8196_SMI_L47_P4_RDCOMV			MTK_M4U_ID(47, 4)
+#define MT8196_SMI_L47_P5_NBM_R			        MTK_M4U_ID(47, 5)
+#define MT8196_SMI_L47_P6_NBM_R_LITE			MTK_M4U_ID(47, 6)
+#define MT8196_SMI_L47_P7_JPGENC_YRD			MTK_M4U_ID(47, 7)
+#define MT8196_SMI_L47_P8_JPGENC_CRD			MTK_M4U_ID(47, 8)
+#define MT8196_SMI_L47_P9_JPGENC_QT			MTK_M4U_ID(47, 9)
+#define MT8196_SMI_L47_P10_FCS_SUB_W			MTK_M4U_ID(47, 10)
+#define MT8196_SMI_L47_P11_FCS_NBM_R			MTK_M4U_ID(47, 11)
+#define MT8196_SMI_L47_P12_WPP_BS			MTK_M4U_ID(47, 12)
+#define MT8196_SMI_L47_P13_WPP_RDMA			MTK_M4U_ID(47, 13)
+#define MT8196_SMI_L47_P14_DB_SYSRAM_W		        MTK_M4U_ID(47, 14)
+#define MT8196_SMI_L47_P15_DB_SYSRAM_R		        MTK_M4U_ID(47, 15)
+#define MT8196_SMI_L47_P16_JPGENC_BS			MTK_M4U_ID(47, 16)
+#define MT8196_SMI_L47_P17_JPGDEC_W			MTK_M4U_ID(47, 17)
+#define MT8196_SMI_L47_P18_JPGDEC_BS			MTK_M4U_ID(47, 18)
+#define MT8196_SMI_L47_P19_NBM_W			MTK_M4U_ID(47, 19)
+#define MT8196_SMI_L47_P20_NBM_W_LITE			MTK_M4U_ID(47, 20)
+#define MT8196_SMI_L47_P21_CUR_LUMA			MTK_M4U_ID(47, 21)
+#define MT8196_SMI_L47_P22_CUR_CHROMA			MTK_M4U_ID(47, 22)
+#define MT8196_SMI_L47_P23_REF_LUMA			MTK_M4U_ID(47, 23)
+#define MT8196_SMI_L47_P24_REF_CHROMA			MTK_M4U_ID(47, 24)
+#define MT8196_SMI_L47_P25_FCS_SUB_R			MTK_M4U_ID(47, 25)
+#define MT8196_SMI_L47_P26_FCS_NBM_W			MTK_M4U_ID(47, 26)
+#define MT8196_SMI_L47_P27_JPGDEC_W_1			MTK_M4U_ID(47, 27)
+#define MT8196_SMI_L47_P28_JPGDEC_BS_1		        MTK_M4U_ID(47, 28)
+#define MT8196_SMI_L47_P29_JPGDEC_HUF_1		        MTK_M4U_ID(47, 29)
+#define MT8196_SMI_L47_P30_JPGDEC_HUF			MTK_M4U_ID(47, 30)
+#define MT8196_SMI_L47_P31_EC_SYSRAM			MTK_M4U_ID(47, 31)
+
+/* Fake larb48 */
+#define MT8196_SMI_L48_CCU0				MTK_M4U_ID(48, 0)
+#define MT8196_SMI_L48_CCU1				MTK_M4U_ID(48, 1)
+
+/* Fake larb49 */
+#define MT8196_SMI_L49_MMUP				MTK_M4U_ID(49, 0)
+#define MT8196_SMI_L49_GCE_D				MTK_M4U_ID(49, 1)
+#define MT8196_SMI_L49_GCE_M				MTK_M4U_ID(49, 2)
+
+#endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
index 2f68a0511a25..fc47fcfc090e 100644
--- a/include/dt-bindings/memory/mtk-memory-port.h
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -6,10 +6,10 @@
 #ifndef __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_
 #define __DT_BINDINGS_MEMORY_MTK_MEMORY_PORT_H_
 
-#define MTK_LARB_NR_MAX			32
+#define MTK_LARB_NR_MAX			64
 
 #define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))
-#define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
+#define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x3f)
 #define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
 
 #define MTK_IFAIOMMU_PERI_ID(port)	MTK_M4U_ID(0, port)
-- 
2.46.0

Re: [PATCH 1/3] dt-bindings: memory: mediatek: Add mt8196 support

[Rob Herring (Arm)]

On Thu, 20 Mar 2025 15:36:16 +0800, Xueqi Zhang wrote:
> Add mt8196 smi support in the bindings.
> Since mt8196 has more than 32 SMI larbs, update 'mediatek,larb-id'
> maximum to 63.
> 
> Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
> ---
>  .../mediatek,smi-common.yaml                  |   4 +-
>  .../memory-controllers/mediatek,smi-larb.yaml |   4 +-
>  .../dt-bindings/memory/mt8196-memory-port.h   | 460 ++++++++++++++++++
>  include/dt-bindings/memory/mtk-memory-port.h  |   4 +-
>  4 files changed, 468 insertions(+), 4 deletions(-)
>  create mode 100644 include/dt-bindings/memory/mt8196-memory-port.h
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Xueqi Zhang]

MT8196 SMI commons is backed up/restored by RTFF HW.
It doesn't need SW control the register backup/store
in the runtime callback.Therefore, add a flag skip_rpm
to help skip RPM operations for SMI commons.

Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
---
 drivers/memory/mtk-smi.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index a8f5467d6b31..b9affa3c3185 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -123,6 +123,7 @@ static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1
 struct mtk_smi_common_plat {
 	enum mtk_smi_type	type;
 	bool			has_gals;
+	bool			skip_rpm;
 	u32			bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
 
 	const struct mtk_smi_reg_pair	*init;
@@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
 {
 	int i, ret;
 
+	if (smi->plat->skip_rpm)
+		return 0;
+
 	for (i = 0; i < clk_nr_required; i++)
 		smi->clks[i].id = clks[i];
 	ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
@@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
 	common->dev = dev;
 	common->plat = of_device_get_match_data(dev);
 
-	if (common->plat->has_gals) {
+	if (!common->plat->skip_rpm && common->plat->has_gals) {
 		if (common->plat->type == MTK_SMI_GEN2)
 			clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
 		else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
@@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
 	}
 
 	/* link its smi-common if this is smi-sub-common */
-	if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
+	if (common->plat->type == MTK_SMI_GEN2_SUB_COMM && !common->plat->skip_rpm) {
 		ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
 		if (ret < 0)
 			return ret;
 	}
 
-	pm_runtime_enable(dev);
+	if (!common->plat->skip_rpm)
+		pm_runtime_enable(dev);
 	platform_set_drvdata(pdev, common);
 	return 0;
 }
-- 
2.46.0

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[AngeloGioacchino Del Regno]

Il 20/03/25 08:36, Xueqi Zhang ha scritto:
> MT8196 SMI commons is backed up/restored by RTFF HW.
> It doesn't need SW control the register backup/store
> in the runtime callback.Therefore, add a flag skip_rpm
> to help skip RPM operations for SMI commons.
> 
> Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>

So the MT8196 SMI common doesn't require any clocks?

That's fine for me, but this looks bloody similar to MT6989's SMI common, which
is SMI GEN3 and not GEN2....

....so, are you sure that you need a `skip_rpm` flag and not new MTK_SMI_GEN3 and
MTK_SMI_GEN3_SUB_COMM types? :-)

Regards,
Angelo

> ---
>   drivers/memory/mtk-smi.c | 11 ++++++++---
>   1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> index a8f5467d6b31..b9affa3c3185 100644
> --- a/drivers/memory/mtk-smi.c
> +++ b/drivers/memory/mtk-smi.c
> @@ -123,6 +123,7 @@ static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1
>   struct mtk_smi_common_plat {
>   	enum mtk_smi_type	type;
>   	bool			has_gals;
> +	bool			skip_rpm;
>   	u32			bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
>   
>   	const struct mtk_smi_reg_pair	*init;
> @@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
>   {
>   	int i, ret;
>   
> +	if (smi->plat->skip_rpm)
> +		return 0;
> +
>   	for (i = 0; i < clk_nr_required; i++)
>   		smi->clks[i].id = clks[i];
>   	ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
> @@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
>   	common->dev = dev;
>   	common->plat = of_device_get_match_data(dev);
>   
> -	if (common->plat->has_gals) {
> +	if (!common->plat->skip_rpm && common->plat->has_gals) {
>   		if (common->plat->type == MTK_SMI_GEN2)
>   			clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
>   		else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
> @@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct platform_device *pdev)
>   	}
>   
>   	/* link its smi-common if this is smi-sub-common */
> -	if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
> +	if (common->plat->type == MTK_SMI_GEN2_SUB_COMM && !common->plat->skip_rpm) {
>   		ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
>   		if (ret < 0)
>   			return ret;
>   	}
>   
> -	pm_runtime_enable(dev);
> +	if (!common->plat->skip_rpm)
> +		pm_runtime_enable(dev);
>   	platform_set_drvdata(pdev, common);
>   	return 0;
>   }

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Xueqi Zhang (张雪琦)]

hi Angelo

First of all, please accept my apologies for the delayed response. I
have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI
related tasks recently.

Regarding your question, my previous description in the patch was not
accurate enough and may have caused some confusion. In fact, not all
SMI commons have their backup/restore handled by the RTFF hardware. The
SMI commons are distributed across various subsystems (e.g., mminfra,
venc, display, cam, etc.). Currently, only the SMI common under the
mminfra subsystem is backed up and restored by the RTFF hardware.

Therefore, I believe adding a specific skip_rpm flag is more
appropriate here. If we were to differentiate this based on a new
MTK_SMI_GEN3 type, it would imply that all SMI common modules of that
generation would skip the RPM operations, which is not the intended
behavior.

To make this clearer, I plan to update the commit message in the next
version as follows:

Subject: memory: mtk-smi: Add skip_rpm flag for certain MT8196 SMI
commons

Body:
On MT8196, certain SMI commons are backed up and restored by the RTFF
(Real-Time Function Fix) hardware rather than by software.

For these specific SMI commons, software-controlled register backup and
restore in the runtime callback is no longer necessary. Therefore,
introduce a skip_rpm flag to bypass these redundant RPM operations for
these SMI commons.

What do you think about this approach?

For reference, here is the link to the patch series on Patchwork:

https://patchwork.kernel.org/project/linux-mediatek/list/?series=945811&archive=both

Thanks,
Xueqi

On Thu, 2025-03-20 at 13:11 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 20/03/25 08:36, Xueqi Zhang ha scritto:
> > MT8196 SMI commons is backed up/restored by RTFF HW.
> > It doesn't need SW control the register backup/store
> > in the runtime callback.Therefore, add a flag skip_rpm
> > to help skip RPM operations for SMI commons.
> > 
> > Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
> 
> So the MT8196 SMI common doesn't require any clocks?
> 
> That's fine for me, but this looks bloody similar to MT6989's SMI
> common, which
> is SMI GEN3 and not GEN2....
> 
> ....so, are you sure that you need a `skip_rpm` flag and not new
> MTK_SMI_GEN3 and
> MTK_SMI_GEN3_SUB_COMM types? :-)
> 
> Regards,
> Angelo
> 
> > ---
> >   drivers/memory/mtk-smi.c | 11 ++++++++---
> >   1 file changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index a8f5467d6b31..b9affa3c3185 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -123,6 +123,7 @@ static const char * const mtk_smi_common_clks[]
> > = {"apb", "smi", "gals0", "gals1
> >   struct mtk_smi_common_plat {
> >       enum mtk_smi_type       type;
> >       bool                    has_gals;
> > +     bool                    skip_rpm;
> >       u32                     bus_sel; /* Balance some larbs to
> > enter mmu0 or mmu1 */
> > 
> >       const struct mtk_smi_reg_pair   *init;
> > @@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct device
> > *dev, struct mtk_smi *smi,
> >   {
> >       int i, ret;
> > 
> > +     if (smi->plat->skip_rpm)
> > +             return 0;
> > +
> >       for (i = 0; i < clk_nr_required; i++)
> >               smi->clks[i].id = clks[i];
> >       ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
> > @@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       common->dev = dev;
> >       common->plat = of_device_get_match_data(dev);
> > 
> > -     if (common->plat->has_gals) {
> > +     if (!common->plat->skip_rpm && common->plat->has_gals) {
> >               if (common->plat->type == MTK_SMI_GEN2)
> >                       clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
> >               else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
> > @@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       }
> > 
> >       /* link its smi-common if this is smi-sub-common */
> > -     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
> > +     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM && !common-
> > >plat->skip_rpm) {
> >               ret = mtk_smi_device_link_common(dev, &common-
> > >smi_common_dev);
> >               if (ret < 0)
> >                       return ret;
> >       }
> > 
> > -     pm_runtime_enable(dev);
> > +     if (!common->plat->skip_rpm)
> > +             pm_runtime_enable(dev);
> >       platform_set_drvdata(pdev, common);
> >       return 0;
> >   }
> 
> 

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Xueqi Zhang (张雪琦)]

Hi Angelo

First of all, please accept my apologies for the delayed response. I
have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI
related tasks recently.

Regarding your question, my previous description in the patch was not
accurate enough and may have caused some confusion. In fact, not all
SMI commons have their backup/restore handled by the RTFF hardware. The
SMI commons are distributed across various subsystems (e.g., mminfra,
venc, display, cam, etc.). Currently, only the SMI common under the
mminfra subsystem is backed up and restored by the RTFF hardware.

Therefore, I believe adding a specific skip_rpm flag is more
appropriate here. If we were to differentiate this based on a new
MTK_SMI_GEN3 type, it would imply that all SMI common modules of that
generation would skip the RPM operations, which is not the intended
behavior.

To make this clearer, I plan to update the commit message in the next
version as follows:

Subject: memory: mtk-smi: Add skip_rpm flag for certain MT8196 SMI
commons

Body:
On MT8196, certain SMI commons are backed up and restored by the RTFF
hardware rather than by software.

For these specific SMI commons, software-controlled register backup and
restore in the runtime callback is no longer necessary. Therefore,
introduce a skip_rpm flag to bypass these redundant RPM operations for
these SMI commons.

What do you think about this approach?

Thanks,
Xueqi

On Thu, 2025-03-20 at 13:11 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 20/03/25 08:36, Xueqi Zhang ha scritto:
> > MT8196 SMI commons is backed up/restored by RTFF HW.
> > It doesn't need SW control the register backup/store
> > in the runtime callback.Therefore, add a flag skip_rpm
> > to help skip RPM operations for SMI commons.
> > 
> > Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
> 
> So the MT8196 SMI common doesn't require any clocks?
> 
> That's fine for me, but this looks bloody similar to MT6989's SMI
> common, which
> is SMI GEN3 and not GEN2....
> 
> ....so, are you sure that you need a `skip_rpm` flag and not new
> MTK_SMI_GEN3 and
> MTK_SMI_GEN3_SUB_COMM types? :-)
> 
> Regards,
> Angelo
> 
> > ---
> >   drivers/memory/mtk-smi.c | 11 ++++++++---
> >   1 file changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index a8f5467d6b31..b9affa3c3185 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -123,6 +123,7 @@ static const char * const mtk_smi_common_clks[]
> > = {"apb", "smi", "gals0", "gals1
> >   struct mtk_smi_common_plat {
> >       enum mtk_smi_type       type;
> >       bool                    has_gals;
> > +     bool                    skip_rpm;
> >       u32                     bus_sel; /* Balance some larbs to
> > enter mmu0 or mmu1 */
> > 
> >       const struct mtk_smi_reg_pair   *init;
> > @@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct device
> > *dev, struct mtk_smi *smi,
> >   {
> >       int i, ret;
> > 
> > +     if (smi->plat->skip_rpm)
> > +             return 0;
> > +
> >       for (i = 0; i < clk_nr_required; i++)
> >               smi->clks[i].id = clks[i];
> >       ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
> > @@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       common->dev = dev;
> >       common->plat = of_device_get_match_data(dev);
> > 
> > -     if (common->plat->has_gals) {
> > +     if (!common->plat->skip_rpm && common->plat->has_gals) {
> >               if (common->plat->type == MTK_SMI_GEN2)
> >                       clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
> >               else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
> > @@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       }
> > 
> >       /* link its smi-common if this is smi-sub-common */
> > -     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
> > +     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM && !common-
> > >plat->skip_rpm) {
> >               ret = mtk_smi_device_link_common(dev, &common-
> > >smi_common_dev);
> >               if (ret < 0)
> >                       return ret;
> >       }
> > 
> > -     pm_runtime_enable(dev);
> > +     if (!common->plat->skip_rpm)
> > +             pm_runtime_enable(dev);
> >       platform_set_drvdata(pdev, common);
> >       return 0;
> >   }
> 
> 

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Xueqi Zhang (张雪琦)]

Hi Angelo,

First of all, please accept my apologies for the delayed response. I 
have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI 
related tasks recently.

Regarding your question, my previous description in the patch was not 
accurate enough and may have caused some confusion. In fact, not 
all SMI commons have their backup/restore handled by the RTFF 
hardware. The SMI commons are distributed across various subsystems 
(e.g., mminfra, venc, display, cam, etc.). Currently, only the SMI 
common under the mminfra subsystem is backed up and restored by 
the RTFF hardware.

Therefore, I believe adding a specific 'skip_rpm' flag is more 
appropriate here. If we were to differentiate this based on a new 
MTK_SMI_GEN3 type, it would imply that all SMI common modules of 
that generation would skip the RPM operations, which is not the 
intended behavior.

To make this clearer, I plan to update the commit message in the 
next version as follows:

Subject: memory: mtk-smi: Add skip_rpm flag for certain MT8196 SMI
commons

Body:
On MT8196, certain SMI commons are backed up and restored by the RTFF 
hardware rather than by software. 

For these specific SMI commons, software-controlled register backup 
and restore in the runtime callback is no longer necessary. Therefore, 
introduce a 'skip_rpm' flag to bypass these redundant RPMoperations
for these SMI commons.

What do you think about this approach?

For reference, here is the link to the patch series on Patchwork:

https://patchwork.kernel.org/project/linux-mediatek/list/?series=945811&archive=both

Thanks,
Xueqi

On Thu, 2025-03-20 at 13:11 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 20/03/25 08:36, Xueqi Zhang ha scritto:
> > MT8196 SMI commons is backed up/restored by RTFF HW.
> > It doesn't need SW control the register backup/store
> > in the runtime callback.Therefore, add a flag skip_rpm
> > to help skip RPM operations for SMI commons.
> > 
> > Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
> 
> So the MT8196 SMI common doesn't require any clocks?
> 
> That's fine for me, but this looks bloody similar to MT6989's SMI
> common, which
> is SMI GEN3 and not GEN2....
> 
> ....so, are you sure that you need a `skip_rpm` flag and not new
> MTK_SMI_GEN3 and
> MTK_SMI_GEN3_SUB_COMM types? :-)
> 
> Regards,
> Angelo
> 
> > ---
> >   drivers/memory/mtk-smi.c | 11 ++++++++---
> >   1 file changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index a8f5467d6b31..b9affa3c3185 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -123,6 +123,7 @@ static const char * const mtk_smi_common_clks[]
> > = {"apb", "smi", "gals0", "gals1
> >   struct mtk_smi_common_plat {
> >       enum mtk_smi_type       type;
> >       bool                    has_gals;
> > +     bool                    skip_rpm;
> >       u32                     bus_sel; /* Balance some larbs to
> > enter mmu0 or mmu1 */
> > 
> >       const struct mtk_smi_reg_pair   *init;
> > @@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct device
> > *dev, struct mtk_smi *smi,
> >   {
> >       int i, ret;
> > 
> > +     if (smi->plat->skip_rpm)
> > +             return 0;
> > +
> >       for (i = 0; i < clk_nr_required; i++)
> >               smi->clks[i].id = clks[i];
> >       ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
> > @@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       common->dev = dev;
> >       common->plat = of_device_get_match_data(dev);
> > 
> > -     if (common->plat->has_gals) {
> > +     if (!common->plat->skip_rpm && common->plat->has_gals) {
> >               if (common->plat->type == MTK_SMI_GEN2)
> >                       clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
> >               else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
> > @@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       }
> > 
> >       /* link its smi-common if this is smi-sub-common */
> > -     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
> > +     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM && !common-
> > >plat->skip_rpm) {
> >               ret = mtk_smi_device_link_common(dev, &common-
> > >smi_common_dev);
> >               if (ret < 0)
> >                       return ret;
> >       }
> > 
> > -     pm_runtime_enable(dev);
> > +     if (!common->plat->skip_rpm)
> > +             pm_runtime_enable(dev);
> >       platform_set_drvdata(pdev, common);
> >       return 0;
> >   }
> 
> 

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Xueqi Zhang (张雪琦)]

Hi Angelo,

First of all, please accept my apologies for the delayed response. I 
have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI 
related tasks recently.

Regarding your question, my previous description in the patch was not 
accurate enough and may have caused some confusion. In fact, not 
all SMI commons have their backup/restore handled by the RTFF 
hardware. The SMI commons are distributed across various subsystems 
(e.g., mminfra, venc, display, cam, etc.). Currently, only the SMI 
common under the mminfra subsystem is backed up and restored by 
the RTFF hardware.

Therefore, I believe adding a specific 'skip_rpm' flag is more 
appropriate here. If we were to differentiate this based on a new 
MTK_SMI_GEN3 type, it would imply that all SMI common modules of 
that generation would skip the RPM operations, which is not the 
intended behavior.

To make this clearer, I plan to update the commit message in the 
next version as follows:

Subject: memory: mtk-smi: Add skip_rpm flag for certain MT8196 SMI
commons

Body:
On MT8196, certain SMI commons are backed up and restored by the RTFF 
hardware rather than by software. 

For these specific SMI commons, software-controlled register backup 
and restore in the runtime callback is no longer necessary. Therefore, 
introduce a 'skip_rpm' flag to bypass these redundant RPMoperations
for these SMI commons.

What do you think about this approach?

Thanks,
Xueqi

On Thu, 2025-03-20 at 13:11 +0100, AngeloGioacchino Del Regno wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
> 
> 
> Il 20/03/25 08:36, Xueqi Zhang ha scritto:
> > MT8196 SMI commons is backed up/restored by RTFF HW.
> > It doesn't need SW control the register backup/store
> > in the runtime callback.Therefore, add a flag skip_rpm
> > to help skip RPM operations for SMI commons.
> > 
> > Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
> 
> So the MT8196 SMI common doesn't require any clocks?
> 
> That's fine for me, but this looks bloody similar to MT6989's SMI
> common, which
> is SMI GEN3 and not GEN2....
> 
> ....so, are you sure that you need a `skip_rpm` flag and not new
> MTK_SMI_GEN3 and
> MTK_SMI_GEN3_SUB_COMM types? :-)
> 
> Regards,
> Angelo
> 
> > ---
> >   drivers/memory/mtk-smi.c | 11 ++++++++---
> >   1 file changed, 8 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
> > index a8f5467d6b31..b9affa3c3185 100644
> > --- a/drivers/memory/mtk-smi.c
> > +++ b/drivers/memory/mtk-smi.c
> > @@ -123,6 +123,7 @@ static const char * const mtk_smi_common_clks[]
> > = {"apb", "smi", "gals0", "gals1
> >   struct mtk_smi_common_plat {
> >       enum mtk_smi_type       type;
> >       bool                    has_gals;
> > +     bool                    skip_rpm;
> >       u32                     bus_sel; /* Balance some larbs to
> > enter mmu0 or mmu1 */
> > 
> >       const struct mtk_smi_reg_pair   *init;
> > @@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct device
> > *dev, struct mtk_smi *smi,
> >   {
> >       int i, ret;
> > 
> > +     if (smi->plat->skip_rpm)
> > +             return 0;
> > +
> >       for (i = 0; i < clk_nr_required; i++)
> >               smi->clks[i].id = clks[i];
> >       ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
> > @@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       common->dev = dev;
> >       common->plat = of_device_get_match_data(dev);
> > 
> > -     if (common->plat->has_gals) {
> > +     if (!common->plat->skip_rpm && common->plat->has_gals) {
> >               if (common->plat->type == MTK_SMI_GEN2)
> >                       clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
> >               else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
> > @@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct
> > platform_device *pdev)
> >       }
> > 
> >       /* link its smi-common if this is smi-sub-common */
> > -     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
> > +     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM && !common-
> > >plat->skip_rpm) {
> >               ret = mtk_smi_device_link_common(dev, &common-
> > >smi_common_dev);
> >               if (ret < 0)
> >                       return ret;
> >       }
> > 
> > -     pm_runtime_enable(dev);
> > +     if (!common->plat->skip_rpm)
> > +             pm_runtime_enable(dev);
> >       platform_set_drvdata(pdev, common);
> >       return 0;
> >   }
> 
> 

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Krzysztof Kozlowski]

On 18/05/2026 09:16, Xueqi Zhang (张雪琦) wrote:
> Hi Angelo,
> 
> First of all, please accept my apologies for the delayed response. I 
> have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI 
> related tasks recently.
> 


How may times are you going to send it? I counted FOUR already!

https://lore.kernel.org/all/?q=%22Re%3A+%5BPATCH+2%2F3%5D+memory%3A+mtk-smi%3A+Add+a+flag+skip_rpm%22

Best regards,
Krzysztof

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Xueqi Zhang (张雪琦)]

hi Krzysztof

My apologies for the multiple emails! I've been having some technical
issues with my mail client's plain-text settings and thought my
previous attempts had failed.Thanks for the reminder!

thanks
xueqi

On Mon, 2026-05-18 at 09:18 +0200, Krzysztof Kozlowski wrote:
> On 18/05/2026 09:16, Xueqi Zhang (张雪琦) wrote:
> > Hi Angelo,
> > 
> > First of all, please accept my apologies for the delayed response.
> > I 
> > have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI 
> > related tasks recently.
> > 
> 
> 
> How may times are you going to send it? I counted FOUR already!
> 
> 
https://lore.kernel.org/all/?q=%22Re%3A+%5BPATCH+2%2F3%5D+memory%3A+mtk-smi%3A+Add+a+flag+skip_rpm%22
>  
> 
> Best regards,
> Krzysztof

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[AngeloGioacchino Del Regno]

On 5/18/26 09:16, Xueqi Zhang (张雪琦) wrote:
> Hi Angelo,
> 
> First of all, please accept my apologies for the delayed response. I
> have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI
> related tasks recently.
> 
> Regarding your question, my previous description in the patch was not
> accurate enough and may have caused some confusion. In fact, not
> all SMI commons have their backup/restore handled by the RTFF
> hardware. The SMI commons are distributed across various subsystems
> (e.g., mminfra, venc, display, cam, etc.). Currently, only the SMI
> common under the mminfra subsystem is backed up and restored by
> the RTFF hardware.
> 
> Therefore, I believe adding a specific 'skip_rpm' flag is more
> appropriate here. If we were to differentiate this based on a new
> MTK_SMI_GEN3 type, it would imply that all SMI common modules of
> that generation would skip the RPM operations, which is not the
> intended behavior.
> 
> To make this clearer, I plan to update the commit message in the
> next version as follows:
> 
> Subject: memory: mtk-smi: Add skip_rpm flag for certain MT8196 SMI
> commons

memory: mtk-smi: Allow no clocks for RTFF managed SMI commons

> 
> Body:
> On MT8196, certain SMI commons are backed up and restored by the RTFF
> hardware rather than by software.
> 
> For these specific SMI commons, software-controlled register backup
> and restore in the runtime callback is no longer necessary. Therefore,
> introduce a 'skip_rpm' flag to bypass these redundant RPMoperations
> for these SMI commons.
> 
> What do you think about this approach?
> 

That would be kind-of ok, but keep in mind: pm_runtime doesn't only manage clocks.

I think that the best option here would be to allow having no clocks instead,
and to still call pm_runtime_{en,dis}able() - as that would get a bit more
future-proof, should any other (newer, older, etc) SoC need to declare any power
domain but still no clocks.

So at this point, I think that just doing something like:

	if (common->plat->has_gals) {
		if (common->plat->rtff_managed) <--- not "skip_rpm"
			clk_required = 0;
		else if (common->plat->type == MTK_SMI_GEN2)
			clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
		else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
			clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
	}

should be sufficient (and/or check zero required clocks in smi_dts_clk_init).

Cheers,
Angelo

> Thanks,
> Xueqi
> 
> On Thu, 2025-03-20 at 13:11 +0100, AngeloGioacchino Del Regno wrote:
>> External email : Please do not click links or open attachments until
>> you have verified the sender or the content.
>>
>>
>> Il 20/03/25 08:36, Xueqi Zhang ha scritto:
>>> MT8196 SMI commons is backed up/restored by RTFF HW.
>>> It doesn't need SW control the register backup/store
>>> in the runtime callback.Therefore, add a flag skip_rpm
>>> to help skip RPM operations for SMI commons.
>>>
>>> Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
>>
>> So the MT8196 SMI common doesn't require any clocks?
>>
>> That's fine for me, but this looks bloody similar to MT6989's SMI
>> common, which
>> is SMI GEN3 and not GEN2....
>>
>> ....so, are you sure that you need a `skip_rpm` flag and not new
>> MTK_SMI_GEN3 and
>> MTK_SMI_GEN3_SUB_COMM types? :-)
>>
>> Regards,
>> Angelo
>>
>>> ---
>>>    drivers/memory/mtk-smi.c | 11 ++++++++---
>>>    1 file changed, 8 insertions(+), 3 deletions(-)
>>>
>>> diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
>>> index a8f5467d6b31..b9affa3c3185 100644
>>> --- a/drivers/memory/mtk-smi.c
>>> +++ b/drivers/memory/mtk-smi.c
>>> @@ -123,6 +123,7 @@ static const char * const mtk_smi_common_clks[]
>>> = {"apb", "smi", "gals0", "gals1
>>>    struct mtk_smi_common_plat {
>>>        enum mtk_smi_type       type;
>>>        bool                    has_gals;
>>> +     bool                    skip_rpm;
>>>        u32                     bus_sel; /* Balance some larbs to
>>> enter mmu0 or mmu1 */
>>>
>>>        const struct mtk_smi_reg_pair   *init;
>>> @@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct device
>>> *dev, struct mtk_smi *smi,
>>>    {
>>>        int i, ret;
>>>
>>> +     if (smi->plat->skip_rpm)
>>> +             return 0;
>>> +
>>>        for (i = 0; i < clk_nr_required; i++)
>>>                smi->clks[i].id = clks[i];
>>>        ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
>>> @@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct
>>> platform_device *pdev)
>>>        common->dev = dev;
>>>        common->plat = of_device_get_match_data(dev);
>>>
>>> -     if (common->plat->has_gals) {
>>> +     if (!common->plat->skip_rpm && common->plat->has_gals) {
>>>                if (common->plat->type == MTK_SMI_GEN2)
>>>                        clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
>>>                else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
>>> @@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct
>>> platform_device *pdev)
>>>        }
>>>
>>>        /* link its smi-common if this is smi-sub-common */
>>> -     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
>>> +     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM && !common-
>>>> plat->skip_rpm) {
>>>                ret = mtk_smi_device_link_common(dev, &common-
>>>> smi_common_dev);
>>>                if (ret < 0)
>>>                        return ret;
>>>        }
>>>
>>> -     pm_runtime_enable(dev);
>>> +     if (!common->plat->skip_rpm)
>>> +             pm_runtime_enable(dev);
>>>        platform_set_drvdata(pdev, common);
>>>        return 0;
>>>    }
>>
>>

Re: [PATCH 2/3] memory: mtk-smi: Add a flag skip_rpm

[Xueqi Zhang (张雪琦)]

Hi Angelo,

Thanks for the detailed explanation. I now understand your concern 
about being future-proof and maintaining a unified pm_runtime flow.

In our current MT8196 DTS, these RTFF-managed SMI common nodes 
do not have a 'power-domains' property, as the power is handled 
automatically by the hardware. 

If we follow your suggestion to keep the pm_runtime_{en,dis}able() 
calls but set clk_required = 0, the runtime callback functions 
(smi_common_runtime_resume/suspend) will still be triggered. 

To avoid any potential conflicts with the RTFF hardware's automatic 
register restoration and to save unnecessary software overhead, 
I propose to:
1. Use the 'rtff_managed' flag as you suggested.
2. Set clk_required = 0 when 'rtff_managed' is true.
3. Add a check inside the runtime_resume/suspend callbacks: if 
   'rtff_managed' is true, return immediately without performing 
   any register backup or restoration.

This way, we keep the standard pm_runtime infrastructure as you 
requested, while ensuring the software doesn't interfere with the 
RTFF hardware's operations.

Does this sound reasonable to you?

Thanks,
Xueqi

On Mon, 2026-05-18 at 12:02 +0200, AngeloGioacchino Del Regno wrote:
> On 5/18/26 09:16, Xueqi Zhang (张雪琦) wrote:
> > Hi Angelo,
> > 
> > First of all, please accept my apologies for the delayed response.
> > I
> > have been deeply occupied with MT8196 Aluminium pKVM SMMU and SMI
> > related tasks recently.
> > 
> > Regarding your question, my previous description in the patch was
> > not
> > accurate enough and may have caused some confusion. In fact, not
> > all SMI commons have their backup/restore handled by the RTFF
> > hardware. The SMI commons are distributed across various subsystems
> > (e.g., mminfra, venc, display, cam, etc.). Currently, only the SMI
> > common under the mminfra subsystem is backed up and restored by
> > the RTFF hardware.
> > 
> > Therefore, I believe adding a specific 'skip_rpm' flag is more
> > appropriate here. If we were to differentiate this based on a new
> > MTK_SMI_GEN3 type, it would imply that all SMI common modules of
> > that generation would skip the RPM operations, which is not the
> > intended behavior.
> > 
> > To make this clearer, I plan to update the commit message in the
> > next version as follows:
> > 
> > Subject: memory: mtk-smi: Add skip_rpm flag for certain MT8196 SMI
> > commons
> 
> memory: mtk-smi: Allow no clocks for RTFF managed SMI commons
> 
> > 
> > Body:
> > On MT8196, certain SMI commons are backed up and restored by the
> > RTFF
> > hardware rather than by software.
> > 
> > For these specific SMI commons, software-controlled register backup
> > and restore in the runtime callback is no longer necessary.
> > Therefore,
> > introduce a 'skip_rpm' flag to bypass these redundant RPMoperations
> > for these SMI commons.
> > 
> > What do you think about this approach?
> > 
> 
> That would be kind-of ok, but keep in mind: pm_runtime doesn't only
> manage clocks.
> 
> I think that the best option here would be to allow having no clocks
> instead,
> and to still call pm_runtime_{en,dis}able() - as that would get a bit
> more
> future-proof, should any other (newer, older, etc) SoC need to
> declare any power
> domain but still no clocks.
> 
> So at this point, I think that just doing something like:
> 
> 	if (common->plat->has_gals) {
> 		if (common->plat->rtff_managed) <--- not "skip_rpm"
> 			clk_required = 0;
> 		else if (common->plat->type == MTK_SMI_GEN2)
> 			clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
> 		else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
> 			clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
> 	}
> 
> should be sufficient (and/or check zero required clocks in
> smi_dts_clk_init).
> 
> Cheers,
> Angelo
> 
> > Thanks,
> > Xueqi
> > 
> > On Thu, 2025-03-20 at 13:11 +0100, AngeloGioacchino Del Regno
> > wrote:
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > > 
> > > 
> > > Il 20/03/25 08:36, Xueqi Zhang ha scritto:
> > > > MT8196 SMI commons is backed up/restored by RTFF HW.
> > > > It doesn't need SW control the register backup/store
> > > > in the runtime callback.Therefore, add a flag skip_rpm
> > > > to help skip RPM operations for SMI commons.
> > > > 
> > > > Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
> > > 
> > > So the MT8196 SMI common doesn't require any clocks?
> > > 
> > > That's fine for me, but this looks bloody similar to MT6989's SMI
> > > common, which
> > > is SMI GEN3 and not GEN2....
> > > 
> > > ....so, are you sure that you need a `skip_rpm` flag and not new
> > > MTK_SMI_GEN3 and
> > > MTK_SMI_GEN3_SUB_COMM types? :-)
> > > 
> > > Regards,
> > > Angelo
> > > 
> > > > ---
> > > >    drivers/memory/mtk-smi.c | 11 ++++++++---
> > > >    1 file changed, 8 insertions(+), 3 deletions(-)
> > > > 
> > > > diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-
> > > > smi.c
> > > > index a8f5467d6b31..b9affa3c3185 100644
> > > > --- a/drivers/memory/mtk-smi.c
> > > > +++ b/drivers/memory/mtk-smi.c
> > > > @@ -123,6 +123,7 @@ static const char * const
> > > > mtk_smi_common_clks[]
> > > > = {"apb", "smi", "gals0", "gals1
> > > >    struct mtk_smi_common_plat {
> > > >        enum mtk_smi_type       type;
> > > >        bool                    has_gals;
> > > > +     bool                    skip_rpm;
> > > >        u32                     bus_sel; /* Balance some larbs
> > > > to
> > > > enter mmu0 or mmu1 */
> > > > 
> > > >        const struct mtk_smi_reg_pair   *init;
> > > > @@ -547,6 +548,9 @@ static int mtk_smi_dts_clk_init(struct
> > > > device
> > > > *dev, struct mtk_smi *smi,
> > > >    {
> > > >        int i, ret;
> > > > 
> > > > +     if (smi->plat->skip_rpm)
> > > > +             return 0;
> > > > +
> > > >        for (i = 0; i < clk_nr_required; i++)
> > > >                smi->clks[i].id = clks[i];
> > > >        ret = devm_clk_bulk_get(dev, clk_nr_required, smi-
> > > > >clks);
> > > > @@ -783,7 +787,7 @@ static int mtk_smi_common_probe(struct
> > > > platform_device *pdev)
> > > >        common->dev = dev;
> > > >        common->plat = of_device_get_match_data(dev);
> > > > 
> > > > -     if (common->plat->has_gals) {
> > > > +     if (!common->plat->skip_rpm && common->plat->has_gals) {
> > > >                if (common->plat->type == MTK_SMI_GEN2)
> > > >                        clk_required =
> > > > MTK_SMI_COM_GALS_REQ_CLK_NR;
> > > >                else if (common->plat->type ==
> > > > MTK_SMI_GEN2_SUB_COMM)
> > > > @@ -814,13 +818,14 @@ static int mtk_smi_common_probe(struct
> > > > platform_device *pdev)
> > > >        }
> > > > 
> > > >        /* link its smi-common if this is smi-sub-common */
> > > > -     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
> > > > +     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM &&
> > > > !common-
> > > > > plat->skip_rpm) {
> > > > 
> > > >                ret = mtk_smi_device_link_common(dev, &common-
> > > > > smi_common_dev);
> > > > 
> > > >                if (ret < 0)
> > > >                        return ret;
> > > >        }
> > > > 
> > > > -     pm_runtime_enable(dev);
> > > > +     if (!common->plat->skip_rpm)
> > > > +             pm_runtime_enable(dev);
> > > >        platform_set_drvdata(pdev, common);
> > > >        return 0;
> > > >    }
> > > 
> > > 
> 
> 

[PATCH 3/3] memory: mtk-smi: mt8196: Add smi support

[Xueqi Zhang]

Add support for MT8196 SMI common and SMI LARB.
Since the MT8196 SMI connects with SMMU, rather than MTK_IOMMU,
it doesn't componet_add with mtk_iommu. Add a flag
MTK_SMI_FLAG_CONNECT_SMMUV3 for this.

Signed-off-by: Xueqi Zhang <xueqi.zhang@mediatek.com>
---
 drivers/memory/mtk-smi.c | 134 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 133 insertions(+), 1 deletion(-)

diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index b9affa3c3185..bd68df23e40b 100644
--- a/drivers/memory/mtk-smi.c
+++ b/drivers/memory/mtk-smi.c
@@ -92,6 +92,7 @@
 #define MTK_SMI_FLAG_SW_FLAG		BIT(1)
 #define MTK_SMI_FLAG_SLEEP_CTL		BIT(2)
 #define MTK_SMI_FLAG_CFG_PORT_SEC_CTL	BIT(3)
+#define MTK_SMI_FLAG_CONNECT_SMMUV3	BIT(4)
 #define MTK_SMI_CAPS(flags, _x)		(!!((flags) & (_x)))
 
 struct mtk_smi_reg_pair {
@@ -275,6 +276,9 @@ static int mtk_smi_larb_config_port_gen2_general(struct device *dev)
 		}
 	}
 
+	if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_CONNECT_SMMUV3))
+		return 0;
+
 	for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
 		reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
 		reg |= F_MMU_EN;
@@ -410,6 +414,101 @@ static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
 	[28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
 };
 
+static const u8 mtk_smi_larb_mt8196_ostd[][SMI_LARB_PORT_NR_MAX] = {
+	[0] = {0x4, 0x4, 0x40, 0x40, 0x1, 0x1, 0x2, 0x2, 0x4, 0x4,
+	       0x1, 0x1, 0x1,},
+	[1] = {0x4, 0x4, 0x40, 0x40, 0x32, 0x1, 0x2, 0x2, 0x2, 0x4,
+	       0x4, 0x2, 0x1, 0x1, 0x1, 0x1,},
+	[2] = {0x1, 0x1, 0x1, 0x1, 0x9, 0xb, 0x2a, 0x1, 0x1, 0x1,
+	       0x1, 0x1, 0x1, 0x1, 0x3, 0x1c, 0x1, 0x1,},
+	[3] = {0x2, 0x2, 0x2, 0x2, 0x1a, 0x20, 0x2a, 0x2, 0x1, 0x1,
+	       0x1, 0x1, 0x1, 0x2, 0x8, 0x1c, 0x1, 0x1,},
+	[4] = {0x40, 0x10, 0x10, 0x1, 0x4, 0x10, 0x8, 0x8,},
+	[5] = {0x10, 0x8, 0x40, 0x1e, 0x8, 0x8, 0x4, 0x1,},
+	[6] = {0x40, 0x12, 0x1,},
+	[7] = {0x20, 0x6, 0x6, 0x1, 0x1, 0x24, 0x2b, 0x7, 0x4, 0x1,
+	       0x1, 0xf, 0x3, 0x5, 0x8, 0x8, 0x3, 0x8, 0x5, 0x23,
+	       0x24, 0x4, 0x2, 0xb, 0x10, 0x17, 0x4, 0x8, 0x5, 0x1,
+	       0x1, 0x6,},
+	[8] = {0x20, 0x6, 0x6, 0x1, 0x1, 0x24, 0x2b, 0x7, 0x4, 0x1,
+	       0x1, 0xf, 0x3, 0x5, 0x8, 0x8, 0x3, 0x8, 0x5, 0x23,
+	       0x24, 0x4, 0x2, 0xb, 0x10, 0x17, 0x4, 0x8, 0x5, 0x1,
+	       0x1, 0x6,},
+	[9] = {0x2b, 0x8, 0x9, 0x31, 0x10, 0x26, 0x15, 0x13, 0x7, 0x4,
+	       0x1, 0x1, 0x7, 0xa, 0xb, 0x6, 0x1, 0x1, 0x1, 0x1,
+	       0x1, 0x1, 0xf, 0x9, 0x6, 0x3,},
+	[10] = {0x2b, 0x8, 0x20, 0x1d, 0x19, 0xf, 0x1, 0x3,},
+	[11] = {0x8, 0x16, 0x16, 0x24, 0x1, 0x1, 0x1, 0x3, 0x32, 0x1,
+		0x8, 0x10, 0x16, 0x2, 0x38,},
+	[12] = {0xa, 0xa, 0x1,},
+	[13] = {0x2, 0x20, 0x14, 0x1, 0x1, 0x2, 0x2,},
+	[14] = {0x2, 0x20, 0x14, 0x1, 0x2, 0x2,},
+	[15] = {0x2b, 0x7, 0x31, 0xa, 0x10, 0x10, 0x2b, 0x29, 0x7, 0x1,},
+	[16] = {0x4, 0x4, 0x12, 0x8, 0x8, 0x16, 0x8, 0x6, 0xe, 0x6,
+		0x1e, 0x18, 0x16, 0xe, 0x8, 0xe, 0x8, 0x2, 0x2,},
+	[17] = {0x18, 0x18, 0x8, 0x8, 0xc, 0x4, 0x2,},
+	[18] = {0xb, 0x1, 0x10, 0x1, 0x2,},
+	[19] = {0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x4, 0x2, 0x1, 0x1,
+		0x4, 0x2, 0x1,},
+	[20] = {0x2, 0x2, 0x2, 0x40, 0x40, 0x40, 0x1, 0x2, 0x2, 0x2,
+		0x4, 0x4, 0x4, 0x1, 0x1,},
+	[21] = {0x2, 0x2, 0x2, 0x40, 0x40, 0x40, 0x1, 0x32, 0x32, 0x32,
+		0x2, 0x2, 0x2, 0x4, 0x4, 0x4, 0x2, 0x1,},
+	[22] = {0x8, 0x16, 0x16, 0x24, 0x1, 0x1, 0x1, 0x3, 0x32, 0x1,
+		0x8, 0x10, 0x16, 0x2, 0x38,},
+	[23] = {0x8, 0x16, 0x16, 0x24, 0x1, 0x1, 0x1, 0x3, 0x32, 0x1,
+		0x8, 0x10, 0x16, 0x2, 0x38,},
+	[24] = {0x20, 0x6, 0x6, 0x1, 0x1, 0x24, 0x2b, 0x7, 0x4, 0x1,
+		0x1, 0xf, 0x3, 0x5, 0x8, 0x8, 0x3, 0x8, 0x5, 0x23,
+		0x24, 0x4, 0x2, 0xb, 0x10, 0x17, 0x4, 0x8, 0x5, 0x1,
+		0x1, 0x6,},
+	[25] = {0x2, 0xc, 0x2, 0xc, 0x6, 0x6, 0x3, 0x3, 0x3, 0x1,
+		0x1, 0x2, 0x2,},
+	[26] = {0x2, 0xc, 0x2, 0xc, 0x6, 0x6, 0x3, 0x3, 0x3, 0x1,
+		0x1, 0x2, 0x2,},
+	[27] = {0x6, 0x2, 0xe, 0x6, 0x2, 0x14, 0x14, 0x4, 0x6,},
+	[28] = {0x2b, 0x8, 0x31, 0x10, 0x26, 0x15, 0x1, 0x10,},
+	[29] = {0x2, 0x2, 0x2, 0x2, 0x10, 0xe, 0x6, 0x6, 0x1, 0x1,
+		0x2, 0x2, 0x2, 0x2,},
+	[30] = {0x2, 0x2, 0x2, 0x2,},
+	[31] = {},
+	[32] = {0x1, 0x1, 0x1, 0x1, 0x2, 0x2, 0x32, 0x32, 0x1, 0x2,},
+	[33] = {0xa, 0x1, 0x1, 0x1, 0xa, 0xa, 0xa, 0x1, 0x26, 0x32,
+		0x32, 0x32, 0x32, 0x32, 0x2, 0x1,},
+	[34] = {0x4, 0x4, 0x40, 0x40, 0x1, 0x1, 0x2, 0x2, 0x4, 0x4,
+		0x1, 0x1, 0x1,},
+	[35] = {0x4, 0x4, 0x40, 0x40, 0x32, 0x1, 0x2, 0x2, 0x2, 0x4,
+		0x4, 0x2, 0x1, 0x1, 0x1, 0x1,},
+	[36] = {0x2, 0x2, 0x2, 0x40, 0x40, 0x40, 0x1, 0x2, 0x2, 0x2,
+		0x4, 0x4, 0x4, 0x1, 0x1,},
+	[37] = {0x2, 0x2, 0x2, 0x40, 0x40, 0x40, 0x1, 0x32, 0x32, 0x32,
+		0x2, 0x2, 0x2, 0x4, 0x4, 0x4, 0x2, 0x1,},
+	[38] = {0x29, 0x40, 0x40, 0x7, 0x4, 0x40, 0x4, 0x18, 0x1, 0x1,
+		0x1, 0x7, 0x4,},
+	[39] = {0x16, 0x4, 0x4, 0x8, 0x4, 0x6, 0x6, 0x13, 0x11, 0x20,
+		0x11, 0x1, 0x1, 0x1, 0x9, 0x8, 0x4, 0x6, 0x6,},
+	[40] = {0x9, 0x7, 0x7, 0xb, 0xf, 0x1d, 0x13, 0x6, 0x1, 0x1,
+		0x1, 0x6, 0x9, 0x7, 0xe, 0x3,},
+	[41] = {0x40, 0x8, 0x1, 0x1, 0x2, 0x1, 0x1, 0x1, 0x1, 0x1,
+		0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+		0x1, 0x8, 0x8, 0x8, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1,
+		0x1, 0x1,},
+	[42] = {0x1, 0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+		0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+		0x1, 0x8, 0x8, 0x8, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1,
+		0x1, 0x1,},
+	[43] = {0x4, 0x4, 0x12, 0x8, 0x8, 0x16, 0x8, 0x6, 0xe, 0x6,
+		0x1e, 0x18, 0x16, 0xe, 0x8, 0xe, 0x8, 0x1, 0x1,},
+	[44] = {0x4, 0x4, 0x12, 0x8, 0x8, 0x16, 0x8, 0x6, 0xe, 0x6,
+		0x1e, 0x18, 0x16, 0xe, 0x8, 0xe, 0x8, 0x1, 0x1,},
+	[45] = {0x18, 0x18, 0x8, 0x8, 0xc, 0x4, 0x1,},
+	[46] = {0x18, 0x18, 0x8, 0x8, 0xc, 0x4, 0x1,},
+	[47] = {0x1, 0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+		0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1,
+		0x1, 0x8, 0x8, 0x8, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1,
+		0x1, 0x1,},
+};
+
 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
 	.port_in_larb = {
 		LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
@@ -470,6 +569,13 @@ static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
 	.ostd		            = mtk_smi_larb_mt8195_ostd,
 };
 
+static const struct mtk_smi_larb_gen mtk_smi_larb_mt8196 = {
+	.config_port                = mtk_smi_larb_config_port_gen2_general,
+	.flags_general	            = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
+				      MTK_SMI_FLAG_SLEEP_CTL | MTK_SMI_FLAG_CONNECT_SMMUV3,
+	.ostd		            = mtk_smi_larb_mt8196_ostd,
+};
+
 static const struct of_device_id mtk_smi_larb_of_ids[] = {
 	{.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
 	{.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
@@ -482,6 +588,7 @@ static const struct of_device_id mtk_smi_larb_of_ids[] = {
 	{.compatible = "mediatek,mt8188-smi-larb", .data = &mtk_smi_larb_mt8188},
 	{.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
 	{.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
+	{.compatible = "mediatek,mt8196-smi-larb", .data = &mtk_smi_larb_mt8196},
 	{}
 };
 MODULE_DEVICE_TABLE(of, mtk_smi_larb_of_ids);
@@ -569,6 +676,7 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
 {
 	struct mtk_smi_larb *larb;
 	struct device *dev = &pdev->dev;
+	bool connect_with_smmuv3;
 	int ret;
 
 	larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
@@ -580,6 +688,13 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
 	if (IS_ERR(larb->base))
 		return PTR_ERR(larb->base);
 
+	connect_with_smmuv3 = MTK_SMI_CAPS(larb->larb_gen->flags_general,
+					   MTK_SMI_FLAG_CONNECT_SMMUV3);
+	if (connect_with_smmuv3 && !IS_ENABLED(CONFIG_ARM_SMMU_V3)) {
+		dev_err(dev, " SMMU property conflict.\n");
+		return -EINVAL;
+	}
+
 	ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
 				   MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
 	if (ret)
@@ -593,6 +708,10 @@ static int mtk_smi_larb_probe(struct platform_device *pdev)
 
 	pm_runtime_enable(dev);
 	platform_set_drvdata(pdev, larb);
+
+	if (!connect_with_smmuv3)
+		return 0;
+
 	ret = component_add(dev, &mtk_smi_larb_component_ops);
 	if (ret)
 		goto err_pm_disable;
@@ -610,7 +729,8 @@ static void mtk_smi_larb_remove(struct platform_device *pdev)
 
 	device_link_remove(&pdev->dev, larb->smi_common_dev);
 	pm_runtime_disable(&pdev->dev);
-	component_del(&pdev->dev, &mtk_smi_larb_component_ops);
+	if (!MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_CONNECT_SMMUV3))
+		component_del(&pdev->dev, &mtk_smi_larb_component_ops);
 }
 
 static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
@@ -750,6 +870,16 @@ static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
 	.has_gals = true,
 };
 
+static const struct mtk_smi_common_plat mtk_smi_common_mt8196 = {
+	.type     = MTK_SMI_GEN2,
+	.skip_rpm = true,
+};
+
+static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8196 = {
+	.type     = MTK_SMI_GEN2_SUB_COMM,
+	.skip_rpm = true,
+};
+
 static const struct mtk_smi_common_plat mtk_smi_common_mt8365 = {
 	.type     = MTK_SMI_GEN2,
 	.bus_sel  = F_MMU1_LARB(2) | F_MMU1_LARB(4),
@@ -770,6 +900,8 @@ static const struct of_device_id mtk_smi_common_of_ids[] = {
 	{.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
 	{.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
 	{.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
+	{.compatible = "mediatek,mt8196-smi-common", .data = &mtk_smi_common_gen2},
+	{.compatible = "mediatek,mt8196-smi-sub-common", .data = &mtk_smi_sub_common_mt8196},
 	{.compatible = "mediatek,mt8365-smi-common", .data = &mtk_smi_common_mt8365},
 	{}
 };
-- 
2.46.0