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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>,  Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>
Cc: Weiyi Lu <weiyi.lu@mediatek.com>,
	srv_heupstream@mediatek.com, linux-kernel@vger.kernel.org,
	linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH v4 13/34] clk: mediatek: Add MT8192 camsys clock support
Date: Thu, 22 Oct 2020 20:37:06 +0800	[thread overview]
Message-ID: <1603370247-30437-14-git-send-email-weiyi.lu@mediatek.com> (raw)
In-Reply-To: <1603370247-30437-1-git-send-email-weiyi.lu@mediatek.com>

Add MT8192 camsys clock provider

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 drivers/clk/mediatek/Kconfig          |  6 +++
 drivers/clk/mediatek/Makefile         |  1 +
 drivers/clk/mediatek/clk-mt8192-cam.c | 72 +++++++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/clk/mediatek/clk-mt8192-cam.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 9360fe4..0cb9f73 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -455,6 +455,12 @@ config COMMON_CLK_MT8192_AUDSYS
 	help
 	  This driver supports MediaTek MT8192 audsys clocks.
 
+config COMMON_CLK_MT8192_CAMSYS
+	bool "Clock driver for MediaTek MT8192 camsys"
+	depends on COMMON_CLK_MT8192
+	help
+	  This driver supports MediaTek MT8192 camsys clocks.
+
 config COMMON_CLK_MT8516
 	bool "Clock driver for MediaTek MT8516"
 	depends on ARCH_MEDIATEK || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a6af4b4..f446834 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -63,5 +63,6 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VDECSYS) += clk-mt8183-vdec.o
 obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
 obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
 obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
+obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
 obj-$(CONFIG_COMMON_CLK_MT8516) += clk-mt8516.o
 obj-$(CONFIG_COMMON_CLK_MT8516_AUDSYS) += clk-mt8516-aud.o
diff --git a/drivers/clk/mediatek/clk-mt8192-cam.c b/drivers/clk/mediatek/clk-mt8192-cam.c
new file mode 100644
index 0000000..68d3f6e
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8192-cam.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0-only
+//
+// Copyright (c) 2020 MediaTek Inc.
+// Author: Weiyi Lu <weiyi.lu@mediatek.com>
+
+#include <linux/clk-provider.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mt8192-clk.h>
+
+static const struct mtk_gate_regs cam_cg_regs = {
+	.set_ofs = 0x4,
+	.clr_ofs = 0x8,
+	.sta_ofs = 0x0,
+};
+
+#define GATE_CAM(_id, _name, _parent, _shift)	\
+	GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate cam_clks[] = {
+	GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "cam_sel", 0),
+	GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "cam_sel", 1),
+	GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "cam_sel", 2),
+	GATE_CAM(CLK_CAM_CAM, "cam_cam", "cam_sel", 6),
+	GATE_CAM(CLK_CAM_CAMTG, "cam_camtg", "cam_sel", 7),
+	GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "cam_sel", 8),
+	GATE_CAM(CLK_CAM_CAMSV0, "cam_camsv0", "cam_sel", 9),
+	GATE_CAM(CLK_CAM_CAMSV1, "cam_camsv1", "cam_sel", 10),
+	GATE_CAM(CLK_CAM_CAMSV2, "cam_camsv2", "cam_sel", 11),
+	GATE_CAM(CLK_CAM_CAMSV3, "cam_camsv3", "cam_sel", 12),
+	GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "cam_sel", 13),
+	GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "cam_sel", 14),
+	GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "cam_sel", 15),
+	GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "cam_sel", 17),
+	GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "cam_sel", 18),
+	GATE_CAM(CLK_CAM_CAM2MM_GALS, "cam2mm_gals", "cam_sel", 19),
+};
+
+static int clk_mt8192_cam_probe(struct platform_device *pdev)
+{
+	struct clk_onecell_data *clk_data;
+	struct device_node *node = pdev->dev.of_node;
+	int r;
+
+	clk_data = mtk_alloc_clk_data(CLK_CAM_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	r = mtk_clk_register_gates(node, cam_clks, ARRAY_SIZE(cam_clks), clk_data);
+	if (r)
+		return r;
+
+	return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
+static const struct of_device_id of_match_clk_mt8192_cam[] = {
+	{ .compatible = "mediatek,mt8192-camsys", },
+	{}
+};
+
+static struct platform_driver clk_mt8192_cam_drv = {
+	.probe = clk_mt8192_cam_probe,
+	.driver = {
+		.name = "clk-mt8192-cam",
+		.of_match_table = of_match_clk_mt8192_cam,
+	},
+};
+
+builtin_platform_driver(clk_mt8192_cam_drv);
-- 
1.8.1.1.dirty
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  parent reply	other threads:[~2020-10-22 12:55 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-22 12:36 [PATCH v4 00/34] Mediatek MT8192 clock support Weiyi Lu
2020-10-22 12:36 ` [PATCH v4 01/34] dt-bindings: ARM: Mediatek: Add new document bindings of camsys raw controller Weiyi Lu
2020-10-22 12:36 ` [PATCH v4 02/34] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller Weiyi Lu
2020-10-22 12:36 ` [PATCH v4 03/34] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller Weiyi Lu
2020-10-22 12:36 ` [PATCH v4 04/34] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Weiyi Lu
2020-10-22 12:36 ` [PATCH v4 05/34] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller Weiyi Lu
2020-10-22 12:36 ` [PATCH v4 06/34] dt-bindings: ARM: Mediatek: Add new document bindings of vdecsys soc controller Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 07/34] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 08/34] clk: mediatek: Add dt-bindings of MT8192 clocks Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 09/34] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 10/34] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 11/34] clk: mediatek: Add MT8192 basic clocks support Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 12/34] clk: mediatek: Add MT8192 audio clock support Weiyi Lu
2020-10-22 12:37 ` Weiyi Lu [this message]
2020-10-22 12:37 ` [PATCH v4 14/34] clk: mediatek: Add MT8192 camsys rawa " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 15/34] clk: mediatek: Add MT8192 camsys rawb " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 16/34] clk: mediatek: Add MT8192 camsys rawc " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 17/34] clk: mediatek: Add MT8192 imgsys " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 18/34] clk: mediatek: Add MT8192 imgsys2 " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 19/34] clk: mediatek: Add MT8192 imp i2c wrapper c " Weiyi Lu
2020-10-24 16:22   ` Yingjoe Chen
2020-10-22 12:37 ` [PATCH v4 20/34] clk: mediatek: Add MT8192 imp i2c wrapper e " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 21/34] clk: mediatek: Add MT8192 imp i2c wrapper n " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 22/34] clk: mediatek: Add MT8192 imp i2c wrapper s " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 23/34] clk: mediatek: Add MT8192 imp i2c wrapper w " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 24/34] clk: mediatek: Add MT8192 imp i2c wrapper ws " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 25/34] clk: mediatek: Add MT8192 ipesys " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 26/34] clk: mediatek: Add MT8192 mdpsys " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 27/34] clk: mediatek: Add MT8192 mfgcfg " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 28/34] clk: mediatek: Add MT8192 mmsys " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 29/34] clk: mediatek: Add MT8192 msdc top " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 30/34] clk: mediatek: Add MT8192 msdc " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 31/34] clk: mediatek: Add MT8192 scp adsp " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 32/34] clk: mediatek: Add MT8192 vdecsys " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 33/34] clk: mediatek: Add MT8192 vdecsys soc " Weiyi Lu
2020-10-22 12:37 ` [PATCH v4 34/34] clk: mediatek: Add MT8192 vencsys " Weiyi Lu

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