Re: [PATCH 1/2] arm64: ptrauth: add pointer authentication Armv8.6 enhanced feature

From: Amit Kachhap <amit.kachhap@arm.com>
To: Will Deacon <will@kernel.org>, Mark Rutland <mark.rutland@arm.com>
Cc: Kees Cook <keescook@chromium.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Kristina Martsenko <kristina.martsenko@arm.com>,
	Mark Brown <broonie@kernel.org>,
	James Morse <james.morse@arm.com>,
	Vincenzo Frascino <Vincenzo.Frascino@arm.com>,
	Dave Martin <Dave.Martin@arm.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/2] arm64: ptrauth: add pointer authentication Armv8.6 enhanced feature
Date: Mon, 2 Mar 2020 18:18:17 +0530	[thread overview]
Message-ID: <194f0008-4071-b143-f326-2f067e3b82fe@arm.com> (raw)
In-Reply-To: <20200228122345.GC3275@willie-the-truck>

Hi Will,

On 2/28/20 5:53 PM, Will Deacon wrote:
> On Fri, Feb 28, 2020 at 12:03:14PM +0000, Mark Rutland wrote:
>> On Fri, Feb 28, 2020 at 11:57:37AM +0000, Will Deacon wrote:
>>> On Wed, Feb 19, 2020 at 06:30:39PM +0530, Amit Daniel Kachhap wrote:
>>>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>>>> index 8d1c979..a4f8adb 100644
>>>> --- a/arch/arm64/kernel/cpufeature.c
>>>> +++ b/arch/arm64/kernel/cpufeature.c
>>>> @@ -154,9 +154,9 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
>>>>   	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
>>>>   	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
>>>>   	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
>>>> -		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
>>>> +		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
>>>>   	ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
>>>> -		       FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
>>>> +		       FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
>>>>   	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
>>>>   	ARM64_FTR_END,
>>>
>>> Hmm. This is a user-visible change and should probably be in its own patch.
>>> It also means we will no longer advertise PAC on systems where not all of
>>> the cores have "Enhanced PAC"; is that really necessary?
>>
>> It matters for KVM, since a guest won't expect the enhanced PAC trap if
>> the ID registers say it does not have it.
>>
>> For userspace, the difference is it'll get a SIGILL on the AUT*
>> instruction rather than a SIGSEGV when using the result of the AUT*
>> instruction.
> 
> Yes, if PAC is enabled.
> 
>>> Generally we rely on incremental updates to unsigned ID register fields
>>> being a superset (i.e. compatible with) the old behaviour. If that's not
>>> the case here, then older kernels are broken and we may need new HWCAPs.
>>
>> In this case, the behaviour isn't a strict superset. Enhanced PAC
>> unconditionally changed the behaviour of AUT* (i.e. there's no opt-in
>> with a control bit), but it's not clear to me how much this matters for
>> userspace.
> 
> Doesn't that violate D13.1.3 "Principles of the ID scheme for fields in
> ID registers"?
> 
> The part I dislike is that older kernels will happily advertise PAC to
> userspace on a system with mismatched legacy/enhanced PAC, and so the
> change above doesn't make sense for userspace because the HWCAPs are
> already unreliable.

How to got about it? Shall I send this part as a separate fix patch
mentioning the requirement for doing it?

//Amit
> 
> Will
> 

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