Re: Re: [RFC PATCH 01/22] dt-bindings: memory: cdns,k3-ddr: Add Cadence K3 DDR controller binding

[MANNURU VENKATESWARLU <v-mannuru@ti.com>]

Hi Krzysztof,

Thank you for the review.

On 15/07/26 10:25, Krzysztof Kozlowski wrote:
> On 14/07/2026 14: 55, MANNURU VENKATESWARLU wrote: > Add device tree 
> binding for the Cadence DDR controller used in TI K3 SoCs. > > 
> Signed-off-by: Neha Malcom Francis <n-francis@ ti. com> > 
> Signed-off-by: Gandhar Deshpande <g-deshpande@ ti. com>
> 
> On 14/07/2026 14:55, MANNURU VENKATESWARLU wrote:
> > Add device tree binding for the Cadence DDR controller used in TI K3 SoCs.
> > 
> > Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
> > Signed-off-by: Gandhar Deshpande <g-deshpande@ti.com>
> > Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
> > ---
> >  .../memory-controllers/ti/cdns,k3-ddr.yaml    | 81 +++++++++++++++++++
> >  1 file changed, 81 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> > 
>
> Where is the rest of 22 patches? I got only these three patches.
>
Sorry for the threading issue. I ran separate 'git send-email' commands 
to target
specific maintainers for each patch, which accidentally broke the series 
layout.
Will fix this for v2 using a proper single-thread approach.

> A nit, subject: drop second/last, redundant "bindings". The
> "dt-bindings" prefix is already stating that these are bindings.
Noted, will drop "binding" from the subject line.
> See also:
> https://urldefense.com/v3/__https://elixir.bootlin.com/linux/v7.1-rc7/source/Documentation/devicetree/bindings/submitting-patches.rst*L23__;Iw!!G3vK!VufvdFJYWNjYPM5GnqHtPsbj-eGrx0jLrAx_YZJ4Zvxail86PMioiY6qiyoVVJs7LkAg0EUeVQ$
Thank you for the references.
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> > new file mode 100644
> > index 0000000000000..89caeb111627a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/ti/cdns,k3-ddr.yaml
> > @@ -0,0 +1,81 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/memory-controllers/ti/cdns,k3-ddr.yaml*__;Iw!!G3vK!VufvdFJYWNjYPM5GnqHtPsbj-eGrx0jLrAx_YZJ4Zvxail86PMioiY6qiyoVVJs7LkDKAFfOoA$
> > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!G3vK!VufvdFJYWNjYPM5GnqHtPsbj-eGrx0jLrAx_YZJ4Zvxail86PMioiY6qiyoVVJs7LkBLS4PG1w$
> > +
> > +title: Cadence DDR controller for K3 devices
> > +
> > +maintainers:
> > +  - Santhosh Kumar K <s-k6@ti.com>
> > +  - Neha Malcom Francis <n-francis@ti.com>
> > +
> > +properties:
> > +  compatible:
> > +    const: cdns,k3-ddr
>
> cdns does not make a K3 SoC.
Valid point. I will revisit the compatible string.
it likely should not carry the K3 suffix on the Cadence side,
using something like "cdns,ddr" instead.

> This is confusing. Are you sure you understand which company products
> you are working on?
>
>
> > +
> > +  reg:
> > +    minItems: 3
>
> Drop.
Will remove minItems.
> > +    maxItems: 3
> > +    description: |
> > +      Address ranges for the different register regions of the DDRSS controller.
> > +      - ctl_cfg: Controller configuration registers
> > +      - ctl_cfg_pi: PHY Interface configuration registers
> > +      - ctl_cfg_phy: PHY configuration registers
>
> Describe items.
Will describe each reg Item
> > +
> > +  reg-names:
> > +    items:
> > +      - const: ctl_cfg
> > +      - const: ctl_cfg_pi
> > +      - const: ctl_cfg_phy
> > +
> > +  bootph-pre-ram: true
>
> Nope
Agreed. Device Tree bindings must strictly describe the hardware itself,not
software or bootloader execution phases. I will remove this U-Boot specific
property entirely from the binding.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - reg-names
> > +
> > +unevaluatedProperties: false
>
> More NO.
will replace with additionalProperties: false.
> Really, can't you make some internal review back there in TI to avoid
> sending something which does not resemble upstream code at all?
>
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +    #include <dt-bindings/soc/ti,sci_pm_domain.h>
> > +
> > +    cbass_main {
>
> NAK
Understood, I will cleanup the example.
>
> > +      #address-cells = <2>;
> > +      #size-cells = <2>;
> > +
> > +      memorycontroller: memorycontroller@2980000 {
>
>
> git grep memorycontroller
>
> And it did not made you thinking that name is wrong? I am done with it.

Correct, my mistake. I will fix the node name to use the generic 
"memory-controller"
format.


>
> > +        compatible = "ti,j721e-ddrss";
>
> Irrelevant. Which binding are you describing here?
The example was Incorrectly focussed on the TI parent wrapper. I will 
trim the example
down to focus strictly on the ddr node.
> Best regards,
> Krzysztof
Thank you,
VENKEY