[RFC PATCH 03/22] dt-bindings: memory: ti,j721s2-msmc: Add TI K3 MSMC binding

[MANNURU VENKATESWARLU <v-mannuru@ti.com>]

Add DT binding for the TI K3 MSMC (Multi-Subsystem Memory
Controller) node present on J721S2, J784S4 and J742S2 SoCs. The
MSMC acts as a bus container for multiple DDR subsystem instances
and carries interleave configuration written by the bootloader.

Signed-off-by: MANNURU VENKATESWARLU <v-mannuru@ti.com>
---
 .../memory-controllers/ti/ti,j721s2-msmc.yaml | 124 ++++++++++++++++++
 1 file changed, 124 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml

diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml
new file mode 100644
index 0000000000000..5ccdc546a121f
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j721s2-msmc.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/ti/ti,j721s2-msmc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI K3 Multi-Subsystem Memory Controller (MSMC)
+
+maintainers:
+  - Neha Malcom Francis <n-francis@ti.com>
+
+description:
+  The K3 MSMC node is present on J721S2, J784S4, and J742S2 SoCs. It acts
+  as a bus container for multiple DDR subsystem instances and carries
+  metadata describing how DDR address space is interleaved across those
+  instances. All properties are configured by the bootloader at boot time
+  prior to OS handoff; the OS treats them as read-only.
+
+properties:
+  compatible:
+    items:
+      - const: ti,j721s2-msmc
+      - const: simple-bus
+
+  '#address-cells':
+    const: 2
+
+  '#size-cells':
+    const: 2
+
+  ranges: true
+
+  bootph-pre-ram: true
+
+  intrlv-gran:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      DDR address interleaving granularity.
+
+  intrlv-size:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      DDR address interleaving region size.
+
+  ecc-enable:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      ECC enable bitmask across DDR instances.
+
+  emif-config:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      EMIF hybrid DDR configuration select.
+
+  emif-active:
+    $ref: /schemas/types.yaml#/definitions/uint32
+    description:
+      Bitmask of active EMIF instances.
+
+patternProperties:
+  "^memorycontroller@[0-9a-f]+$":
+    type: object
+    description: DDR subsystem child node, see ti,j7-ddrss.yaml.
+
+required:
+  - compatible
+  - '#address-cells'
+  - '#size-cells'
+  - ranges
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+    msmc0: msmc {
+        compatible = "ti,j721s2-msmc", "simple-bus";
+        #address-cells = <2>;
+        #size-cells = <2>;
+        ranges;
+        intrlv-gran = <0>;
+        intrlv-size = <0>;
+        ecc-enable  = <0>;
+        emif-config = <0>;
+        emif-active = <0>;
+        bootph-pre-ram;
+
+        memorycontroller0: memorycontroller@2980000 {
+            compatible = "ti,j721s2-ddrss";
+            reg = <0x0 0x02990000 0x0 0x4000>,
+                  <0x0 0x0114000 0x0 0x100>,
+                  <0x0 0x02980000 0x0 0x200>;
+            reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
+            power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
+                            <&k3_pds 96 TI_SCI_PD_SHARED>;
+            interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+            #address-cells = <2>;
+            #size-cells = <2>;
+            ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>;
+            ti,ddr-freq0   = <0>;
+            ti,ddr-freq1   = <0>;
+            ti,ddr-freq2   = <0>;
+            ti,ddr-fhs-cnt = <0>;
+            clocks = <&k3_clks 138 0>, <&k3_clks 43 2>;
+            instance = <0>;
+            bootph-pre-ram;
+
+            ddr0: ddr@0 {
+                compatible = "cdns,k3-ddr";
+                reg = <0x00 0x0000 0x00 0x72c>,
+                      <0x00 0x2000 0x00 0x4b0>,
+                      <0x00 0x4000 0x00 0x163c>;
+                reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy";
+                bootph-pre-ram;
+            };
+
+            ddr_pmu0: ddr-pmu@100 {
+                compatible = "ti,k3-ddr-pmu";
+                reg = <0x00 0x100 0x00 0x14>;
+            };
+        };
+    };
-- 
2.34.1