[PATCH] Use definition for cmpxchg swi

[linux@arm.linux.org.uk (Russell King - ARM Linux)]

On Mon, Nov 09, 2009 at 07:08:52PM +0000, Jamie Lokier wrote:
> Russell King - ARM Linux wrote:
> > I'll add a comment then.
> > 
> > Note, however, that the original code was buggy - it resulted in
> > the '0xfff0' syscall being called instead of '0xffff0' - note the
> > extra 4 bits there.
> 
> Meaning that nobody has ever actually used the original code? :-)

Correct, because SMP on ARM architectures prior to V6 is rather rare.
My only implementation of that is a pile of FPGAs implementing a 4-way
ARM926 SMP system.

> I notice that it loads the syscall number register for EABI
> compatibility, but that instruction could be trivially omitted with
> OABI-compatible kernels, couldn't it?

It could.

> By the way, did you change it to LDR to make it faster?  (I.e. does
> that make it faster?)

Well, we could use one mov and two orr instructions to load the minimum
20 bits of syscall number (which equates to a minimum of 3 cycles) or
one ldr, which can be 1 cycle if the cache is warm.  Since the result
is not used in the following two instructions, there is no impact from
result delays.