[PATCH 0/5] PCIe Xilinx with generic driver for Microblaze and

[PATCH 0/5] PCIe Xilinx with generic driver for Microblaze and

[Bharat Kumar Gogada]

This patch series does modifications to pcie-xilinx.c, to support common
driver on both Zynq and Microblaze architectures.
Microblaze pci-common.c has been modified to support generic driver.

I'm aware Paul Burton <paul.burton@imgtec.com> has also sent patches
related to pcie-xilinx.c, but I'm unable to comment on them. 
I request Paul Burton to please add me in cc list so that I can comment on
those patches.

Bharat Kumar Gogada (5):
  PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function
  PCI: xilinx: Removing struct hw_irq structure.
  PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both    
     Zynq and Microblaze
  PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze
    node.
  Microblaze: Modifying microblaze PCI subsytem to support generic
    Xilinx      AXI PCIe Host Bridge IP driver

 .../devicetree/bindings/pci/xilinx-pcie.txt        |  36 +++-
 arch/microblaze/Kconfig                            |   3 +
 arch/microblaze/pci/pci-common.c                   |  61 +++---
 drivers/pci/host/Kconfig                           |   2 +-
 drivers/pci/host/pcie-xilinx.c                     | 208 ++++-----------------
 5 files changed, 97 insertions(+), 213 deletions(-)

-- 
2.1.1

[PATCH 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function

[Bharat Kumar Gogada]

Removing xilinx_pcie_parse_and_add_res function replacing with
of_pci_get_host_bridge_resources API.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Removing xilinx_pcie_parse_and_add_res function and replacing it
with of_pci_get_host_bridge_resources kernel API which does the same.
---
 drivers/pci/host/pcie-xilinx.c | 108 ++---------------------------------------
 1 file changed, 5 insertions(+), 103 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3c7a0d5..588e568 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -94,8 +94,6 @@
 /* Number of MSI IRQs */
 #define XILINX_NUM_MSI_IRQS		128
 
-/* Number of Memory Resources */
-#define XILINX_MAX_NUM_RESOURCES	3
 
 /**
  * struct xilinx_pcie_port - PCIe port information
@@ -105,7 +103,6 @@
  * @root_busno: Root Bus number
  * @dev: Device pointer
  * @irq_domain: IRQ domain pointer
- * @bus_range: Bus range
  * @resources: Bus Resources
  */
 struct xilinx_pcie_port {
@@ -115,7 +112,6 @@ struct xilinx_pcie_port {
 	u8 root_busno;
 	struct device *dev;
 	struct irq_domain *irq_domain;
-	struct resource bus_range;
 	struct list_head resources;
 };
 
@@ -658,98 +654,6 @@ static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 	return bus;
 }
 
-/**
- * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
- * @port: PCIe port information
- *
- * Return: '0' on success and error value on failure
- */
-static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
-{
-	struct device *dev = port->dev;
-	struct device_node *node = dev->of_node;
-	struct resource *mem;
-	resource_size_t offset;
-	struct of_pci_range_parser parser;
-	struct of_pci_range range;
-	struct resource_entry *win;
-	int err = 0, mem_resno = 0;
-
-	/* Get the ranges */
-	if (of_pci_range_parser_init(&parser, node)) {
-		dev_err(dev, "missing \"ranges\" property\n");
-		return -EINVAL;
-	}
-
-	/* Parse the ranges and add the resources found to the list */
-	for_each_of_pci_range(&parser, &range) {
-
-		if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
-			dev_err(dev, "Maximum memory resources exceeded\n");
-			return -EINVAL;
-		}
-
-		mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
-		if (!mem) {
-			err = -ENOMEM;
-			goto free_resources;
-		}
-
-		of_pci_range_to_resource(&range, node, mem);
-
-		switch (mem->flags & IORESOURCE_TYPE_BITS) {
-		case IORESOURCE_MEM:
-			offset = range.cpu_addr - range.pci_addr;
-			mem_resno++;
-			break;
-		default:
-			err = -EINVAL;
-			break;
-		}
-
-		if (err < 0) {
-			dev_warn(dev, "Invalid resource found %pR\n", mem);
-			continue;
-		}
-
-		err = request_resource(&iomem_resource, mem);
-		if (err)
-			goto free_resources;
-
-		pci_add_resource_offset(&port->resources, mem, offset);
-	}
-
-	/* Get the bus range */
-	if (of_pci_parse_bus_range(node, &port->bus_range)) {
-		u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
-		u8 last;
-
-		last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
-			XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
-
-		port->bus_range = (struct resource) {
-			.name	= node->name,
-			.start	= 0,
-			.end	= last,
-			.flags	= IORESOURCE_BUS,
-		};
-	}
-
-	/* Register bus resource */
-	pci_add_resource(&port->resources, &port->bus_range);
-
-	return 0;
-
-free_resources:
-	release_child_resources(&iomem_resource);
-	resource_list_for_each_entry(win, &port->resources)
-		devm_kfree(dev, win->res);
-	pci_free_resource_list(&port->resources);
-
-	return err;
-}
-
-/**
  * xilinx_pcie_parse_dt - Parse Device tree
  * @port: PCIe port information
  *
@@ -802,6 +706,8 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 	struct hw_pci hw;
 	struct device *dev = &pdev->dev;
 	int err;
+	resource_size_t iobase = 0;
+	LIST_HEAD(res);
 
 	if (!dev->of_node)
 		return -ENODEV;
@@ -826,14 +732,10 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 		return err;
 	}
 
-	/*
-	 * Parse PCI ranges, configuration bus range and
-	 * request their resources
-	 */
-	INIT_LIST_HEAD(&port->resources);
-	err = xilinx_pcie_parse_and_add_res(port);
+	err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff, &res,
+					       &iobase);
 	if (err) {
-		dev_err(dev, "Failed adding resources\n");
+		dev_err(dev, "Getting bridge resources failed\n");
 		return err;
 	}
 
-- 
2.1.1

[PATCH 2/5] PCI: xilinx: Removing struct hw_irq structure.

[Bharat Kumar Gogada]

Removing struct hw_irq and adding generic PCI core API's.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Removing architecure dependecy structure struct hw_irq which is ARM 32-bit
specific structure, and adding generic PCI core API's to register to
PCI subsytem.
Removing funtions which are not being used with generic API's.
---
 drivers/pci/host/pcie-xilinx.c | 80 +++++++++---------------------------------
 1 file changed, 16 insertions(+), 64 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 588e568..3e3757f 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -117,11 +117,6 @@ struct xilinx_pcie_port {
 
 static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
 
-static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
-{
-	return sys->private_data;
-}
-
 static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
 {
 	return readl(port->reg_base + reg);
@@ -163,7 +158,7 @@ static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
  */
 static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+	struct xilinx_pcie_port *port = bus->sysdata;
 
 	/* Check if link is up when trying to access downstream ports */
 	if (bus->number != port->root_busno)
@@ -196,7 +191,7 @@ static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
 static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
 					 unsigned int devfn, int where)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
+	struct xilinx_pcie_port *port = bus->sysdata;
 	int relbus;
 
 	if (!xilinx_pcie_valid_device(bus, devfn))
@@ -228,7 +223,7 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
 
 	if (!test_bit(irq, msi_irq_in_use)) {
 		msi = irq_get_msi_desc(irq);
-		port = sys_to_pcie(msi_desc_to_pci_sysdata(msi));
+		port = msi_desc_to_pci_sysdata(msi);
 		dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
 	} else {
 		clear_bit(irq, msi_irq_in_use);
@@ -277,7 +272,7 @@ static int xilinx_pcie_msi_setup_irq(struct msi_controller *chip,
 				     struct pci_dev *pdev,
 				     struct msi_desc *desc)
 {
-	struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
+	struct xilinx_pcie_port *port = pdev->bus->sysdata;
 	unsigned int irq;
 	int hwirq;
 	struct msi_msg msg;
@@ -614,46 +609,6 @@ static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
 }
 
 /**
- * xilinx_pcie_setup - Setup memory resources
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: '1' on success and error value on failure
- */
-static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
-{
-	struct xilinx_pcie_port *port = sys_to_pcie(sys);
-
-	list_splice_init(&port->resources, &sys->resources);
-
-	return 1;
-}
-
-/**
- * xilinx_pcie_scan_bus - Scan PCIe bus for devices
- * @nr: Bus number
- * @sys: Per controller structure
- *
- * Return: Valid Bus pointer on success and NULL on failure
- */
-static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
-{
-	struct xilinx_pcie_port *port = sys_to_pcie(sys);
-	struct pci_bus *bus;
-
-	port->root_busno = sys->busnr;
-
-	if (IS_ENABLED(CONFIG_PCI_MSI))
-		bus = pci_scan_root_bus_msi(port->dev, sys->busnr,
-					    &xilinx_pcie_ops, sys,
-					    &sys->resources,
-					    &xilinx_pcie_msi_chip);
-	else
-		bus = pci_scan_root_bus(port->dev, sys->busnr,
-					&xilinx_pcie_ops, sys, &sys->resources);
-	return bus;
-}
-
  * xilinx_pcie_parse_dt - Parse Device tree
  * @port: PCIe port information
  *
@@ -703,8 +658,9 @@ static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
 static int xilinx_pcie_probe(struct platform_device *pdev)
 {
 	struct xilinx_pcie_port *port;
-	struct hw_pci hw;
 	struct device *dev = &pdev->dev;
+	struct pci_bus *bus;
+
 	int err;
 	resource_size_t iobase = 0;
 	LIST_HEAD(res);
@@ -738,24 +694,20 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 		dev_err(dev, "Getting bridge resources failed\n");
 		return err;
 	}
-
-	platform_set_drvdata(pdev, port);
-
-	/* Register the device */
-	memset(&hw, 0, sizeof(hw));
-	hw = (struct hw_pci) {
-		.nr_controllers	= 1,
-		.private_data	= (void **)&port,
-		.setup		= xilinx_pcie_setup,
-		.map_irq	= of_irq_parse_and_map_pci,
-		.scan		= xilinx_pcie_scan_bus,
-		.ops		= &xilinx_pcie_ops,
-	};
+	bus = pci_create_root_bus(&pdev->dev, 0,
+				  &xilinx_pcie_ops, port, &res);
+	if (!bus)
+		return -ENOMEM;
 
 #ifdef CONFIG_PCI_MSI
 	xilinx_pcie_msi_chip.dev = port->dev;
+	bus->msi = &xilinx_pcie_msi_chip;
 #endif
-	pci_common_init_dev(dev, &hw);
+	pci_scan_child_bus(bus);
+	pci_assign_unassigned_bus_resources(bus);
+	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+	pci_bus_add_devices(bus);
+	platform_set_drvdata(pdev, port);
 
 	return 0;
 }
-- 
2.1.1

[PATCH 3/5] PCI: xilinx: Modifying AXI PCIe Host Bridge driver to work on both Zynq and Microblaze

[Bharat Kumar Gogada]

Modifying Xilinx AXI PCIe Host Bridge Soft IP driver to work on both
Zynq and Microblaze Architectures.
With these modifications drivers/pci/host/pcie-xilinx.c, will
work on both Zynq and Microblaze Architectures.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Changed Total number of MSI IRQ count logic according to both architectures.
Updated MSI assigning functions accordingly to new count.
Modified irq_domain_add_linear with new MSI IRQ count.
Added #ifdef to pci_fixup_irqs which are ARM specific API.
---
 drivers/pci/host/pcie-xilinx.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index 3e3757f..05f6f2e 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -93,6 +93,11 @@
 
 /* Number of MSI IRQs */
 #define XILINX_NUM_MSI_IRQS		128
+#ifdef CONFIG_ARM
+#define TOT_NR_IRQS			XILINX_NUM_MSI_IRQS
+#else
+#define TOT_NR_IRQS			(NR_IRQS + XILINX_NUM_MSI_IRQS)
+#endif
 
 
 /**
@@ -238,15 +243,20 @@ static void xilinx_pcie_destroy_msi(unsigned int irq)
  */
 static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
 {
+	int irq;
 	int pos;
 
 	pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
-	if (pos < XILINX_NUM_MSI_IRQS)
+	irq = pos;
+#ifdef CONFIG_MICROBLAZE
+	irq = XILINX_NUM_MSI_IRQS + pos;
+#endif
+	if (irq < TOT_NR_IRQS)
 		set_bit(pos, msi_irq_in_use);
 	else
 		return -ENOSPC;
 
-	return pos;
+	return irq;
 }
 
 /**
@@ -520,7 +530,7 @@ static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
 
 		free_pages(port->msi_pages, 0);
 
-		num_irqs = XILINX_NUM_MSI_IRQS;
+		num_irqs = TOT_NR_IRQS;
 	} else {
 		/* INTx */
 		num_irqs = 4;
@@ -565,7 +575,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
 	/* Setup MSI */
 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
 		port->irq_domain = irq_domain_add_linear(node,
-							 XILINX_NUM_MSI_IRQS,
+							 TOT_NR_IRQS,
 							 &msi_domain_ops,
 							 &xilinx_pcie_msi_chip);
 		if (!port->irq_domain) {
@@ -705,7 +715,9 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
 #endif
 	pci_scan_child_bus(bus);
 	pci_assign_unassigned_bus_resources(bus);
+#ifdef CONFIG_ARM
 	pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
+#endif
 	pci_bus_add_devices(bus);
 	platform_set_drvdata(pdev, port);
 
-- 
2.1.1

[PATCH 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node.

[Bharat Kumar Gogada]

Updated Zynq PCI binding documentation with Microblaze node.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Changes:
Adding Microblaze device tree node Documnetation.
---
 .../devicetree/bindings/pci/xilinx-pcie.txt        | 36 ++++++++++++++++++++--
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
index 02f979a..d207bf4 100644
--- a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
@@ -17,7 +17,10 @@ Required properties:
 	Please refer to the standard PCI bus binding document for a more
 	detailed explanation
 
-Optional properties:
+Optional properties for Zynq:
+- bus-range: PCI bus numbers covered
+
+Required property for Microblaze:
 - bus-range: PCI bus numbers covered
 
 Interrupt controller child node
@@ -38,13 +41,13 @@ the four INTx interrupts in ISR and route them to this domain.
 
 Example:
 ++++++++
-
+Zynq:
 	pci_express: axi-pcie at 50000000 {
 		#address-cells = <3>;
 		#size-cells = <2>;
 		#interrupt-cells = <1>;
 		compatible = "xlnx,axi-pcie-host-1.00.a";
-		reg = < 0x50000000 0x10000000 >;
+		reg = < 0x50000000 0x1000000 >;
 		device_type = "pci";
 		interrupts = < 0 52 4 >;
 		interrupt-map-mask = <0 0 0 7>;
@@ -60,3 +63,30 @@ Example:
 			#interrupt-cells = <1>;
 		};
 	};
+
+
+Microblaze:
+	pci_express: axi-pcie at 10000000 {
+		#address-cells = <3>;
+		#size-cells = <2>;
+		#interrupt-cells = <1>;
+		compatible = "xlnx,axi-pcie-host-1.00.a";
+		reg = <0x10000000 0x4000000>;
+		device_type = "pci";
+		interrupt-parent = <&microbalze_0_intc>;
+		interrupts = <1 2>;
+		interrupt-map-mask = <0 0 0 7>;
+		interrupt-map = <0 0 0 1 &pcie_intc 1>,
+				<0 0 0 2 &pcie_intc 2>,
+				<0 0 0 3 &pcie_intc 3>,
+				<0 0 0 4 &pcie_intc 4>;
+		ranges = <0x02000000 0x00000000 0x80000000 0x80000000 0x00000000 0x10000000>;
+		bus-range = <0x00 0xff>;
+
+		pcie_intc: interrupt-controller {
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+
+	};
-- 
2.1.1

[PATCH 5/5] Microblaze: Modifying microblaze PCI subsytem to support generic Xilinx AXI PCIe Host Bridge IP driver

[Bharat Kumar Gogada]

This patch does required modifications to microblaze PCI subsystem, to
work with generic driver (drivers/pci/host/pcie-xilinx.c) on Microblaze
and Zynq.

Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
---
Modified pcibios_fixup_bus in pci-common.c, as per generic architecuture.
Modified pcibios_align_resource in pci-common.c, as per generic
architecuture.
Modified pcibios_get_phb_of_node function in pci-common.c, to remove
dependency on struct pci_controller.
Removed pci_domain_nr in pci-common.c, instead using generic code.
Added pcibios_add_device in pci-common.c, as per generic architecuture.
Adding Kernel configuration in arch/microblaze as required for generic PCI
domains.
Added kernel configuration for driver to support Microblaze.
---
 arch/microblaze/Kconfig          |  3 ++
 arch/microblaze/pci/pci-common.c | 61 +++++++++++++++-------------------------
 drivers/pci/host/Kconfig         |  2 +-
 3 files changed, 27 insertions(+), 39 deletions(-)

diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 0bce820..c3702b9 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -271,6 +271,9 @@ config PCI
 config PCI_DOMAINS
 	def_bool PCI
 
+config PCI_DOMAINS_GENERIC
+	def_bool PCI_DOMAINS
+
 config PCI_SYSCALL
 	def_bool PCI
 
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index ae838ed..bc72856 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -123,17 +123,6 @@ unsigned long pci_address_to_pio(phys_addr_t address)
 }
 EXPORT_SYMBOL_GPL(pci_address_to_pio);
 
-/*
- * Return the domain number for this bus.
- */
-int pci_domain_nr(struct pci_bus *bus)
-{
-	struct pci_controller *hose = pci_bus_to_host(bus);
-
-	return hose->global_number;
-}
-EXPORT_SYMBOL(pci_domain_nr);
-
 /* This routine is meant to be used early during boot, when the
  * PCI bus numbers have not yet been assigned, and you need to
  * issue PCI config cycles to an OF device.
@@ -863,26 +852,10 @@ void pcibios_setup_bus_devices(struct pci_bus *bus)
 
 void pcibios_fixup_bus(struct pci_bus *bus)
 {
-	/* When called from the generic PCI probe, read PCI<->PCI bridge
-	 * bases. This is -not- called when generating the PCI tree from
-	 * the OF device-tree.
-	 */
-	if (bus->self != NULL)
-		pci_read_bridge_bases(bus);
-
-	/* Now fixup the bus bus */
-	pcibios_setup_bus_self(bus);
-
-	/* Now fixup devices on that bus */
-	pcibios_setup_bus_devices(bus);
+	/* nothing to do */
 }
 EXPORT_SYMBOL(pcibios_fixup_bus);
 
-static int skip_isa_ioresource_align(struct pci_dev *dev)
-{
-	return 0;
-}
-
 /*
  * We need to avoid collisions with `mirrored' VGA ports
  * and other strange ISA hardware, so we always want the
@@ -899,20 +872,20 @@ static int skip_isa_ioresource_align(struct pci_dev *dev)
 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
 				resource_size_t size, resource_size_t align)
 {
-	struct pci_dev *dev = data;
 	resource_size_t start = res->start;
 
-	if (res->flags & IORESOURCE_IO) {
-		if (skip_isa_ioresource_align(dev))
-			return start;
-		if (start & 0x300)
-			start = (start + 0x3ff) & ~0x3ff;
-	}
-
 	return start;
 }
 EXPORT_SYMBOL(pcibios_align_resource);
 
+int pcibios_add_device(struct pci_dev *dev)
+{
+	dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
+
+	return 0;
+}
+EXPORT_SYMBOL(pcibios_add_device);
+
 /*
  * Reparent resource children of pr that conflict with res
  * under res, and make res replace those children.
@@ -1335,9 +1308,21 @@ static void pcibios_setup_phb_resources(struct pci_controller *hose,
 
 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
 {
-	struct pci_controller *hose = bus->sysdata;
+	struct device_node *np;
+
+	for_each_node_by_type(np, "pci") {
+		const void *prop;
+		unsigned int bus_min;
+
+		prop = of_get_property(np, "bus-range", NULL);
+		if (!prop)
+			continue;
+		bus_min = be32_to_cpup(prop);
+		if (bus->number == bus_min)
+			return np;
+	}
 
-	return of_node_get(hose->dn);
+	return NULL;
 }
 
 static void pcibios_scan_phb(struct pci_controller *hose)
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index d5e58ba..7c56c2e 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -79,7 +79,7 @@ config PCI_KEYSTONE
 
 config PCIE_XILINX
 	bool "Xilinx AXI PCIe host bridge support"
-	depends on ARCH_ZYNQ
+	depends on ARCH_ZYNQ || MICROBLAZE
 	help
 	  Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
 	  Host Bridge driver.
-- 
2.1.1

[PATCH 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function

[kbuild test robot]

Hi Bharat,

[auto build test ERROR on pci/next]
[also build test ERROR on v4.4 next-20160111]
[if your patch is applied to the wrong git tree, please drop us a note to help improving the system]

url:    https://github.com/0day-ci/linux/commits/Bharat-Kumar-Gogada/PCI-xilinx-Removing-xilinx_pcie_parse_and_add_res-function/20160112-133224
base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: arm-allyesconfig (attached as .config)
reproduce:
        wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=arm 

Note: the linux-review/Bharat-Kumar-Gogada/PCI-xilinx-Removing-xilinx_pcie_parse_and_add_res-function/20160112-133224 HEAD 8ae5c17c14eb5023b68a0c2bc9fabb3b24eab051 builds fine.
      It only hurts bisectibility.

All errors (new ones prefixed by >>):

>> drivers/pci/host/pcie-xilinx.c:657:25: error: expected '=', ',', ';', 'asm' or '__attribute__' before '-' token
     * xilinx_pcie_parse_dt - Parse Device tree
                            ^
>> drivers/pci/host/pcie-xilinx.c:658:4: error: stray '@' in program
     * @port: PCIe port information
       ^
   drivers/pci/host/pcie-xilinx.c: In function 'xilinx_pcie_probe':
>> drivers/pci/host/pcie-xilinx.c:722:2: error: implicit declaration of function 'xilinx_pcie_parse_dt' [-Werror=implicit-function-declaration]
     err = xilinx_pcie_parse_dt(port);
     ^
   drivers/pci/host/pcie-xilinx.c: At top level:
   drivers/pci/host/pcie-xilinx.c:391:20: warning: 'xilinx_pcie_intr_handler' defined but not used [-Wunused-function]
    static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
                       ^
   cc1: some warnings being treated as errors

vim +657 drivers/pci/host/pcie-xilinx.c

8953aab1 Lorenzo Pieralisi   2015-07-29  651  	else
8953aab1 Lorenzo Pieralisi   2015-07-29  652  		bus = pci_scan_root_bus(port->dev, sys->busnr,
8953aab1 Lorenzo Pieralisi   2015-07-29  653  					&xilinx_pcie_ops, sys, &sys->resources);
8961def5 Srikanth Thokala    2014-08-20  654  	return bus;
8961def5 Srikanth Thokala    2014-08-20  655  }
8961def5 Srikanth Thokala    2014-08-20  656  
8961def5 Srikanth Thokala    2014-08-20 @657   * xilinx_pcie_parse_dt - Parse Device tree
8961def5 Srikanth Thokala    2014-08-20 @658   * @port: PCIe port information
8961def5 Srikanth Thokala    2014-08-20  659   *
8961def5 Srikanth Thokala    2014-08-20  660   * Return: '0' on success and error value on failure
8961def5 Srikanth Thokala    2014-08-20  661   */
8961def5 Srikanth Thokala    2014-08-20  662  static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
8961def5 Srikanth Thokala    2014-08-20  663  {
8961def5 Srikanth Thokala    2014-08-20  664  	struct device *dev = port->dev;
8961def5 Srikanth Thokala    2014-08-20  665  	struct device_node *node = dev->of_node;
8961def5 Srikanth Thokala    2014-08-20  666  	struct resource regs;
8961def5 Srikanth Thokala    2014-08-20  667  	const char *type;
8961def5 Srikanth Thokala    2014-08-20  668  	int err;
8961def5 Srikanth Thokala    2014-08-20  669  
8961def5 Srikanth Thokala    2014-08-20  670  	type = of_get_property(node, "device_type", NULL);
8961def5 Srikanth Thokala    2014-08-20  671  	if (!type || strcmp(type, "pci")) {
8961def5 Srikanth Thokala    2014-08-20  672  		dev_err(dev, "invalid \"device_type\" %s\n", type);
8961def5 Srikanth Thokala    2014-08-20  673  		return -EINVAL;
8961def5 Srikanth Thokala    2014-08-20  674  	}
8961def5 Srikanth Thokala    2014-08-20  675  
8961def5 Srikanth Thokala    2014-08-20  676  	err = of_address_to_resource(node, 0, &regs);
8961def5 Srikanth Thokala    2014-08-20  677  	if (err) {
8961def5 Srikanth Thokala    2014-08-20  678  		dev_err(dev, "missing \"reg\" property\n");
8961def5 Srikanth Thokala    2014-08-20  679  		return err;
8961def5 Srikanth Thokala    2014-08-20  680  	}
8961def5 Srikanth Thokala    2014-08-20  681  
8961def5 Srikanth Thokala    2014-08-20  682  	port->reg_base = devm_ioremap_resource(dev, &regs);
8961def5 Srikanth Thokala    2014-08-20  683  	if (IS_ERR(port->reg_base))
8961def5 Srikanth Thokala    2014-08-20  684  		return PTR_ERR(port->reg_base);
8961def5 Srikanth Thokala    2014-08-20  685  
8961def5 Srikanth Thokala    2014-08-20  686  	port->irq = irq_of_parse_and_map(node, 0);
8961def5 Srikanth Thokala    2014-08-20  687  	err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
9dd875f8 Grygorii Strashko   2015-12-10  688  			       IRQF_SHARED | IRQF_NO_THREAD,
9dd875f8 Grygorii Strashko   2015-12-10  689  			       "xilinx-pcie", port);
8961def5 Srikanth Thokala    2014-08-20  690  	if (err) {
8961def5 Srikanth Thokala    2014-08-20  691  		dev_err(dev, "unable to request irq %d\n", port->irq);
8961def5 Srikanth Thokala    2014-08-20  692  		return err;
8961def5 Srikanth Thokala    2014-08-20  693  	}
8961def5 Srikanth Thokala    2014-08-20  694  
8961def5 Srikanth Thokala    2014-08-20  695  	return 0;
8961def5 Srikanth Thokala    2014-08-20  696  }
8961def5 Srikanth Thokala    2014-08-20  697  
8961def5 Srikanth Thokala    2014-08-20  698  /**
8961def5 Srikanth Thokala    2014-08-20  699   * xilinx_pcie_probe - Probe function
8961def5 Srikanth Thokala    2014-08-20  700   * @pdev: Platform device pointer
8961def5 Srikanth Thokala    2014-08-20  701   *
8961def5 Srikanth Thokala    2014-08-20  702   * Return: '0' on success and error value on failure
8961def5 Srikanth Thokala    2014-08-20  703   */
8961def5 Srikanth Thokala    2014-08-20  704  static int xilinx_pcie_probe(struct platform_device *pdev)
8961def5 Srikanth Thokala    2014-08-20  705  {
8961def5 Srikanth Thokala    2014-08-20  706  	struct xilinx_pcie_port *port;
8961def5 Srikanth Thokala    2014-08-20  707  	struct hw_pci hw;
8961def5 Srikanth Thokala    2014-08-20  708  	struct device *dev = &pdev->dev;
8961def5 Srikanth Thokala    2014-08-20  709  	int err;
aefcb31a Bharat Kumar Gogada 2016-01-12  710  	resource_size_t iobase = 0;
aefcb31a Bharat Kumar Gogada 2016-01-12  711  	LIST_HEAD(res);
8961def5 Srikanth Thokala    2014-08-20  712  
8961def5 Srikanth Thokala    2014-08-20  713  	if (!dev->of_node)
8961def5 Srikanth Thokala    2014-08-20  714  		return -ENODEV;
8961def5 Srikanth Thokala    2014-08-20  715  
8961def5 Srikanth Thokala    2014-08-20  716  	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
8961def5 Srikanth Thokala    2014-08-20  717  	if (!port)
8961def5 Srikanth Thokala    2014-08-20  718  		return -ENOMEM;
8961def5 Srikanth Thokala    2014-08-20  719  
8961def5 Srikanth Thokala    2014-08-20  720  	port->dev = dev;
8961def5 Srikanth Thokala    2014-08-20  721  
8961def5 Srikanth Thokala    2014-08-20 @722  	err = xilinx_pcie_parse_dt(port);
8961def5 Srikanth Thokala    2014-08-20  723  	if (err) {
8961def5 Srikanth Thokala    2014-08-20  724  		dev_err(dev, "Parsing DT failed\n");
8961def5 Srikanth Thokala    2014-08-20  725  		return err;

:::::: The code at line 657 was first introduced by commit
:::::: 8961def56845593f22ce85474e428f6e4892fdd3 PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver

:::::: TO: Srikanth Thokala <sthokal@xilinx.com>
:::::: CC: Bjorn Helgaas <bhelgaas@google.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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[PATCH 1/5] PCI: xilinx: Removing xilinx_pcie_parse_and_add_res function

[Bharat Kumar Gogada]

Will resend the patches.

> Hi Bharat,
> 
> [auto build test ERROR on pci/next]
> [also build test ERROR on v4.4 next-20160111] [if your patch is applied to the
> wrong git tree, please drop us a note to help improving the system]
> 
> url:    https://github.com/0day-ci/linux/commits/Bharat-Kumar-Gogada/PCI-
> xilinx-Removing-xilinx_pcie_parse_and_add_res-function/20160112-133224
> base:   https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
> config: arm-allyesconfig (attached as .config)
> reproduce:
>         wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-
> tests.git/plain/sbin/make.cross -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # save the attached .config to linux build tree
>         make.cross ARCH=arm
> 
> Note: the linux-review/Bharat-Kumar-Gogada/PCI-xilinx-Removing-
> xilinx_pcie_parse_and_add_res-function/20160112-133224 HEAD
> 8ae5c17c14eb5023b68a0c2bc9fabb3b24eab051 builds fine.
>       It only hurts bisectibility.
> 
> All errors (new ones prefixed by >>):
> 
> >> drivers/pci/host/pcie-xilinx.c:657:25: error: expected '=', ',', ';',
> >> 'asm' or '__attribute__' before '-' token
>      * xilinx_pcie_parse_dt - Parse Device tree
>                             ^
> >> drivers/pci/host/pcie-xilinx.c:658:4: error: stray '@' in program
>      * @port: PCIe port information
>        ^
>    drivers/pci/host/pcie-xilinx.c: In function 'xilinx_pcie_probe':
> >> drivers/pci/host/pcie-xilinx.c:722:2: error: implicit declaration of
> >> function 'xilinx_pcie_parse_dt'
> >> [-Werror=implicit-function-declaration]
>      err = xilinx_pcie_parse_dt(port);
>      ^
>    drivers/pci/host/pcie-xilinx.c: At top level:
>    drivers/pci/host/pcie-xilinx.c:391:20: warning: 'xilinx_pcie_intr_handler'
> defined but not used [-Wunused-function]
>     static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
>                        ^
>    cc1: some warnings being treated as errors
> 
> vim +657 drivers/pci/host/pcie-xilinx.c
> 
> 8953aab1 Lorenzo Pieralisi   2015-07-29  651  	else
> 8953aab1 Lorenzo Pieralisi   2015-07-29  652  		bus =
> pci_scan_root_bus(port->dev, sys->busnr,
> 8953aab1 Lorenzo Pieralisi   2015-07-29  653
> 	&xilinx_pcie_ops, sys, &sys->resources);
> 8961def5 Srikanth Thokala    2014-08-20  654  	return bus;
> 8961def5 Srikanth Thokala    2014-08-20  655  }
> 8961def5 Srikanth Thokala    2014-08-20  656
> 8961def5 Srikanth Thokala    2014-08-20 @657   * xilinx_pcie_parse_dt - Parse
> Device tree
> 8961def5 Srikanth Thokala    2014-08-20 @658   * @port: PCIe port
> information
> 8961def5 Srikanth Thokala    2014-08-20  659   *
> 8961def5 Srikanth Thokala    2014-08-20  660   * Return: '0' on success and
> error value on failure
> 8961def5 Srikanth Thokala    2014-08-20  661   */
> 8961def5 Srikanth Thokala    2014-08-20  662  static int
> xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
> 8961def5 Srikanth Thokala    2014-08-20  663  {
> 8961def5 Srikanth Thokala    2014-08-20  664  	struct device *dev = port-
> >dev;
> 8961def5 Srikanth Thokala    2014-08-20  665  	struct device_node *node =
> dev->of_node;
> 8961def5 Srikanth Thokala    2014-08-20  666  	struct resource regs;
> 8961def5 Srikanth Thokala    2014-08-20  667  	const char *type;
> 8961def5 Srikanth Thokala    2014-08-20  668  	int err;
> 8961def5 Srikanth Thokala    2014-08-20  669
> 8961def5 Srikanth Thokala    2014-08-20  670  	type =
> of_get_property(node, "device_type", NULL);
> 8961def5 Srikanth Thokala    2014-08-20  671  	if (!type || strcmp(type,
> "pci")) {
> 8961def5 Srikanth Thokala    2014-08-20  672  		dev_err(dev, "invalid
> \"device_type\" %s\n", type);
> 8961def5 Srikanth Thokala    2014-08-20  673  		return -EINVAL;
> 8961def5 Srikanth Thokala    2014-08-20  674  	}
> 8961def5 Srikanth Thokala    2014-08-20  675
> 8961def5 Srikanth Thokala    2014-08-20  676  	err =
> of_address_to_resource(node, 0, &regs);
> 8961def5 Srikanth Thokala    2014-08-20  677  	if (err) {
> 8961def5 Srikanth Thokala    2014-08-20  678  		dev_err(dev,
> "missing \"reg\" property\n");
> 8961def5 Srikanth Thokala    2014-08-20  679  		return err;
> 8961def5 Srikanth Thokala    2014-08-20  680  	}
> 8961def5 Srikanth Thokala    2014-08-20  681
> 8961def5 Srikanth Thokala    2014-08-20  682  	port->reg_base =
> devm_ioremap_resource(dev, &regs);
> 8961def5 Srikanth Thokala    2014-08-20  683  	if (IS_ERR(port->reg_base))
> 8961def5 Srikanth Thokala    2014-08-20  684  		return PTR_ERR(port-
> >reg_base);
> 8961def5 Srikanth Thokala    2014-08-20  685
> 8961def5 Srikanth Thokala    2014-08-20  686  	port->irq =
> irq_of_parse_and_map(node, 0);
> 8961def5 Srikanth Thokala    2014-08-20  687  	err = devm_request_irq(dev,
> port->irq, xilinx_pcie_intr_handler,
> 9dd875f8 Grygorii Strashko   2015-12-10  688
> IRQF_SHARED | IRQF_NO_THREAD,
> 9dd875f8 Grygorii Strashko   2015-12-10  689  			       "xilinx-
> pcie", port);
> 8961def5 Srikanth Thokala    2014-08-20  690  	if (err) {
> 8961def5 Srikanth Thokala    2014-08-20  691  		dev_err(dev, "unable
> to request irq %d\n", port->irq);
> 8961def5 Srikanth Thokala    2014-08-20  692  		return err;
> 8961def5 Srikanth Thokala    2014-08-20  693  	}
> 8961def5 Srikanth Thokala    2014-08-20  694
> 8961def5 Srikanth Thokala    2014-08-20  695  	return 0;
> 8961def5 Srikanth Thokala    2014-08-20  696  }
> 8961def5 Srikanth Thokala    2014-08-20  697
> 8961def5 Srikanth Thokala    2014-08-20  698  /**
> 8961def5 Srikanth Thokala    2014-08-20  699   * xilinx_pcie_probe - Probe
> function
> 8961def5 Srikanth Thokala    2014-08-20  700   * @pdev: Platform device
> pointer
> 8961def5 Srikanth Thokala    2014-08-20  701   *
> 8961def5 Srikanth Thokala    2014-08-20  702   * Return: '0' on success and
> error value on failure
> 8961def5 Srikanth Thokala    2014-08-20  703   */
> 8961def5 Srikanth Thokala    2014-08-20  704  static int
> xilinx_pcie_probe(struct platform_device *pdev)
> 8961def5 Srikanth Thokala    2014-08-20  705  {
> 8961def5 Srikanth Thokala    2014-08-20  706  	struct xilinx_pcie_port *port;
> 8961def5 Srikanth Thokala    2014-08-20  707  	struct hw_pci hw;
> 8961def5 Srikanth Thokala    2014-08-20  708  	struct device *dev = &pdev-
> >dev;
> 8961def5 Srikanth Thokala    2014-08-20  709  	int err;
> aefcb31a Bharat Kumar Gogada 2016-01-12  710  	resource_size_t
> iobase = 0;
> aefcb31a Bharat Kumar Gogada 2016-01-12  711  	LIST_HEAD(res);
> 8961def5 Srikanth Thokala    2014-08-20  712
> 8961def5 Srikanth Thokala    2014-08-20  713  	if (!dev->of_node)
> 8961def5 Srikanth Thokala    2014-08-20  714  		return -ENODEV;
> 8961def5 Srikanth Thokala    2014-08-20  715
> 8961def5 Srikanth Thokala    2014-08-20  716  	port = devm_kzalloc(dev,
> sizeof(*port), GFP_KERNEL);
> 8961def5 Srikanth Thokala    2014-08-20  717  	if (!port)
> 8961def5 Srikanth Thokala    2014-08-20  718  		return -ENOMEM;
> 8961def5 Srikanth Thokala    2014-08-20  719
> 8961def5 Srikanth Thokala    2014-08-20  720  	port->dev = dev;
> 8961def5 Srikanth Thokala    2014-08-20  721
> 8961def5 Srikanth Thokala    2014-08-20 @722  	err =
> xilinx_pcie_parse_dt(port);
> 8961def5 Srikanth Thokala    2014-08-20  723  	if (err) {
> 8961def5 Srikanth Thokala    2014-08-20  724  		dev_err(dev, "Parsing
> DT failed\n");
> 8961def5 Srikanth Thokala    2014-08-20  725  		return err;
> 
> :::::: The code at line 657 was first introduced by commit
> :::::: 8961def56845593f22ce85474e428f6e4892fdd3 PCI: xilinx: Add Xilinx AXI
> PCIe Host Bridge IP driver
> 
> :::::: TO: Srikanth Thokala <sthokal@xilinx.com>
> :::::: CC: Bjorn Helgaas <bhelgaas@google.com>
> 
> ---
> 0-DAY kernel test infrastructure                Open Source Technology Center
> https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

[PATCH 4/5] PCI: xilinx: Updating Zynq PCI binding documentation with Microblaze node.

[Rob Herring]

On Tue, Jan 12, 2016 at 10:56:38AM +0530, Bharat Kumar Gogada wrote:
> Updated Zynq PCI binding documentation with Microblaze node.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Changes:
> Adding Microblaze device tree node Documnetation.
> ---
>  .../devicetree/bindings/pci/xilinx-pcie.txt        | 36 ++++++++++++++++++++--
>  1 file changed, 33 insertions(+), 3 deletions(-)

Acked-by: Rob Herring <robh@kernel.org>