[PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register

[PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register

[megous]

From: Ondrej Jirman <megous@megous.com>

The current code defines W1 clock gate to be at 0x1cc, overlaying it
with the IR gate.

Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
causing interrupt floods on H6 (because interrupt flags can't be cleared,
due to IR module's bus being disabled).

Signed-off-by: Ondrej Jirman <megous@megous.com>
Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
---
 drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
index 27554eaf6929..8d05d4f1f8a1 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
@@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk,	"r-apb2-i2c",	"r-apb2",
 static SUNXI_CCU_GATE(r_apb1_ir_clk,	"r-apb1-ir",	"r-apb1",
 		      0x1cc, BIT(0), 0);
 static SUNXI_CCU_GATE(r_apb1_w1_clk,	"r-apb1-w1",	"r-apb1",
-		      0x1cc, BIT(0), 0);
+		      0x1ec, BIT(0), 0);
 
 /* Information of IR(RX) mod clock is gathered from BSP source code */
 static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
-- 
2.21.0


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Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register

[Clément Péron]

Hi Ondrej,

On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
<linux-sunxi@googlegroups.com> wrote:
>
> From: Ondrej Jirman <megous@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> index 27554eaf6929..8d05d4f1f8a1 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk,       "r-apb2-i2c",   "r-apb2",
>  static SUNXI_CCU_GATE(r_apb1_ir_clk,   "r-apb1-ir",    "r-apb1",
>                       0x1cc, BIT(0), 0);
>  static SUNXI_CCU_GATE(r_apb1_w1_clk,   "r-apb1-w1",    "r-apb1",
> -                     0x1cc, BIT(0), 0);
> +                     0x1ec, BIT(0), 0);
Just for information where did you find this information?
Using the vendor kernel or user manual?

Thanks,
Clément

>
>  /* Information of IR(RX) mod clock is gathered from BSP source code */
>  static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> --
> 2.21.0
>
> --
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Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register

[Ondřej Jirman]

Hi Clément,

On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> Hi Ondrej,
> 
> On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> <linux-sunxi@googlegroups.com> wrote:
> >
> > From: Ondrej Jirman <megous@megous.com>
> >
> > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > with the IR gate.
> >
> > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > causing interrupt floods on H6 (because interrupt flags can't be cleared,
> > due to IR module's bus being disabled).
> >
> > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> > ---
> >  drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > index 27554eaf6929..8d05d4f1f8a1 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk,       "r-apb2-i2c",   "r-apb2",
> >  static SUNXI_CCU_GATE(r_apb1_ir_clk,   "r-apb1-ir",    "r-apb1",
> >                       0x1cc, BIT(0), 0);
> >  static SUNXI_CCU_GATE(r_apb1_w1_clk,   "r-apb1-w1",    "r-apb1",
> > -                     0x1cc, BIT(0), 0);
> > +                     0x1ec, BIT(0), 0);
> Just for information where did you find this information?
> Using the vendor kernel or user manual?

Informed guess. All gates and resets are in the same register. And
you can see below that reset register for w1 is 0x1ec. (reset register
for ir is 0x1cc)

regards,
	o.

> Thanks,
> Clément
> 
> >
> >  /* Information of IR(RX) mod clock is gathered from BSP source code */
> >  static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > --
> > 2.21.0
> >
> > --
> > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> > For more options, visit https://groups.google.com/d/optout.

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Re: [linux-sunxi] [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register

[Clément Péron]

Hi Ondrej,

On Tue, 4 Jun 2019 at 18:21, Ondřej Jirman <megous@megous.com> wrote:
>
> Hi Clément,
>
> On Tue, Jun 04, 2019 at 06:14:15PM +0200, Clément Péron wrote:
> > Hi Ondrej,
> >
> > On Tue, 4 Jun 2019 at 17:40, megous via linux-sunxi
> > <linux-sunxi@googlegroups.com> wrote:
> > >
> > > From: Ondrej Jirman <megous@megous.com>
> > >
> > > The current code defines W1 clock gate to be at 0x1cc, overlaying it
> > > with the IR gate.
> > >
> > > Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> > > causing interrupt floods on H6 (because interrupt flags can't be cleared,
> > > due to IR module's bus being disabled).
> > >
> > > Signed-off-by: Ondrej Jirman <megous@megous.com>
> > > Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")
> > > ---
> > >  drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > index 27554eaf6929..8d05d4f1f8a1 100644
> > > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > > @@ -104,7 +104,7 @@ static SUNXI_CCU_GATE(r_apb2_i2c_clk,       "r-apb2-i2c",   "r-apb2",
> > >  static SUNXI_CCU_GATE(r_apb1_ir_clk,   "r-apb1-ir",    "r-apb1",
> > >                       0x1cc, BIT(0), 0);
> > >  static SUNXI_CCU_GATE(r_apb1_w1_clk,   "r-apb1-w1",    "r-apb1",
> > > -                     0x1cc, BIT(0), 0);
> > > +                     0x1ec, BIT(0), 0);
> > Just for information where did you find this information?
> > Using the vendor kernel or user manual?
>
> Informed guess. All gates and resets are in the same register. And
> you can see below that reset register for w1 is 0x1ec. (reset register
> for ir is 0x1cc)
Ok, I thinks this can confirm the value:
https://github.com/orangepi-xunlong/OrangePiH6_Linux4_9/blob/master/drivers/clk/sunxi/clk-sun50iw6.h#L161

Acked-by: Clément Péron <peron.clem@gmail.com>

Regards,
Clément
>
> regards,
>         o.
>
> > Thanks,
> > Clément
> >
> > >
> > >  /* Information of IR(RX) mod clock is gathered from BSP source code */
> > >  static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
> > > --
> > > 2.21.0
> > >
> > > --
> > > You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> > > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com.
> > > To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20190604154036.23211-1-megous%40megous.com.
> > > For more options, visit https://groups.google.com/d/optout.

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Re: [PATCH v2] clk: sunxi-ng: sun50i-h6-r: Fix incorrect W1 clock gate register

[Maxime Ripard]

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On Tue, Jun 04, 2019 at 05:40:36PM +0200, megous@megous.com wrote:
> From: Ondrej Jirman <megous@megous.com>
>
> The current code defines W1 clock gate to be at 0x1cc, overlaying it
> with the IR gate.
>
> Clock gate for r-apb1-w1 is at 0x1ec. This fixes issues with IR receiver
> causing interrupt floods on H6 (because interrupt flags can't be cleared,
> due to IR module's bus being disabled).
>
> Signed-off-by: Ondrej Jirman <megous@megous.com>
> Fixes: b7c7b05065aa77ae ("clk: sunxi-ng: add support for H6 PRCM CCU")

Applied, thanks

Maxime

--
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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