From: Reiji Watanabe <reijiw@google.com>
To: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Will Deacon <will@kernel.org>, Andrew Jones <drjones@redhat.com>,
Peng Liang <liangpeng10@huawei.com>,
Peter Shier <pshier@google.com>,
Ricardo Koller <ricarkol@google.com>,
Oliver Upton <oupton@google.com>,
Jing Zhang <jingzhangos@google.com>,
Raghavendra Rao Anata <rananta@google.com>,
Reiji Watanabe <reijiw@google.com>
Subject: [RFC PATCH 14/25] KVM: arm64: Add consistency checking for frac fields of ID registers
Date: Mon, 11 Oct 2021 21:35:24 -0700 [thread overview]
Message-ID: <20211012043535.500493-15-reijiw@google.com> (raw)
In-Reply-To: <20211012043535.500493-1-reijiw@google.com>
Feature fractional field of an ID register cannot be simply validated
at KVM_SET_ONE_REG because its validity depends on its (main) feature
field value, which could be in a different ID register (and might be
set later).
Validate fractional fields at the first KVM_RUN instead.
Signed-off-by: Reiji Watanabe <reijiw@google.com>
---
arch/arm64/kvm/sys_regs.c | 98 +++++++++++++++++++++++++++++++++++++--
1 file changed, 94 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2c092136cdff..536e313992d4 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -632,9 +632,6 @@ static struct id_reg_info id_aa64pfr0_el1_info = {
static struct id_reg_info id_aa64pfr1_el1_info = {
.sys_reg = SYS_ID_AA64PFR1_EL1,
- .ignore_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_RASFRAC) |
- ARM64_FEATURE_MASK(ID_AA64PFR1_MPAMFRAC) |
- ARM64_FEATURE_MASK(ID_AA64PFR1_CSV2FRAC),
.init = init_id_aa64pfr1_el1_info,
.validate = validate_id_aa64pfr1_el1,
.get_reset_val = get_reset_id_aa64pfr1_el1,
@@ -3198,10 +3195,79 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
return write_demux_regids(uindices);
}
+/* ID register's fractional field information with its feature field. */
+struct feature_frac {
+ u32 frac_id;
+ u32 id;
+ u64 frac_mask;
+ u64 mask;
+};
+
+static const struct feature_frac feature_frac_table[] = {
+ {
+ .frac_id = SYS_ID_AA64PFR1_EL1,
+ .frac_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_RASFRAC),
+ .id = SYS_ID_AA64PFR0_EL1,
+ .mask = ARM64_FEATURE_MASK(ID_AA64PFR0_RAS),
+ },
+ {
+ .frac_id = SYS_ID_AA64PFR1_EL1,
+ .frac_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_MPAMFRAC),
+ .id = SYS_ID_AA64PFR0_EL1,
+ .mask = ARM64_FEATURE_MASK(ID_AA64PFR0_MPAM),
+ },
+ {
+ .frac_id = SYS_ID_AA64PFR1_EL1,
+ .frac_mask = ARM64_FEATURE_MASK(ID_AA64PFR1_CSV2FRAC),
+ .id = SYS_ID_AA64PFR0_EL1,
+ .mask = ARM64_FEATURE_MASK(ID_AA64PFR0_CSV2),
+ },
+};
+
+/*
+ * Return non-zero if the feature/fractional fields pair are not
+ * supported. Return zero otherwise.
+ */
+static int vcpu_id_reg_feature_frac_check(const struct kvm_vcpu *vcpu,
+ const struct feature_frac *ftr_frac)
+{
+ const struct id_reg_info *id_reg;
+ u32 id;
+ u64 val, lim;
+ int err;
+
+ /* Check the feature field */
+ id = ftr_frac->id;
+ val = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id)) & ftr_frac->mask;
+ id_reg = GET_ID_REG_INFO(id);
+ lim = id_reg ? id_reg->vcpu_limit_val : read_sanitised_ftr_reg(id);
+ lim &= ftr_frac->mask;
+ err = arm64_check_features(id, val, lim);
+ if (err)
+ /* The feature version is larger than the limit. */
+ return err;
+
+ if (val != lim)
+ /*
+ * The feature version is smaller than the limit.
+ * Any fractional version should be fine.
+ */
+ return 0;
+
+ /* Check the fractional field */
+ id = ftr_frac->frac_id;
+ val = __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id)) & ftr_frac->frac_mask;
+ id_reg = GET_ID_REG_INFO(id);
+ lim = id_reg ? id_reg->vcpu_limit_val : read_sanitised_ftr_reg(id);
+ lim &= ftr_frac->frac_mask;
+ return arm64_check_features(id, val, lim);
+}
+
int kvm_id_regs_consistency_check(const struct kvm_vcpu *vcpu)
{
- int i;
+ int i, err;
const struct kvm_vcpu *t_vcpu;
+ const struct feature_frac *frac;
/*
* Make sure vcpu->arch.has_run_once is visible for others so that
@@ -3222,6 +3288,17 @@ int kvm_id_regs_consistency_check(const struct kvm_vcpu *vcpu)
KVM_ARM_ID_REG_MAX_NUM))
return -EINVAL;
}
+
+ /*
+ * Check ID registers' fractional fields, which aren't checked
+ * when userspace sets.
+ */
+ for (i = 0; i < ARRAY_SIZE(feature_frac_table); i++) {
+ frac = &feature_frac_table[i];
+ err = vcpu_id_reg_feature_frac_check(vcpu, frac);
+ if (err)
+ return err;
+ }
return 0;
}
@@ -3240,6 +3317,19 @@ static void id_reg_info_init_all(void)
else
id_reg_info_init(id_reg);
}
+
+ /*
+ * Update ignore_mask of ID registers based on fractional fields
+ * information. Any ID register that have fractional fields
+ * is expected to have its own id_reg_info.
+ */
+ for (i = 0; i < ARRAY_SIZE(feature_frac_table); i++) {
+ id_reg = GET_ID_REG_INFO(feature_frac_table[i].frac_id);
+ if (WARN_ON_ONCE(!id_reg))
+ continue;
+
+ id_reg->ignore_mask |= feature_frac_table[i].frac_mask;
+ }
}
void kvm_sys_reg_table_init(void)
--
2.33.0.882.g93a45727a2-goog
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next prev parent reply other threads:[~2021-10-12 4:45 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-12 4:35 [RFC PATCH 00/25] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 01/25] KVM: arm64: Add has_reset_once flag for vcpu Reiji Watanabe
2021-10-15 10:12 ` Andrew Jones
2021-10-16 19:54 ` Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 02/25] KVM: arm64: Save ID registers' sanitized value per vCPU Reiji Watanabe
2021-10-15 13:09 ` Andrew Jones
2021-10-17 0:42 ` Reiji Watanabe
2021-10-18 14:30 ` Andrew Jones
2021-10-18 23:54 ` Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 03/25] KVM: arm64: Introduce a validation function for an ID register Reiji Watanabe
2021-10-15 13:30 ` Andrew Jones
[not found] ` <CAAeT=Fy-enk=X_PaRSDEKQ01yQzdyU=bcpq8cuCZhtpzC=JvnQ@mail.gmail.com>
[not found] ` <20211018144215.fvz7lrqiqlwhadms@gator.home>
[not found] ` <CAAeT=FyvRg7cD9-N81BM4gz0FaZHcaoWWQptniB5zDKdL=OkXg@mail.gmail.com>
[not found] ` <20211019062516.smjbbil5ugbipwno@gator.home>
2021-10-19 7:26 ` Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 04/25] KVM: arm64: Introduce struct id_reg_info Reiji Watanabe
2021-10-15 13:47 ` Andrew Jones
2021-10-17 4:43 ` Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 05/25] KVM: arm64: Keep consistency of ID registers between vCPUs Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 06/25] KVM: arm64: Make ID_AA64PFR0_EL1 writable Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 07/25] KVM: arm64: Make ID_AA64PFR1_EL1 writable Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 08/25] KVM: arm64: Make ID_AA64ISAR0_EL1 writable Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 09/25] KVM: arm64: Make ID_AA64ISAR1_EL1 writable Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 10/25] KVM: arm64: Make ID_AA64DFR0_EL1 writable Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 11/25] KVM: arm64: Make ID_DFR0_EL1 writable Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 12/25] KVM: arm64: Make MVFR1_EL1 writable Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 13/25] KVM: arm64: Make ID registers without id_reg_info writable Reiji Watanabe
2021-10-12 4:35 ` Reiji Watanabe [this message]
2021-10-12 4:35 ` [RFC PATCH 15/25] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_WRITABLE capability Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 16/25] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 17/25] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 18/25] KVM: arm64: Introduce framework to trap disabled features Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 19/25] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 20/25] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 21/25] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1 Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 22/25] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 23/25] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 24/25] KVM: arm64: Activate trapping of disabled CPU features for the guest Reiji Watanabe
2021-10-12 4:35 ` [RFC PATCH 25/25] KVM: arm64: selftests: Introduce id_reg_test Reiji Watanabe
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