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From: Reiji Watanabe <reijiw@google.com>
To: Marc Zyngier <maz@kernel.org>, kvmarm@lists.cs.columbia.edu
Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	 James Morse <james.morse@arm.com>,
	Alexandru Elisei <alexandru.elisei@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Will Deacon <will@kernel.org>, Andrew Jones <drjones@redhat.com>,
	 Peng Liang <liangpeng10@huawei.com>,
	Peter Shier <pshier@google.com>,
	 Ricardo Koller <ricarkol@google.com>,
	Oliver Upton <oupton@google.com>,
	 Jing Zhang <jingzhangos@google.com>,
	Raghavendra Rao Anata <rananta@google.com>,
	Reiji Watanabe <reijiw@google.com>
Subject: [RFC PATCH 05/25] KVM: arm64: Keep consistency of ID registers between vCPUs
Date: Mon, 11 Oct 2021 21:35:15 -0700	[thread overview]
Message-ID: <20211012043535.500493-6-reijiw@google.com> (raw)
In-Reply-To: <20211012043535.500493-1-reijiw@google.com>

All vCPUs that are owned by a VM must have the same values of ID
registers.

Return an error at the very first KVM_RUN for a vCPU if the vCPU has
different values in any ID registers from any other vCPUs that have
already started KVM_RUN once.  Also, return an error if userspace
tries to change a value of ID register for a vCPU that already
started KVM_RUN once.

Changing ID register is still not allowed at present though.

Signed-off-by: Reiji Watanabe <reijiw@google.com>
---
 arch/arm64/include/asm/kvm_host.h |  2 ++
 arch/arm64/kvm/arm.c              |  3 +++
 arch/arm64/kvm/sys_regs.c         | 31 +++++++++++++++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 0cd351099adf..69af669308b0 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -745,6 +745,8 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
 long kvm_vm_ioctl_mte_copy_tags(struct kvm *kvm,
 				struct kvm_arm_copy_mte_tags *copy_tags);
 
+int kvm_id_regs_consistency_check(const struct kvm_vcpu *vcpu);
+
 /* Guest/host FPSIMD coordination helpers */
 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index fe102cd2e518..45ca72a37872 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -620,6 +620,9 @@ static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
 
 	ret = kvm_arm_pmu_v3_enable(vcpu);
 
+	if (kvm_id_regs_consistency_check(vcpu))
+		return -EPERM;
+
 	return ret;
 }
 
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 8a0b88f9a975..2fe3121d50ca 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1331,6 +1331,10 @@ static int __set_id_reg(struct kvm_vcpu *vcpu,
 	if (val != read_id_reg(vcpu, rd, raz) && !GET_ID_REG_INFO(encoding))
 		return -EINVAL;
 
+	/* Don't allow to change the reg after the first KVM_RUN. */
+	if (vcpu->arch.has_run_once)
+		return -EINVAL;
+
 	if (raz)
 		return (val == 0) ? 0 : -EINVAL;
 
@@ -2901,6 +2905,33 @@ int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
 	return write_demux_regids(uindices);
 }
 
+int kvm_id_regs_consistency_check(const struct kvm_vcpu *vcpu)
+{
+	int i;
+	const struct kvm_vcpu *t_vcpu;
+
+	/*
+	 * Make sure vcpu->arch.has_run_once is visible for others so that
+	 * ID regs' consistency between two vCPUs is checked by either one
+	 * at least.
+	 */
+	smp_mb();
+	WARN_ON(!vcpu->arch.has_run_once);
+
+	kvm_for_each_vcpu(i, t_vcpu, vcpu->kvm) {
+		if (!t_vcpu->arch.has_run_once)
+			/* ID regs still could be updated. */
+			continue;
+
+		if (memcmp(&__vcpu_sys_reg(vcpu, ID_REG_BASE),
+			   &__vcpu_sys_reg(t_vcpu, ID_REG_BASE),
+			   sizeof(__vcpu_sys_reg(vcpu, ID_REG_BASE)) *
+					KVM_ARM_ID_REG_MAX_NUM))
+			return -EINVAL;
+	}
+	return 0;
+}
+
 static void id_reg_info_init_all(void)
 {
 	int i;
-- 
2.33.0.882.g93a45727a2-goog


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  parent reply	other threads:[~2021-10-12  4:38 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-12  4:35 [RFC PATCH 00/25] KVM: arm64: Make CPU ID registers writable by userspace Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 01/25] KVM: arm64: Add has_reset_once flag for vcpu Reiji Watanabe
2021-10-15 10:12   ` Andrew Jones
2021-10-16 19:54     ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 02/25] KVM: arm64: Save ID registers' sanitized value per vCPU Reiji Watanabe
2021-10-15 13:09   ` Andrew Jones
2021-10-17  0:42     ` Reiji Watanabe
2021-10-18 14:30       ` Andrew Jones
2021-10-18 23:54         ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 03/25] KVM: arm64: Introduce a validation function for an ID register Reiji Watanabe
2021-10-15 13:30   ` Andrew Jones
     [not found]     ` <CAAeT=Fy-enk=X_PaRSDEKQ01yQzdyU=bcpq8cuCZhtpzC=JvnQ@mail.gmail.com>
     [not found]       ` <20211018144215.fvz7lrqiqlwhadms@gator.home>
     [not found]         ` <CAAeT=FyvRg7cD9-N81BM4gz0FaZHcaoWWQptniB5zDKdL=OkXg@mail.gmail.com>
     [not found]           ` <20211019062516.smjbbil5ugbipwno@gator.home>
2021-10-19  7:26             ` Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 04/25] KVM: arm64: Introduce struct id_reg_info Reiji Watanabe
2021-10-15 13:47   ` Andrew Jones
2021-10-17  4:43     ` Reiji Watanabe
2021-10-12  4:35 ` Reiji Watanabe [this message]
2021-10-12  4:35 ` [RFC PATCH 06/25] KVM: arm64: Make ID_AA64PFR0_EL1 writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 07/25] KVM: arm64: Make ID_AA64PFR1_EL1 writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 08/25] KVM: arm64: Make ID_AA64ISAR0_EL1 writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 09/25] KVM: arm64: Make ID_AA64ISAR1_EL1 writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 10/25] KVM: arm64: Make ID_AA64DFR0_EL1 writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 11/25] KVM: arm64: Make ID_DFR0_EL1 writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 12/25] KVM: arm64: Make MVFR1_EL1 writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 13/25] KVM: arm64: Make ID registers without id_reg_info writable Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 14/25] KVM: arm64: Add consistency checking for frac fields of ID registers Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 15/25] KVM: arm64: Introduce KVM_CAP_ARM_ID_REG_WRITABLE capability Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 16/25] KVM: arm64: Use vcpu->arch cptr_el2 to track value of cptr_el2 for VHE Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 17/25] KVM: arm64: Use vcpu->arch.mdcr_el2 to track value of mdcr_el2 Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 18/25] KVM: arm64: Introduce framework to trap disabled features Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 19/25] KVM: arm64: Trap disabled features of ID_AA64PFR0_EL1 Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 20/25] KVM: arm64: Trap disabled features of ID_AA64PFR1_EL1 Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 21/25] KVM: arm64: Trap disabled features of ID_AA64DFR0_EL1 Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 22/25] KVM: arm64: Trap disabled features of ID_AA64MMFR1_EL1 Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 23/25] KVM: arm64: Trap disabled features of ID_AA64ISAR1_EL1 Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 24/25] KVM: arm64: Activate trapping of disabled CPU features for the guest Reiji Watanabe
2021-10-12  4:35 ` [RFC PATCH 25/25] KVM: arm64: selftests: Introduce id_reg_test Reiji Watanabe

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