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From: Will Deacon <will@kernel.org>
To: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, boqun.feng@gmail.com,
	catalin.marinas@arm.com, peterz@infradead.org
Subject: Re: [PATCH 3/5] arm64: atomics: lse: define ANDs in terms of ANDNOTs
Date: Mon, 13 Dec 2021 19:29:36 +0000	[thread overview]
Message-ID: <20211213192935.GC12868@willie-the-truck> (raw)
In-Reply-To: <20211210151410.2782645-4-mark.rutland@arm.com>

On Fri, Dec 10, 2021 at 03:14:08PM +0000, Mark Rutland wrote:
> The FEAT_LSE atomic instructions include atomic bit-clear instructions
> (`ldclr*` and `stclr*`) which can be used to directly implement ANDNOT
> operations. Each AND op is implemented as a copy of the corresponding
> ANDNOT op with a leading `mvn` instruction to apply a bitwise NOT to the
> `i` argument.
> 
> As the compiler has no visibility of the `mvn`, this leads to less than
> optimal code generation when generating `i` into a register. For
> example, __lse_atomic_fetch_and(0xf, v) can be compiled to:
> 
> 	mov     w1, #0xf
> 	mvn     w1, w1
> 	ldclral w1, w1, [x2]
> 
> This patch improves this by replacing the `mvn` with NOT in C before the
> inline assembly block, e.g.
> 
> 	i = ~i;
> 
> This allows the compiler to generate `i` into a register more optimally,
> e.g.
> 
> 	mov     w1, #0xfffffff0
> 	ldclral w1, w1, [x2]
> 
> With this change the assembly for each AND op is identical to the
> corresponding ANDNOT op (including barriers and clobbers), so I've
> removed the inline assembly and rewritten each AND op in terms of the
> corresponding ANDNOT op, e.g.
> 
> | static inline void __lse_atomic_and(int i, atomic_t *v)
> | {
> | 	return __lse_atomic_andnot(~i, v);
> | }
> 
> This is intended as an optimization and cleanup.
> There should be no functional change as a result of this patch.
> 
> Signed-off-by: Mark Rutland <mark.rutland@arm.com>
> Cc: Boqun Feng <boqun.feng@gmail.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Peter Zijlstra <peterz@infradead.org>
> Cc: Will Deacon <will@kernel.org>
> ---
>  arch/arm64/include/asm/atomic_lse.h | 34 ++++-------------------------
>  1 file changed, 4 insertions(+), 30 deletions(-)

Acked-by: Will Deacon <will@kernel.org>

Will

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  reply	other threads:[~2021-12-13 19:30 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-10 15:14 [PATCH 0/5] arm64: atomics: cleanups and codegen improvements Mark Rutland
2021-12-10 15:14 ` [PATCH 1/5] arm64: atomics: format whitespace consistently Mark Rutland
2021-12-13 19:20   ` Will Deacon
2021-12-10 15:14 ` [PATCH 2/5] arm64: atomics lse: define SUBs in terms of ADDs Mark Rutland
2021-12-13 19:27   ` Will Deacon
2021-12-10 15:14 ` [PATCH 3/5] arm64: atomics: lse: define ANDs in terms of ANDNOTs Mark Rutland
2021-12-13 19:29   ` Will Deacon [this message]
2021-12-10 15:14 ` [PATCH 4/5] arm64: atomics: lse: improve constraints for simple ops Mark Rutland
2021-12-13 19:40   ` Will Deacon
2021-12-14 13:04     ` Mark Rutland
2021-12-10 15:14 ` [PATCH 5/5] arm64: atomics: lse: define RETURN ops in terms of FETCH ops Mark Rutland
2021-12-10 22:19   ` Peter Zijlstra
2021-12-13 16:49     ` Mark Rutland
2021-12-13 19:43   ` Will Deacon
2021-12-10 22:26 ` [PATCH 0/5] arm64: atomics: cleanups and codegen improvements Peter Zijlstra
2021-12-14 16:54 ` Catalin Marinas

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