[PATCH v2 0/5] arm64: mte: add core dump support

[PATCH v2 0/5] arm64: mte: add core dump support

[Catalin Marinas]

Hi,

This is the second version of the core dump support for MTE tags.
Changes since v1
(https://lore.kernel.org/r/20211208121941.494956-1-catalin.marinas@arm.com):

- Made the documentation slightly clearer on what the size of a segment.
- Added Luis' acks.
- Rebased to 5.17-rc2.

The arm64 Memory Tagging Extensions allow assigning a 4-bit (allocation)
tag to a 16-byte memory range. Bits 56..59 of a pointer are checked
against the allocation tag on access and a fault may be raised if
there's a mismatch. The additional 4-bit metadata is useful for
debugging hence this series to dump it to the core file.

When a core file is generated and the user has mappings with PROT_MTE,
segments with the PT_ARM_MEMTAG_MTE type are dumped. These correspond to
the PT_LOAD segments for the same virtual addresses. The choice of an
ELF segment rather than a note was made due to the 32-bit size
limitation of a note which would only cover vmas up to 37-bit.

The last patch documents the core file format. The tags are dumped
packed, two 4-bit tags per byte (unlike ptrace where we have one tag per
byte) and there is no header to define the format, it's all fixed for
the PT_ARM_MEMTAG_MTE type.

Below you can see the output of 'readelf -a core' for a program mapping
two regions with PROT_MTE, one 2-page and the other 4-page long. Half of
the first page in each range was filled with 0xa and 0xb tags
respectively.

Program Headers:
  Type           Offset   VirtAddr           PhysAddr           FileSiz  MemSiz   Flg Align
  ...
  LOAD           0x030000 0x0000ffff80034000 0x0000000000000000 0x000000 0x002000 RW  0x1000
  LOAD           0x030000 0x0000ffff80036000 0x0000000000000000 0x004000 0x004000 RW  0x1000
  ...
  LOPROC+0x1     0x05b000 0x0000ffff80034000 0x0000000000000000 0x000100 0x002000     0
  LOPROC+0x1     0x05b100 0x0000ffff80036000 0x0000000000000000 0x000200 0x004000     0

The relevant 'od -tx1 core' output:

05b000 bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb
*
05b040 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
05b100 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa
*
05b140 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
*
05b300

Catalin Marinas (5):
  elfcore: Replace CONFIG_{IA64,UML} checks with a new option
  elf: Introduce the ARM MTE ELF segment type
  arm64: mte: Define the number of bytes for storing the tags in a page
  arm64: mte: Dump the MTE tags in the core file
  arm64: mte: Document the core dump file format

 .../arm64/memory-tagging-extension.rst        |  23 ++++
 arch/arm64/Kconfig                            |   1 +
 arch/arm64/include/asm/mte-def.h              |   1 +
 arch/arm64/kernel/Makefile                    |   1 +
 arch/arm64/kernel/elfcore.c                   | 123 ++++++++++++++++++
 arch/arm64/lib/mte.S                          |   4 +-
 arch/arm64/mm/mteswap.c                       |   2 +-
 arch/ia64/Kconfig                             |   1 +
 arch/x86/um/Kconfig                           |   1 +
 fs/Kconfig.binfmt                             |   3 +
 include/linux/elfcore.h                       |   4 +-
 include/uapi/linux/elf.h                      |   3 +
 12 files changed, 162 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm64/kernel/elfcore.c


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[PATCH v2 1/5] elfcore: Replace CONFIG_{IA64, UML} checks with a new option

[Catalin Marinas]

As arm64 is about to introduce MTE-specific phdrs in the core dump, add
a common CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS option currently selectable
by UML_X86 and IA64.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Eric Biederman <ebiederm@xmission.com>
---
 arch/ia64/Kconfig       | 1 +
 arch/x86/um/Kconfig     | 1 +
 fs/Kconfig.binfmt       | 3 +++
 include/linux/elfcore.h | 4 ++--
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index a7e01573abd8..e003b2473c64 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -8,6 +8,7 @@ menu "Processor type and features"
 
 config IA64
 	bool
+	select ARCH_BINFMT_ELF_EXTRA_PHDRS
 	select ARCH_HAS_DMA_MARK_CLEAN
 	select ARCH_HAS_STRNCPY_FROM_USER
 	select ARCH_HAS_STRNLEN_USER
diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig
index 40d6a06e41c8..ead7e5b3a975 100644
--- a/arch/x86/um/Kconfig
+++ b/arch/x86/um/Kconfig
@@ -8,6 +8,7 @@ endmenu
 
 config UML_X86
 	def_bool y
+	select ARCH_BINFMT_ELF_EXTRA_PHDRS if X86_32
 
 config 64BIT
 	bool "64-bit kernel" if "$(SUBARCH)" = "x86"
diff --git a/fs/Kconfig.binfmt b/fs/Kconfig.binfmt
index 4d5ae61580aa..68e586283764 100644
--- a/fs/Kconfig.binfmt
+++ b/fs/Kconfig.binfmt
@@ -36,6 +36,9 @@ config COMPAT_BINFMT_ELF
 config ARCH_BINFMT_ELF_STATE
 	bool
 
+config ARCH_BINFMT_ELF_EXTRA_PHDRS
+	bool
+
 config ARCH_HAVE_ELF_PROT
 	bool
 
diff --git a/include/linux/elfcore.h b/include/linux/elfcore.h
index 746e081879a5..b02d5fc711db 100644
--- a/include/linux/elfcore.h
+++ b/include/linux/elfcore.h
@@ -114,7 +114,7 @@ static inline int elf_core_copy_task_fpregs(struct task_struct *t, struct pt_reg
 #endif
 }
 
-#if (defined(CONFIG_UML) && defined(CONFIG_X86_32)) || defined(CONFIG_IA64)
+#ifdef CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS
 /*
  * These functions parameterize elf_core_dump in fs/binfmt_elf.c to write out
  * extra segments containing the gate DSO contents.  Dumping its
@@ -149,6 +149,6 @@ static inline size_t elf_core_extra_data_size(void)
 {
 	return 0;
 }
-#endif
+#endif /* CONFIG_ARCH_EXTRA_PHDRS */
 
 #endif /* _LINUX_ELFCORE_H */

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Re: [PATCH v2 1/5] elfcore: Replace CONFIG_{IA64,UML} checks with a new option

[Will Deacon]

On Mon, Jan 31, 2022 at 04:54:52PM +0000, Catalin Marinas wrote:
> As arm64 is about to introduce MTE-specific phdrs in the core dump, add
> a common CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS option currently selectable
> by UML_X86 and IA64.
> 
> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Eric Biederman <ebiederm@xmission.com>
> ---
>  arch/ia64/Kconfig       | 1 +
>  arch/x86/um/Kconfig     | 1 +
>  fs/Kconfig.binfmt       | 3 +++
>  include/linux/elfcore.h | 4 ++--
>  4 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
> index a7e01573abd8..e003b2473c64 100644
> --- a/arch/ia64/Kconfig
> +++ b/arch/ia64/Kconfig
> @@ -8,6 +8,7 @@ menu "Processor type and features"
>  
>  config IA64
>  	bool
> +	select ARCH_BINFMT_ELF_EXTRA_PHDRS
>  	select ARCH_HAS_DMA_MARK_CLEAN
>  	select ARCH_HAS_STRNCPY_FROM_USER
>  	select ARCH_HAS_STRNLEN_USER
> diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig
> index 40d6a06e41c8..ead7e5b3a975 100644
> --- a/arch/x86/um/Kconfig
> +++ b/arch/x86/um/Kconfig
> @@ -8,6 +8,7 @@ endmenu
>  
>  config UML_X86
>  	def_bool y
> +	select ARCH_BINFMT_ELF_EXTRA_PHDRS if X86_32
>  
>  config 64BIT
>  	bool "64-bit kernel" if "$(SUBARCH)" = "x86"
> diff --git a/fs/Kconfig.binfmt b/fs/Kconfig.binfmt
> index 4d5ae61580aa..68e586283764 100644
> --- a/fs/Kconfig.binfmt
> +++ b/fs/Kconfig.binfmt
> @@ -36,6 +36,9 @@ config COMPAT_BINFMT_ELF
>  config ARCH_BINFMT_ELF_STATE
>  	bool
>  
> +config ARCH_BINFMT_ELF_EXTRA_PHDRS
> +	bool
> +
>  config ARCH_HAVE_ELF_PROT
>  	bool
>  
> diff --git a/include/linux/elfcore.h b/include/linux/elfcore.h
> index 746e081879a5..b02d5fc711db 100644
> --- a/include/linux/elfcore.h
> +++ b/include/linux/elfcore.h
> @@ -114,7 +114,7 @@ static inline int elf_core_copy_task_fpregs(struct task_struct *t, struct pt_reg
>  #endif
>  }
>  
> -#if (defined(CONFIG_UML) && defined(CONFIG_X86_32)) || defined(CONFIG_IA64)
> +#ifdef CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS
>  /*
>   * These functions parameterize elf_core_dump in fs/binfmt_elf.c to write out
>   * extra segments containing the gate DSO contents.  Dumping its
> @@ -149,6 +149,6 @@ static inline size_t elf_core_extra_data_size(void)
>  {
>  	return 0;
>  }
> -#endif
> +#endif /* CONFIG_ARCH_EXTRA_PHDRS */

nit: closing comment doesn't match the name of the new Kconfig symbol.

I'll fix that and put the series into -next.

Will

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[PATCH v2 2/5] elf: Introduce the ARM MTE ELF segment type

[Catalin Marinas]

Memory tags will be dumped in the core file as segments with their own
type. Discussions with the binutils and the generic ABI community
settled on using new definitions in the PT_*PROC space (and to be
documented in the processor-specific ABIs).

Introduce PT_ARM_MEMTAG_MTE as (PT_LOPROC + 0x1). Not included in this
patch since there is no upstream support but the CHERI/BSD community
will also reserve:

  #define PT_ARM_MEMTAG_CHERI    (PT_LOPROC + 0x2)
  #define PT_RISCV_MEMTAG_CHERI  (PT_LOPROC + 0x3)

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
---
 include/uapi/linux/elf.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/uapi/linux/elf.h b/include/uapi/linux/elf.h
index 61bf4774b8f2..fe8e5b74cb39 100644
--- a/include/uapi/linux/elf.h
+++ b/include/uapi/linux/elf.h
@@ -40,6 +40,9 @@ typedef __s64	Elf64_Sxword;
 
 #define PT_GNU_STACK	(PT_LOOS + 0x474e551)
 
+/* ARM MTE memory tag segment type */
+#define PT_ARM_MEMTAG_MTE	(PT_LOPROC + 0x1)
+
 /*
  * Extended Numbering
  *

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[PATCH v2 3/5] arm64: mte: Define the number of bytes for storing the tags in a page

[Catalin Marinas]

Rather than explicitly calculating the number of bytes for a compact tag
storage format corresponding to a page, just add a MTE_PAGE_TAG_STORAGE
macro. With the current MTE implementation of 4 bits per tag, we store
2 tags in a byte.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
---
 arch/arm64/include/asm/mte-def.h | 1 +
 arch/arm64/lib/mte.S             | 4 ++--
 arch/arm64/mm/mteswap.c          | 2 +-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/mte-def.h b/arch/arm64/include/asm/mte-def.h
index 626d359b396e..14ee86b019c2 100644
--- a/arch/arm64/include/asm/mte-def.h
+++ b/arch/arm64/include/asm/mte-def.h
@@ -11,6 +11,7 @@
 #define MTE_TAG_SHIFT		56
 #define MTE_TAG_SIZE		4
 #define MTE_TAG_MASK		GENMASK((MTE_TAG_SHIFT + (MTE_TAG_SIZE - 1)), MTE_TAG_SHIFT)
+#define MTE_PAGE_TAG_STORAGE	(MTE_GRANULES_PER_PAGE * MTE_TAG_SIZE / 8)
 
 #define __MTE_PREAMBLE		ARM64_ASM_PREAMBLE ".arch_extension memtag\n"
 
diff --git a/arch/arm64/lib/mte.S b/arch/arm64/lib/mte.S
index f531dcb95174..8590af3c98c0 100644
--- a/arch/arm64/lib/mte.S
+++ b/arch/arm64/lib/mte.S
@@ -134,7 +134,7 @@ SYM_FUNC_END(mte_copy_tags_to_user)
 /*
  * Save the tags in a page
  *   x0 - page address
- *   x1 - tag storage
+ *   x1 - tag storage, MTE_PAGE_TAG_STORAGE bytes
  */
 SYM_FUNC_START(mte_save_page_tags)
 	multitag_transfer_size x7, x5
@@ -158,7 +158,7 @@ SYM_FUNC_END(mte_save_page_tags)
 /*
  * Restore the tags in a page
  *   x0 - page address
- *   x1 - tag storage
+ *   x1 - tag storage, MTE_PAGE_TAG_STORAGE bytes
  */
 SYM_FUNC_START(mte_restore_page_tags)
 	multitag_transfer_size x7, x5
diff --git a/arch/arm64/mm/mteswap.c b/arch/arm64/mm/mteswap.c
index 7c4ef56265ee..a9e50e930484 100644
--- a/arch/arm64/mm/mteswap.c
+++ b/arch/arm64/mm/mteswap.c
@@ -12,7 +12,7 @@ static DEFINE_XARRAY(mte_pages);
 void *mte_allocate_tag_storage(void)
 {
 	/* tags granule is 16 bytes, 2 tags stored per byte */
-	return kmalloc(PAGE_SIZE / 16 / 2, GFP_KERNEL);
+	return kmalloc(MTE_PAGE_TAG_STORAGE, GFP_KERNEL);
 }
 
 void mte_free_tag_storage(char *storage)

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[PATCH v2 4/5] arm64: mte: Dump the MTE tags in the core file

[Catalin Marinas]

For each vma mapped with PROT_MTE (the VM_MTE flag set), generate a
PT_ARM_MEMTAG_MTE segment in the core file and dump the corresponding
tags. The in-file size for such segments is 128 bytes per page.

For pages in a VM_MTE vma which are not present in the user page tables
or don't have the PG_mte_tagged flag set (e.g. execute-only), just write
zeros in the core file.

An example of program headers for two vmas, one 2-page, the other 4-page
long:

  Type           Offset   VirtAddr           PhysAddr           FileSiz  MemSiz   Flg Align
  ...
  LOAD           0x030000 0x0000ffff80034000 0x0000000000000000 0x000000 0x002000 RW  0x1000
  LOAD           0x030000 0x0000ffff80036000 0x0000000000000000 0x004000 0x004000 RW  0x1000
  ...
  LOPROC+0x1     0x05b000 0x0000ffff80034000 0x0000000000000000 0x000100 0x002000     0
  LOPROC+0x1     0x05b100 0x0000ffff80036000 0x0000000000000000 0x000200 0x004000     0

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
---
 arch/arm64/Kconfig          |   1 +
 arch/arm64/kernel/Makefile  |   1 +
 arch/arm64/kernel/elfcore.c | 123 ++++++++++++++++++++++++++++++++++++
 3 files changed, 125 insertions(+)
 create mode 100644 arch/arm64/kernel/elfcore.c

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index f2b5a4abef21..2772c8b97511 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -10,6 +10,7 @@ config ARM64
 	select ACPI_SPCR_TABLE if ACPI
 	select ACPI_PPTT if ACPI
 	select ARCH_HAS_DEBUG_WX
+	select ARCH_BINFMT_ELF_EXTRA_PHDRS
 	select ARCH_BINFMT_ELF_STATE
 	select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE
 	select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 88b3e2a21408..986837d7ec82 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -61,6 +61,7 @@ obj-$(CONFIG_ARM64_ACPI_PARKING_PROTOCOL)	+= acpi_parking_protocol.o
 obj-$(CONFIG_PARAVIRT)			+= paravirt.o
 obj-$(CONFIG_RANDOMIZE_BASE)		+= kaslr.o
 obj-$(CONFIG_HIBERNATION)		+= hibernate.o hibernate-asm.o
+obj-$(CONFIG_ELF_CORE)			+= elfcore.o
 obj-$(CONFIG_KEXEC_CORE)		+= machine_kexec.o relocate_kernel.o	\
 					   cpu-reset.o
 obj-$(CONFIG_KEXEC_FILE)		+= machine_kexec_file.o kexec_image.o
diff --git a/arch/arm64/kernel/elfcore.c b/arch/arm64/kernel/elfcore.c
new file mode 100644
index 000000000000..3455ee4acc04
--- /dev/null
+++ b/arch/arm64/kernel/elfcore.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/coredump.h>
+#include <linux/elfcore.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+
+#include <asm/cpufeature.h>
+#include <asm/mte.h>
+
+#define for_each_mte_vma(tsk, vma)					\
+	if (system_supports_mte())					\
+		for (vma = tsk->mm->mmap; vma; vma = vma->vm_next)	\
+			if (vma->vm_flags & VM_MTE)
+
+static unsigned long mte_vma_tag_dump_size(struct vm_area_struct *vma)
+{
+	if (vma->vm_flags & VM_DONTDUMP)
+		return 0;
+
+	return vma_pages(vma) * MTE_PAGE_TAG_STORAGE;
+}
+
+/* Derived from dump_user_range(); start/end must be page-aligned */
+static int mte_dump_tag_range(struct coredump_params *cprm,
+			      unsigned long start, unsigned long end)
+{
+	unsigned long addr;
+
+	for (addr = start; addr < end; addr += PAGE_SIZE) {
+		char tags[MTE_PAGE_TAG_STORAGE];
+		struct page *page = get_dump_page(addr);
+
+		/*
+		 * get_dump_page() returns NULL when encountering an empty
+		 * page table entry that would otherwise have been filled with
+		 * the zero page. Skip the equivalent tag dump which would
+		 * have been all zeros.
+		 */
+		if (!page) {
+			dump_skip(cprm, MTE_PAGE_TAG_STORAGE);
+			continue;
+		}
+
+		/*
+		 * Pages mapped in user space as !pte_access_permitted() (e.g.
+		 * PROT_EXEC only) may not have the PG_mte_tagged flag set.
+		 */
+		if (!test_bit(PG_mte_tagged, &page->flags)) {
+			put_page(page);
+			dump_skip(cprm, MTE_PAGE_TAG_STORAGE);
+			continue;
+		}
+
+		mte_save_page_tags(page_address(page), tags);
+		put_page(page);
+		if (!dump_emit(cprm, tags, MTE_PAGE_TAG_STORAGE))
+			return 0;
+	}
+
+	return 1;
+}
+
+Elf_Half elf_core_extra_phdrs(void)
+{
+	struct vm_area_struct *vma;
+	int vma_count = 0;
+
+	for_each_mte_vma(current, vma)
+		vma_count++;
+
+	return vma_count;
+}
+
+int elf_core_write_extra_phdrs(struct coredump_params *cprm, loff_t offset)
+{
+	struct vm_area_struct *vma;
+
+	for_each_mte_vma(current, vma) {
+		struct elf_phdr phdr;
+
+		phdr.p_type = PT_ARM_MEMTAG_MTE;
+		phdr.p_offset = offset;
+		phdr.p_vaddr = vma->vm_start;
+		phdr.p_paddr = 0;
+		phdr.p_filesz = mte_vma_tag_dump_size(vma);
+		phdr.p_memsz = vma->vm_end - vma->vm_start;
+		offset += phdr.p_filesz;
+		phdr.p_flags = 0;
+		phdr.p_align = 0;
+
+		if (!dump_emit(cprm, &phdr, sizeof(phdr)))
+			return 0;
+	}
+
+	return 1;
+}
+
+size_t elf_core_extra_data_size(void)
+{
+	struct vm_area_struct *vma;
+	size_t data_size = 0;
+
+	for_each_mte_vma(current, vma)
+		data_size += mte_vma_tag_dump_size(vma);
+
+	return data_size;
+}
+
+int elf_core_write_extra_data(struct coredump_params *cprm)
+{
+	struct vm_area_struct *vma;
+
+	for_each_mte_vma(current, vma) {
+		if (vma->vm_flags & VM_DONTDUMP)
+			continue;
+
+		if (!mte_dump_tag_range(cprm, vma->vm_start, vma->vm_end))
+			return 0;
+	}
+
+	return 1;
+}

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Re: [PATCH v2 4/5] arm64: mte: Dump the MTE tags in the core file

[Mark Brown]

[-- Attachment #1.1: Type: text/plain, Size: 517 bytes --]

On Mon, Jan 31, 2022 at 04:54:55PM +0000, Catalin Marinas wrote:

> For each vma mapped with PROT_MTE (the VM_MTE flag set), generate a
> PT_ARM_MEMTAG_MTE segment in the core file and dump the corresponding
> tags. The in-file size for such segments is 128 bytes per page.

> For pages in a VM_MTE vma which are not present in the user page tables
> or don't have the PG_mte_tagged flag set (e.g. execute-only), just write
> zeros in the core file.

For what it's worth

Reviewed-by: Mark Brown <broonie@kernel.org>

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

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[PATCH v2 5/5] arm64: mte: Document the core dump file format

[Catalin Marinas]

Add the program header definition and data layout for the
PT_ARM_MEMTAG_MTE segments.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Luis Machado <luis.machado@linaro.org>
---
 .../arm64/memory-tagging-extension.rst        | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/Documentation/arm64/memory-tagging-extension.rst b/Documentation/arm64/memory-tagging-extension.rst
index 7b99c8f428eb..5a70d7a3ca12 100644
--- a/Documentation/arm64/memory-tagging-extension.rst
+++ b/Documentation/arm64/memory-tagging-extension.rst
@@ -213,6 +213,29 @@ address ABI control and MTE configuration of a process as per the
 Documentation/arm64/tagged-address-abi.rst and above. The corresponding
 ``regset`` is 1 element of 8 bytes (``sizeof(long))``).
 
+Core dump support
+-----------------
+
+The allocation tags for user memory mapped with ``PROT_MTE`` are dumped
+in the core file as additional ``PT_ARM_MEMTAG_MTE`` segments. The
+program header for such segment is defined as:
+
+:``p_type``: ``PT_ARM_MEMTAG_MTE``
+:``p_flags``: 0
+:``p_offset``: segment file offset
+:``p_vaddr``: segment virtual address, same as the corresponding
+  ``PT_LOAD`` segment
+:``p_paddr``: 0
+:``p_filesz``: segment size in file, calculated as ``p_mem_sz / 32``
+  (two 4-bit tags cover 32 bytes of memory)
+:``p_memsz``: segment size in memory, same as the corresponding
+  ``PT_LOAD`` segment
+:``p_align``: 0
+
+The tags are stored in the core file at ``p_offset`` as two 4-bit tags
+in a byte. With the tag granule of 16 bytes, a 4K page requires 128
+bytes in the core file.
+
 Example of correct usage
 ========================
 

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Re: [PATCH v2 0/5] arm64: mte: add core dump support

[Will Deacon]

On Mon, 31 Jan 2022 16:54:51 +0000, Catalin Marinas wrote:
> This is the second version of the core dump support for MTE tags.
> Changes since v1
> (https://lore.kernel.org/r/20211208121941.494956-1-catalin.marinas@arm.com):
> 
> - Made the documentation slightly clearer on what the size of a segment.
> - Added Luis' acks.
> - Rebased to 5.17-rc2.
> 
> [...]

Applied to arm64 (for-next/mte), thanks!

[1/5] elfcore: Replace CONFIG_{IA64, UML} checks with a new option
      https://git.kernel.org/arm64/c/b62a8486de3a
[2/5] elf: Introduce the ARM MTE ELF segment type
      https://git.kernel.org/arm64/c/761b9b366cec
[3/5] arm64: mte: Define the number of bytes for storing the tags in a page
      https://git.kernel.org/arm64/c/ab1e435ca791
[4/5] arm64: mte: Dump the MTE tags in the core file
      https://git.kernel.org/arm64/c/6dd8b1a0b6cb
[5/5] arm64: mte: Document the core dump file format
      https://git.kernel.org/arm64/c/731451ab3c0c

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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