From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<colnor+dt@kernel.org>, <thippeswamy.havalige@amd.com>,
<michal.simek@amd.com>, <bharat.kumar.gogada@amd.com>
Subject: [PATCH v5 RESEND 1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers
Date: Mon, 16 Oct 2023 10:40:59 +0530 [thread overview]
Message-ID: <20231016051102.1180432-2-thippeswamy.havalige@amd.com> (raw)
In-Reply-To: <20231016051102.1180432-1-thippeswamy.havalige@amd.com>
The primary,secondary and sub-ordinate bus number registers are updated by
Linux PCI core, so remove code which updates respective fields of type 1
header.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
---
changes in v5:
- None
changes in v4:
- None
changes in v3:
- Remove unnecessary period at end of subject line.
- Updated commit message.
changes in v2:
- Code increasing ECAM Size value is added into a seperate patch.
- Modified commit messages.
changes in v1:
- Modified commit messages.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index 176686bdb15c..d8a3a08be1d5 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -166,7 +166,6 @@ struct nwl_pcie {
int irq_intx;
int irq_misc;
u32 ecam_value;
- u8 last_busno;
struct nwl_msi msi;
struct irq_domain *legacy_irq_domain;
struct clk *clk;
@@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
{
struct device *dev = pcie->dev;
struct platform_device *pdev = to_platform_device(dev);
- u32 breg_val, ecam_val, first_busno = 0;
+ u32 breg_val, ecam_val;
int err;
breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
@@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
E_ECAM_BASE_HI);
- /* Get bus range */
- ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
- pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT;
- /* Write primary, secondary and subordinate bus numbers */
- ecam_val = first_busno;
- ecam_val |= (first_busno + 1) << 8;
- ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT);
- writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS));
-
if (nwl_pcie_link_up(pcie))
dev_info(dev, "Link is UP\n");
else
--
2.25.1
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next prev parent reply other threads:[~2023-10-16 5:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-16 5:10 [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Thippeswamy Havalige
2023-10-16 5:10 ` Thippeswamy Havalige [this message]
2023-10-16 5:11 ` [PATCH v5 RESEND 2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
2023-10-16 5:11 ` [PATCH v5 RESEND 3/4] PCI: xilinx-nwl: Rename ECAM size default macro Thippeswamy Havalige
2023-10-16 5:11 ` [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Thippeswamy Havalige
2023-10-20 10:35 ` [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Havalige, Thippeswamy
2023-10-23 17:26 ` Bjorn Helgaas
2023-10-23 17:36 ` Havalige, Thippeswamy
2023-12-16 21:31 ` Krzysztof Wilczyński
-- strict thread matches above, loose matches on Subject: below --
2023-10-05 16:40 [PATCH v5 RESEND 0/4] ncrease " Thippeswamy Havalige
2023-10-05 16:40 ` [PATCH v5 RESEND 1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Thippeswamy Havalige
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