From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<colnor+dt@kernel.org>, <thippeswamy.havalige@amd.com>,
<michal.simek@amd.com>, <bharat.kumar.gogada@amd.com>
Subject: [PATCH v5 RESEND 2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example
Date: Mon, 16 Oct 2023 10:41:00 +0530 [thread overview]
Message-ID: <20231016051102.1180432-3-thippeswamy.havalige@amd.com> (raw)
In-Reply-To: <20231016051102.1180432-1-thippeswamy.havalige@amd.com>
Update ECAM size in example to discover up to 256 buses.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Acked-by: Rob Herring <robh@kernel.org>
---
changes in v5:
None
changes in v4:
None
changes in v3:
Remove period at end of subject line
changes in v2:
None.
changes in v1:
None.
---
Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
index 897602559b37..426f90a47f35 100644
--- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml
@@ -118,7 +118,7 @@ examples:
compatible = "xlnx,nwl-pcie-2.11";
reg = <0x0 0xfd0e0000 0x0 0x1000>,
<0x0 0xfd480000 0x0 0x1000>,
- <0x80 0x00000000 0x0 0x1000000>;
+ <0x80 0x00000000 0x0 0x10000000>;
reg-names = "breg", "pcireg", "cfg";
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
<0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>;
--
2.25.1
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next prev parent reply other threads:[~2023-10-16 5:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-16 5:10 [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Thippeswamy Havalige
2023-10-16 5:10 ` [PATCH v5 RESEND 1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Thippeswamy Havalige
2023-10-16 5:11 ` Thippeswamy Havalige [this message]
2023-10-16 5:11 ` [PATCH v5 RESEND 3/4] PCI: xilinx-nwl: Rename ECAM size default macro Thippeswamy Havalige
2023-10-16 5:11 ` [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Thippeswamy Havalige
2023-10-20 10:35 ` [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Havalige, Thippeswamy
2023-10-23 17:26 ` Bjorn Helgaas
2023-10-23 17:36 ` Havalige, Thippeswamy
2023-12-16 21:31 ` Krzysztof Wilczyński
-- strict thread matches above, loose matches on Subject: below --
2023-10-05 16:40 [PATCH v5 RESEND 0/4] ncrease " Thippeswamy Havalige
2023-10-05 16:40 ` [PATCH v5 RESEND 2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
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