From: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
To: <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <bhelgaas@google.com>, <lpieralisi@kernel.org>, <kw@linux.com>,
<robh@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<colnor+dt@kernel.org>, <thippeswamy.havalige@amd.com>,
<michal.simek@amd.com>, <bharat.kumar.gogada@amd.com>
Subject: [PATCH v5 RESEND 3/4] PCI: xilinx-nwl: Rename ECAM size default macro
Date: Mon, 16 Oct 2023 10:41:01 +0530 [thread overview]
Message-ID: <20231016051102.1180432-4-thippeswamy.havalige@amd.com> (raw)
In-Reply-To: <20231016051102.1180432-1-thippeswamy.havalige@amd.com>
Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove
redundant code
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
---
changes in v5:
Remove period at end of subject line.
---
drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
index d8a3a08be1d5..8fe0e8a325b0 100644
--- a/drivers/pci/controller/pcie-xilinx-nwl.c
+++ b/drivers/pci/controller/pcie-xilinx-nwl.c
@@ -126,7 +126,7 @@
#define E_ECAM_CR_ENABLE BIT(0)
#define E_ECAM_SIZE_LOC GENMASK(20, 16)
#define E_ECAM_SIZE_SHIFT 16
-#define NWL_ECAM_VALUE_DEFAULT 12
+#define NWL_ECAM_MAX_SIZE 12
#define CFG_DMA_REG_BAR GENMASK(2, 0)
#define CFG_PCIE_CACHE GENMASK(7, 0)
@@ -165,7 +165,6 @@ struct nwl_pcie {
u32 ecam_size;
int irq_intx;
int irq_misc;
- u32 ecam_value;
struct nwl_msi msi;
struct irq_domain *legacy_irq_domain;
struct clk *clk;
@@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
- (pcie->ecam_value << E_ECAM_SIZE_SHIFT),
+ (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT),
E_ECAM_CONTROL);
nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
@@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev)
pcie = pci_host_bridge_priv(bridge);
pcie->dev = dev;
- pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT;
err = nwl_pcie_parse_dt(pcie, pdev);
if (err) {
--
2.25.1
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next prev parent reply other threads:[~2023-10-16 5:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-16 5:10 [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Thippeswamy Havalige
2023-10-16 5:10 ` [PATCH v5 RESEND 1/4] PCI: xilinx-nwl: Remove unnecessary code which updates primary, secondary and sub-ordinate bus numbers Thippeswamy Havalige
2023-10-16 5:11 ` [PATCH v5 RESEND 2/4] dt-bindings: PCI: xilinx-nwl: Modify ECAM size in example Thippeswamy Havalige
2023-10-16 5:11 ` Thippeswamy Havalige [this message]
2023-10-16 5:11 ` [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Thippeswamy Havalige
2023-10-20 10:35 ` [PATCH v5 RESEND 0/4] increase ecam size value to discover 256 buses during Havalige, Thippeswamy
2023-10-23 17:26 ` Bjorn Helgaas
2023-10-23 17:36 ` Havalige, Thippeswamy
2023-12-16 21:31 ` Krzysztof Wilczyński
-- strict thread matches above, loose matches on Subject: below --
2023-10-05 16:40 [PATCH v5 RESEND 0/4] ncrease " Thippeswamy Havalige
2023-10-05 16:40 ` [PATCH v5 RESEND 3/4] PCI: xilinx-nwl: Rename ECAM size default macro Thippeswamy Havalige
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