* [PATCH] PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS ms
@ 2024-10-22 8:31 Siddharth Vadapalli
2024-11-02 14:19 ` Krzysztof Wilczyński
0 siblings, 1 reply; 3+ messages in thread
From: Siddharth Vadapalli @ 2024-10-22 8:31 UTC (permalink / raw)
To: bhelgaas, lpieralisi, kw, robh, vigneshr, manivannan.sadhasivam,
thomas.richard
Cc: linux-omap, linux-pci, linux-kernel, linux-arm-kernel, srk,
s-vadapalli
According to Section 2.2 of the PCI Express Card Electromechanical
Specification (Revision 5.1), in order to ensure that the power and the
reference clock are stable, PERST# has to be deasserted after a delay of
100 milliseconds (TPVPERL). Currently, it is being assumed that the power
is already stable, which is not necessarily true. Hence, change the delay
to PCIE_T_PVPERL_MS to guarantee that power and reference clock are stable.
Fixes: f96b69713733 ("PCI: j721e: Use T_PERST_CLK_US macro")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Hello,
This patch is based on commit
c2ee9f594da8 KVM: selftests: Fix build on on non-x86 architectures
of Mainline Linux.
Regards,
Siddharth.
drivers/pci/controller/cadence/pci-j721e.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c
index 284f2e0e4d26..e464cfc2c332 100644
--- a/drivers/pci/controller/cadence/pci-j721e.c
+++ b/drivers/pci/controller/cadence/pci-j721e.c
@@ -671,15 +671,14 @@ static int j721e_pcie_resume_noirq(struct device *dev)
return ret;
/*
- * The "Power Sequencing and Reset Signal Timings" table of the
- * PCI Express Card Electromechanical Specification, Revision
- * 5.1, Section 2.9.2, Symbol "T_PERST-CLK", indicates PERST#
- * should be deasserted after minimum of 100us once REFCLK is
- * stable. The REFCLK to the connector in RC mode is selected
- * while enabling the PHY. So deassert PERST# after 100 us.
+ * Section 2.2 of the PCI Express Card Electromechanical
+ * Specification (Revision 5.1) mandates that the deassertion
+ * of the PERST# signal should be delayed by 100 ms (TPVPERL).
+ * This shall ensure that the power and the reference clock
+ * are stable.
*/
if (pcie->reset_gpio) {
- fsleep(PCIE_T_PERST_CLK_US);
+ msleep(PCIE_T_PVPERL_MS);
gpiod_set_value_cansleep(pcie->reset_gpio, 1);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS ms
2024-10-22 8:31 [PATCH] PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS ms Siddharth Vadapalli
@ 2024-11-02 14:19 ` Krzysztof Wilczyński
2024-11-04 7:08 ` Siddharth Vadapalli
0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Wilczyński @ 2024-11-02 14:19 UTC (permalink / raw)
To: Siddharth Vadapalli
Cc: bhelgaas, lpieralisi, robh, vigneshr, manivannan.sadhasivam,
thomas.richard, linux-omap, linux-pci, linux-kernel,
linux-arm-kernel, srk
Hello,
> According to Section 2.2 of the PCI Express Card Electromechanical
> Specification (Revision 5.1), in order to ensure that the power and the
> reference clock are stable, PERST# has to be deasserted after a delay of
> 100 milliseconds (TPVPERL). Currently, it is being assumed that the power
> is already stable, which is not necessarily true. Hence, change the delay
> to PCIE_T_PVPERL_MS to guarantee that power and reference clock are stable.
[...]
> This patch is based on commit
> c2ee9f594da8 KVM: selftests: Fix build on on non-x86 architectures
> of Mainline Linux.
Why KVM? Do you have the link to this commit handy?
[...]
> if (pcie->reset_gpio) {
> - fsleep(PCIE_T_PERST_CLK_US);
> + msleep(PCIE_T_PVPERL_MS);
fsleep() with the same macro and for the same reason is also used in the
j721e_pcie_probe() callback. I think, we would want both changed.
Krzysztof
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS ms
2024-11-02 14:19 ` Krzysztof Wilczyński
@ 2024-11-04 7:08 ` Siddharth Vadapalli
0 siblings, 0 replies; 3+ messages in thread
From: Siddharth Vadapalli @ 2024-11-04 7:08 UTC (permalink / raw)
To: Krzysztof Wilczyński
Cc: Siddharth Vadapalli, bhelgaas, lpieralisi, robh, vigneshr,
manivannan.sadhasivam, thomas.richard, linux-omap, linux-pci,
linux-kernel, linux-arm-kernel, srk
On Sat, Nov 02, 2024 at 11:19:14PM +0900, Krzysztof Wilczyński wrote:
> Hello,
>
> > According to Section 2.2 of the PCI Express Card Electromechanical
> > Specification (Revision 5.1), in order to ensure that the power and the
> > reference clock are stable, PERST# has to be deasserted after a delay of
> > 100 milliseconds (TPVPERL). Currently, it is being assumed that the power
> > is already stable, which is not necessarily true. Hence, change the delay
> > to PCIE_T_PVPERL_MS to guarantee that power and reference clock are stable.
> [...]
> > This patch is based on commit
> > c2ee9f594da8 KVM: selftests: Fix build on on non-x86 architectures
> > of Mainline Linux.
>
> Why KVM? Do you have the link to this commit handy?
Since this is a fix, I had based the patch on the latest Mainline Linux
with the head corresponding to the aforementioned commit. Link:
https://github.com/torvalds/linux/commit/c2ee9f594da8
>
> [...]
> > if (pcie->reset_gpio) {
> > - fsleep(PCIE_T_PERST_CLK_US);
> > + msleep(PCIE_T_PVPERL_MS);
>
> fsleep() with the same macro and for the same reason is also used in the
> j721e_pcie_probe() callback. I think, we would want both changed.
Thank you for pointing this out. I will update it in the v2 patch.
Regards,
Siddharth.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2024-10-22 8:31 [PATCH] PCI: j721e: Deassert PERST# after a delay of PCIE_T_PVPERL_MS ms Siddharth Vadapalli
2024-11-02 14:19 ` Krzysztof Wilczyński
2024-11-04 7:08 ` Siddharth Vadapalli
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