From: Atish Patra <atishp@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
weilin.wang@intel.com
Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Conor Dooley <conor@kernel.org>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-perf-users@vger.kernel.org,
Atish Patra <atishp@rivosinc.com>,
Kaiwen Xue <kaiwenx@rivosinc.com>
Subject: [PATCH v4 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions
Date: Wed, 05 Feb 2025 23:23:07 -0800 [thread overview]
Message-ID: <20250205-counter_delegation-v4-2-835cfa88e3b1@rivosinc.com> (raw)
In-Reply-To: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com>
From: Kaiwen Xue <kaiwenx@rivosinc.com>
This adds definitions of new CSRs and bits defined in Sxcsrind ISA
extension. These CSR enables indirect accesses mechanism to access
any CSRs in M-, S-, and VS-mode. The range of the select values
and ireg will be define by the ISA extension using Sxcsrind extension.
Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index 37bdea65bbd8..2ad2d492e6b4 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -318,6 +318,12 @@
/* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */
#define CSR_SISELECT 0x150
#define CSR_SIREG 0x151
+/* Supervisor-Level Window to Indirectly Accessed Registers (Sxcsrind) */
+#define CSR_SIREG2 0x152
+#define CSR_SIREG3 0x153
+#define CSR_SIREG4 0x155
+#define CSR_SIREG5 0x156
+#define CSR_SIREG6 0x157
/* Supervisor-Level Interrupts (AIA) */
#define CSR_STOPEI 0x15c
@@ -365,6 +371,14 @@
/* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */
#define CSR_VSISELECT 0x250
#define CSR_VSIREG 0x251
+/*
+ * VS-Level Window to Indirectly Accessed Registers (H-extension with Sxcsrind)
+ */
+#define CSR_VSIREG2 0x252
+#define CSR_VSIREG3 0x253
+#define CSR_VSIREG4 0x255
+#define CSR_VSIREG5 0x256
+#define CSR_VISREG6 0x257
/* VS-Level Interrupts (H-extension with AIA) */
#define CSR_VSTOPEI 0x25c
@@ -407,6 +421,12 @@
/* Machine-Level Window to Indirectly Accessed Registers (AIA) */
#define CSR_MISELECT 0x350
#define CSR_MIREG 0x351
+/* Machine-Level Window to Indrecitly Accessed Registers (Sxcsrind) */
+#define CSR_MIREG2 0x352
+#define CSR_MIREG3 0x353
+#define CSR_MIREG4 0x355
+#define CSR_MIREG5 0x356
+#define CSR_MIREG6 0x357
/* Machine-Level Interrupts (AIA) */
#define CSR_MTOPEI 0x35c
@@ -452,6 +472,11 @@
# define CSR_IEH CSR_MIEH
# define CSR_ISELECT CSR_MISELECT
# define CSR_IREG CSR_MIREG
+# define CSR_IREG2 CSR_MIREG2
+# define CSR_IREG3 CSR_MIREG3
+# define CSR_IREG4 CSR_MIREG4
+# define CSR_IREG5 CSR_MIREG5
+# define CSR_IREG6 CSR_MIREG6
# define CSR_IPH CSR_MIPH
# define CSR_TOPEI CSR_MTOPEI
# define CSR_TOPI CSR_MTOPI
@@ -477,6 +502,11 @@
# define CSR_IEH CSR_SIEH
# define CSR_ISELECT CSR_SISELECT
# define CSR_IREG CSR_SIREG
+# define CSR_IREG2 CSR_SIREG2
+# define CSR_IREG3 CSR_SIREG3
+# define CSR_IREG4 CSR_SIREG4
+# define CSR_IREG5 CSR_SIREG5
+# define CSR_IREG6 CSR_SIREG6
# define CSR_IPH CSR_SIPH
# define CSR_TOPEI CSR_STOPEI
# define CSR_TOPI CSR_STOPI
--
2.43.0
next prev parent reply other threads:[~2025-02-06 7:27 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-06 7:23 [PATCH v4 00/21] Add Counter delegation ISA extension support Atish Patra
2025-02-06 7:23 ` [PATCH v4 01/21] perf pmu-events: Add functions in jevent.py to parse counter and event info for hardware aware grouping Atish Patra
2025-02-06 7:23 ` Atish Patra [this message]
2025-02-07 7:57 ` [PATCH v4 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions Clément Léger
2025-02-06 7:23 ` [PATCH v4 03/21] RISC-V: Add Sxcsrind ISA extension definition and parsing Atish Patra
2025-02-06 7:23 ` [PATCH v4 04/21] dt-bindings: riscv: add Sxcsrind ISA extension description Atish Patra
2025-02-19 14:09 ` Rob Herring (Arm)
2025-02-06 7:23 ` [PATCH v4 05/21] RISC-V: Define indirect CSR access helpers Atish Patra
2025-02-06 7:23 ` [PATCH v4 06/21] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2025-02-07 9:21 ` Clément Léger
2025-02-06 7:23 ` [PATCH v4 07/21] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2025-02-19 14:09 ` Rob Herring (Arm)
2025-02-06 7:23 ` [PATCH v4 08/21] RISC-V: Add Sscfg extension CSR definition Atish Patra
2025-02-07 9:30 ` Clément Léger
2025-02-27 0:03 ` Atish Kumar Patra
2025-02-06 7:23 ` [PATCH v4 09/21] RISC-V: Add Ssccfg ISA extension definition and parsing Atish Patra
2025-02-07 8:08 ` Clément Léger
2025-02-07 8:13 ` Clément Léger
2025-02-27 0:06 ` Atish Kumar Patra
2025-02-06 7:23 ` [PATCH v4 10/21] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2025-02-06 8:39 ` Rob Herring (Arm)
2025-02-06 7:23 ` [PATCH v4 11/21] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2025-02-06 10:51 ` Will Deacon
2025-02-07 16:53 ` Atish Kumar Patra
2025-02-07 9:59 ` Clément Léger
2025-02-06 7:23 ` [PATCH v4 12/21] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2025-02-07 10:29 ` Clément Léger
2025-02-27 1:05 ` Atish Kumar Patra
2025-02-06 7:23 ` [PATCH v4 13/21] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2025-02-06 7:23 ` [PATCH v4 14/21] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2025-02-06 7:23 ` [PATCH v4 15/21] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2025-02-06 7:23 ` [PATCH v4 16/21] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2025-02-06 7:23 ` [PATCH v4 17/21] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2025-02-06 7:23 ` [PATCH v4 18/21] RISC-V: perf: Add Qemu virt machine events Atish Patra
2025-02-06 7:23 ` [PATCH v4 19/21] tools/perf: Support event code for arch standard events Atish Patra
2025-02-06 7:23 ` [PATCH v4 20/21] tools/perf: Pass the Counter constraint values in the pmu events Atish Patra
2025-02-06 7:23 ` [PATCH v4 21/21] Sync empty-pmu-events.c with autogenerated one Atish Patra
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