[BOOT-WRAPPER PATCH 0/3] Enable use of FPMR and ZT0

[BOOT-WRAPPER PATCH 0/3] Enable use of FPMR and ZT0

[Mark Rutland]

When the kernel gained support for FEAT_FPMR and FEAT_SME2,
corresponding support was not added to the boot-wrapper. Both of these
features require some (trivial) enablement to avoid traps being taken to
EL3 durung normal operation.

These patches add the missing support to the boot-wrapper.

The first two patches were prviously posted as part of an earlier
series:

  https://lore.kernel.org/linux-arm-kernel/20241126153955.477569-1-mark.rutland@arm.com/

I've updated their commit messages for clarity, but I have made no
functional changes.

Mark.

Mark Rutland (3):
  aarch64: shuffle ID_AA64PFR{0,1}_EL1 definitions
  aarch64: Enable use of FPMR
  aarch64: Enable use of ZT0

 arch/aarch64/include/asm/cpu.h | 11 ++++++++---
 arch/aarch64/init.c            |  6 ++++++
 2 files changed, 14 insertions(+), 3 deletions(-)

-- 
2.30.2

[BOOT-WRAPPER PATCH 1/3] aarch64: shuffle ID_AA64PFR{0,1}_EL1 definitions

[Mark Rutland]

Usually the ID register definitions are sorted alphanumerically, but for
historical reasons the ID_AA64PFR0_* definitions are placed before the
ID_AA64PFR1_* definitions. Reorder these for consistency.

There should be no functional change as a result of this patch.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
 arch/aarch64/include/asm/cpu.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index b04bf71..22d6cbf 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -116,15 +116,15 @@
 #define ID_AA64MMFR3_EL1_S2POE		BITS(23, 20)
 #define ID_AA64MMFR3_EL1_D128		BITS(35, 32)
 
+#define ID_AA64PFR0_EL1_RAS		BITS(31, 28)
+#define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
+#define ID_AA64PFR0_EL1_CSV2		BITS(59, 56)
+
 #define ID_AA64PFR1_EL1_MTE		BITS(11, 8)
 #define ID_AA64PFR1_EL1_SME		BITS(27, 24)
 #define ID_AA64PFR1_EL1_CSV2_frac	BITS(35, 32)
 #define ID_AA64PFR1_EL1_THE		BITS(51, 48)
 
-#define ID_AA64PFR0_EL1_RAS		BITS(31, 28)
-#define ID_AA64PFR0_EL1_SVE		BITS(35, 32)
-#define ID_AA64PFR0_EL1_CSV2		BITS(59, 56)
-
 #define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
 #define ID_AA64SMFR0_EL1_FA64		BIT(63)
 
-- 
2.30.2

[BOOT-WRAPPER PATCH 2/3] aarch64: Enable use of FPMR

[Mark Rutland]

FEAT_FPMR adds the FPMR register. Acceses to FPMR (whether direct or
indirect) trap to EL3 unless SCR_EL3.EnFPM is set, and so boot-wrapper
support is necessary.

Support for FEAT_FPMR was added to Linux in v6.8 without any
boot-wrapper support. Consequently when FPMR is enabled in a model, the
kernel will hang when attempting to write to the FPMR (e.g. when
entering userspace for the first time).

Add boot-wrapper support for FEAT_FPMR, as described in the latest ARM
ARM (ARM DDI 0487 L.a), which can be found at:

  https://developer.arm.com/documentation/ddi0487/la/?lang=en

The ID_AA64PFR2_EL1 ID register has existed as reserved RES0 space since
ARMv8.0 but only recently gained a name, and so older assemblers may not
be able to encode ID_AA64PFR2_EL1 directly. Thus we need an explicit
definition of the sysreg encoding to support these assemblers.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/aarch64/include/asm/cpu.h | 4 ++++
 arch/aarch64/init.c            | 3 +++
 2 files changed, 7 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index 22d6cbf..aab7657 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -75,6 +75,7 @@
 #define SCR_EL3_SCTLR2En		BIT(44)
 #define SCR_EL3_PIEN			BIT(45)
 #define SCR_EL3_D128En			BIT(47)
+#define SCR_EL3_EnFPM			BIT(50)
 #define SCR_EL3_FGTEN2			BIT(59)
 
 #define VTCR_EL2_MSA			BIT(31)
@@ -125,6 +126,9 @@
 #define ID_AA64PFR1_EL1_CSV2_frac	BITS(35, 32)
 #define ID_AA64PFR1_EL1_THE		BITS(51, 48)
 
+#define ID_AA64PFR2_EL1			s3_0_c0_c4_2
+#define ID_AA64PFR2_EL1_FPMR		BITS(35, 32)
+
 #define ID_AA64SMFR0_EL1		s3_0_c0_c4_5
 #define ID_AA64SMFR0_EL1_FA64		BIT(63)
 
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index fe7ed5f..bb19848 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -133,6 +133,9 @@ static void cpu_init_el3(void)
 	if (mrs_field(ID_AA64PFR1_EL1, THE))
 		scr |= SCR_EL3_RCWMASKEn;
 
+	if (mrs_field(ID_AA64PFR2_EL1, FPMR))
+		scr |= SCR_EL3_EnFPM;
+
 	msr(SCR_EL3, scr);
 
 	msr(CPTR_EL3, cptr);
-- 
2.30.2

[BOOT-WRAPPER PATCH 3/3] aarch64: Enable use of ZT0

[Mark Rutland]

FEAT_SME2 adds the ZT0 register. Accesses to ZT0 trap to EL3 unless
SMCR_EL3.EZT0 is set, and so boot-wrapper support is necessary.

Support for FEAT_SME2 was added to Linux in v6.3 without any
boot-wrapper support. Consequently when SME2 is enabled in a model, any
attempt to access ZT0 (whether in userspace, kernel, or hypervisor) will
result in a hang. Linux will (only) access ZT0 during a context switch
when PSTATE.ZA==1, and so this hang is seen long after boot, when
applications first set PSTATE.ZA.

Add boot-wrapper support for ZT0, as described in the latest ARM ARM
(ARM DDI 0487 L.a), which can be found at:

  https://developer.arm.com/documentation/ddi0487/la/?lang=en

All we need to do at EL3 is set SMCR_EL3.EZT0; it's up to lower ELs to
configure their SMCR_ELx register appropriately.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Mark Brown <broonie@kernel.org>
---
 arch/aarch64/include/asm/cpu.h | 1 +
 arch/aarch64/init.c            | 3 +++
 2 files changed, 4 insertions(+)

diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index aab7657..2b3a659 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -175,6 +175,7 @@
 #define ZCR_EL3_LEN_MAX		0xf
 
 #define SMCR_EL3		s3_6_c1_c2_6
+#define SMCR_EL3_EZT0		BIT(30)
 #define SMCR_EL3_FA64		BIT(31)
 #define SMCR_EL3_LEN_MAX	0xf
 
diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c
index bb19848..e1640a9 100644
--- a/arch/aarch64/init.c
+++ b/arch/aarch64/init.c
@@ -189,6 +189,9 @@ static void cpu_init_el3(void)
 		if (mrs_field(ID_AA64SMFR0_EL1, FA64))
 			smcr |= SMCR_EL3_FA64;
 
+		if (mrs_field(ID_AA64PFR1_EL1, SME) >= 2)
+			smcr |= SMCR_EL3_EZT0;
+
 		msr(SMCR_EL3, smcr);
 	}
 }
-- 
2.30.2

Re: [BOOT-WRAPPER PATCH 0/3] Enable use of FPMR and ZT0

[Mark Rutland]

On Sun, May 11, 2025 at 10:52:08AM +0100, Mark Rutland wrote:
> When the kernel gained support for FEAT_FPMR and FEAT_SME2,
> corresponding support was not added to the boot-wrapper. Both of these
> features require some (trivial) enablement to avoid traps being taken to
> EL3 durung normal operation.
> 
> These patches add the missing support to the boot-wrapper.

Applied.

Mark.