* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-08-20 18:46 ` [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia Bjorn Helgaas
@ 2025-08-20 19:08 ` Jan Palus
2025-08-20 19:30 ` Bjorn Helgaas
2025-08-21 0:45 ` Jan Palus
2025-09-02 20:32 ` Pali Rohár
2 siblings, 1 reply; 11+ messages in thread
From: Jan Palus @ 2025-08-20 19:08 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Rob Herring, Thomas Petazzoni, Pali Rohár, linux-arm-kernel,
linux-pci, regressions
On 20.08.2025 13:46, Bjorn Helgaas wrote:
> [+cc maintainers, regressions list]
>
> Jan, thanks very much for the report and the bisection. Could you
> attach the devicetree you're using to the bugzilla?
I guess I could dump it from running system if you'd like me to, but it's
an upstream one without any customizations.
> On Wed, Aug 20, 2025 at 05:43:39PM +0000, bugzilla-daemon@kernel.org wrote:
> > https://bugzilla.kernel.org/show_bug.cgi?id=220479
> >
> > Summary: [regression 6.16] mvebu: no pci devices detected on
> > turris omnia
> > Reporter: jpalus@fastmail.com
> >
> > Booting kernel 6.16 results in no PCI devices being detected (output of `lspci`
> > is completely empty). Bisected to:
> >
> > 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 is the first new commit
> > commit 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 (HEAD)
> > Author: Rob Herring (Arm) <robh@kernel.org>
> > Date: Thu Nov 7 16:32:55 2024
> >
> > PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"
> >
> > The mvebu "ranges" is a bit unusual with its own encoding of addresses,
> > but it's still just normal "ranges" as far as parsing is concerned.
> > Convert mvebu_get_tgt_attr() to use the for_each_of_range() iterator
> > instead of open coding the parsing.
> >
> > Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Link: https://patch.msgid.link/20241107153255.2740610-1-robh@kernel.org
> >
> > drivers/pci/controller/pci-mvebu.c | 26 +++++++++-----------------
> > 1 file changed, 9 insertions(+), 17 deletions(-)
> >
> >
> > kernel 6.16 logs following mesages related to PCI:
> >
> > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: pcie0.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: pcie1.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: pcie2.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > pci_bus 0000:00: root bus resource [bus 00-ff]
> > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > [0x00080000-0x00081fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > [0x00040000-0x00041fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > [0x00044000-0x00045fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > [0x00048000-0x00049fff])
> > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > PCI: bus0: Fast back to back transfers enabled
> > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> >
> >
> > while kernel 6.15 logs following:
> >
> > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: pcie0.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > pci_bus 0000:00: root bus resource [bus 00-ff]
> > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > [0x00080000-0x00081fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > [0x00040000-0x00041fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > [0x00044000-0x00045fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > [0x00048000-0x00049fff])
> > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > pci 0000:00:01.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:01.0: PCI bridge to [bus 00]
> > pci 0000:00:01.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@1,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@1,0/interrupt-controller
> > pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:02.0: PCI bridge to [bus 00]
> > pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@2,0/interrupt-controller
> > pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:03.0: PCI bridge to [bus 00]
> > pci 0000:00:03.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@3,0/interrupt-controller
> > PCI: bus0: Fast back to back transfers disabled
> > pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > PCI: bus1: Fast back to back transfers enabled
> > pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> > pci 0000:02:00.0: [168c:003c] type 00 class 0x028000 PCIe Endpoint
> > pci 0000:02:00.0: BAR 0 [mem 0x00000000-0x001fffff 64bit]
> > pci 0000:02:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > pci 0000:02:00.0: supports D1
> > pci 0000:02:00.0: PME# supported from D0 D1 D3hot
> > pci 0000:00:02.0: ASPM: current common clock configuration is inconsistent,
> > reconfiguring
> > pci 0000:00:02.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > pci 0000:00:02.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > PCI: bus2: Fast back to back transfers disabled
> > pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
> > pci 0000:03:00.0: [168c:0033] type 00 class 0x028000 PCIe Endpoint
> > pci 0000:03:00.0: BAR 0 [mem 0x00000000-0x0001ffff 64bit]
> > pci 0000:03:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > pci 0000:03:00.0: supports D1
> > pci 0000:03:00.0: PME# supported from D0 D1 D3hot
> > pci 0000:00:03.0: ASPM: current common clock configuration is inconsistent,
> > reconfiguring
> > pci 0000:00:03.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > pci 0000:00:03.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > PCI: bus3: Fast back to back transfers disabled
> > pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
> > pci 0000:00:02.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02]
> > add_size 200000 add_align 200000
> > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned
> > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]: assigned
> > pci 0000:00:01.0: PCI bridge to [bus 01]
> > pci 0000:02:00.0: BAR 0 [mem 0xe0000000-0xe01fffff 64bit]: assigned
> > pci 0000:02:00.0: ROM [mem 0xe0200000-0xe020ffff pref]: assigned
> > pci 0000:00:02.0: PCI bridge to [bus 02]
> > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]
> > pci 0000:03:00.0: BAR 0 [mem 0xe0400000-0xe041ffff 64bit]: assigned
> > pci 0000:03:00.0: ROM [mem 0xe0420000-0xe042ffff pref]: assigned
> > pci 0000:00:03.0: PCI bridge to [bus 03]
> > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]
> > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> > pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe03fffff]
> > pci_bus 0000:03: resource 1 [mem 0xe0400000-0xe04fffff]
> > pcieport 0000:00:02.0: enabling device (0140 -> 0142)
> > pcieport 0000:00:03.0: enabling device (0140 -> 0142)
>
> #regzbot introduced: 5da3d94a23c6 ("PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"")
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-08-20 19:08 ` Jan Palus
@ 2025-08-20 19:30 ` Bjorn Helgaas
2025-08-20 19:51 ` Jan Palus
0 siblings, 1 reply; 11+ messages in thread
From: Bjorn Helgaas @ 2025-08-20 19:30 UTC (permalink / raw)
To: Jan Palus
Cc: Rob Herring, Thomas Petazzoni, Pali Rohár, linux-arm-kernel,
linux-pci, regressions
On Wed, Aug 20, 2025 at 09:08:33PM +0200, Jan Palus wrote:
> On 20.08.2025 13:46, Bjorn Helgaas wrote:
> > [+cc maintainers, regressions list]
> >
> > Jan, thanks very much for the report and the bisection. Could you
> > attach the devicetree you're using to the bugzilla?
>
> I guess I could dump it from running system if you'd like me to, but it's
> an upstream one without any customizations.
It's just easier if we know exactly what you're using. I'm not an
mvebu user and can't guess.
> > On Wed, Aug 20, 2025 at 05:43:39PM +0000, bugzilla-daemon@kernel.org wrote:
> > > https://bugzilla.kernel.org/show_bug.cgi?id=220479
> > >
> > > Summary: [regression 6.16] mvebu: no pci devices detected on
> > > turris omnia
> > > Reporter: jpalus@fastmail.com
> > >
> > > Booting kernel 6.16 results in no PCI devices being detected (output of `lspci`
> > > is completely empty). Bisected to:
> > >
> > > 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 is the first new commit
> > > commit 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 (HEAD)
> > > Author: Rob Herring (Arm) <robh@kernel.org>
> > > Date: Thu Nov 7 16:32:55 2024
> > >
> > > PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"
> > >
> > > The mvebu "ranges" is a bit unusual with its own encoding of addresses,
> > > but it's still just normal "ranges" as far as parsing is concerned.
> > > Convert mvebu_get_tgt_attr() to use the for_each_of_range() iterator
> > > instead of open coding the parsing.
> > >
> > > Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > Link: https://patch.msgid.link/20241107153255.2740610-1-robh@kernel.org
> > >
> > > drivers/pci/controller/pci-mvebu.c | 26 +++++++++-----------------
> > > 1 file changed, 9 insertions(+), 17 deletions(-)
> > >
> > >
> > > kernel 6.16 logs following mesages related to PCI:
> > >
> > > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > mvebu-pcie soc:pcie: pcie0.0: cannot get tgt/attr for mem window
> > > mvebu-pcie soc:pcie: pcie1.0: cannot get tgt/attr for mem window
> > > mvebu-pcie soc:pcie: pcie2.0: cannot get tgt/attr for mem window
> > > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > > pci_bus 0000:00: root bus resource [bus 00-ff]
> > > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > > [0x00080000-0x00081fff])
> > > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > > [0x00040000-0x00041fff])
> > > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > > [0x00044000-0x00045fff])
> > > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > > [0x00048000-0x00049fff])
> > > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > > PCI: bus0: Fast back to back transfers enabled
> > > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> > >
> > >
> > > while kernel 6.15 logs following:
> > >
> > > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > mvebu-pcie soc:pcie: pcie0.0: Slot power limit 10.0W
> > > mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W
> > > mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W
> > > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > > pci_bus 0000:00: root bus resource [bus 00-ff]
> > > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > > [0x00080000-0x00081fff])
> > > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > > [0x00040000-0x00041fff])
> > > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > > [0x00044000-0x00045fff])
> > > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > > [0x00048000-0x00049fff])
> > > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > > pci 0000:00:01.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > > pci 0000:00:01.0: PCI bridge to [bus 00]
> > > pci 0000:00:01.0: bridge window [io 0x0000-0x0fff]
> > > pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff]
> > > /soc/pcie/pcie@1,0: Fixed dependency cycle(s) with
> > > /soc/pcie/pcie@1,0/interrupt-controller
> > > pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > > pci 0000:00:02.0: PCI bridge to [bus 00]
> > > pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
> > > pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
> > > /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with
> > > /soc/pcie/pcie@2,0/interrupt-controller
> > > pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > > pci 0000:00:03.0: PCI bridge to [bus 00]
> > > pci 0000:00:03.0: bridge window [io 0x0000-0x0fff]
> > > pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff]
> > > /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with
> > > /soc/pcie/pcie@3,0/interrupt-controller
> > > PCI: bus0: Fast back to back transfers disabled
> > > pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > > pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > > pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > > PCI: bus1: Fast back to back transfers enabled
> > > pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> > > pci 0000:02:00.0: [168c:003c] type 00 class 0x028000 PCIe Endpoint
> > > pci 0000:02:00.0: BAR 0 [mem 0x00000000-0x001fffff 64bit]
> > > pci 0000:02:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > > pci 0000:02:00.0: supports D1
> > > pci 0000:02:00.0: PME# supported from D0 D1 D3hot
> > > pci 0000:00:02.0: ASPM: current common clock configuration is inconsistent,
> > > reconfiguring
> > > pci 0000:00:02.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > > pci 0000:00:02.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > > PCI: bus2: Fast back to back transfers disabled
> > > pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
> > > pci 0000:03:00.0: [168c:0033] type 00 class 0x028000 PCIe Endpoint
> > > pci 0000:03:00.0: BAR 0 [mem 0x00000000-0x0001ffff 64bit]
> > > pci 0000:03:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > > pci 0000:03:00.0: supports D1
> > > pci 0000:03:00.0: PME# supported from D0 D1 D3hot
> > > pci 0000:00:03.0: ASPM: current common clock configuration is inconsistent,
> > > reconfiguring
> > > pci 0000:00:03.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > > pci 0000:00:03.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > > PCI: bus3: Fast back to back transfers disabled
> > > pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
> > > pci 0000:00:02.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02]
> > > add_size 200000 add_align 200000
> > > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned
> > > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]: assigned
> > > pci 0000:00:01.0: PCI bridge to [bus 01]
> > > pci 0000:02:00.0: BAR 0 [mem 0xe0000000-0xe01fffff 64bit]: assigned
> > > pci 0000:02:00.0: ROM [mem 0xe0200000-0xe020ffff pref]: assigned
> > > pci 0000:00:02.0: PCI bridge to [bus 02]
> > > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]
> > > pci 0000:03:00.0: BAR 0 [mem 0xe0400000-0xe041ffff 64bit]: assigned
> > > pci 0000:03:00.0: ROM [mem 0xe0420000-0xe042ffff pref]: assigned
> > > pci 0000:00:03.0: PCI bridge to [bus 03]
> > > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]
> > > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> > > pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe03fffff]
> > > pci_bus 0000:03: resource 1 [mem 0xe0400000-0xe04fffff]
> > > pcieport 0000:00:02.0: enabling device (0140 -> 0142)
> > > pcieport 0000:00:03.0: enabling device (0140 -> 0142)
> >
> > #regzbot introduced: 5da3d94a23c6 ("PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"")
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-08-20 19:30 ` Bjorn Helgaas
@ 2025-08-20 19:51 ` Jan Palus
0 siblings, 0 replies; 11+ messages in thread
From: Jan Palus @ 2025-08-20 19:51 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Rob Herring, Thomas Petazzoni, Pali Rohár, linux-arm-kernel,
linux-pci, regressions
On 20.08.2025 14:30, Bjorn Helgaas wrote:
> On Wed, Aug 20, 2025 at 09:08:33PM +0200, Jan Palus wrote:
> > On 20.08.2025 13:46, Bjorn Helgaas wrote:
> > > [+cc maintainers, regressions list]
> > >
> > > Jan, thanks very much for the report and the bisection. Could you
> > > attach the devicetree you're using to the bugzilla?
> >
> > I guess I could dump it from running system if you'd like me to, but it's
> > an upstream one without any customizations.
>
> It's just easier if we know exactly what you're using. I'm not an
> mvebu user and can't guess.
>
Just to make it clear, as stated in summary, issue concerns Turris Omnia
device for which following dts is applicable:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts?h=v6.16
> > > On Wed, Aug 20, 2025 at 05:43:39PM +0000, bugzilla-daemon@kernel.org wrote:
> > > > https://bugzilla.kernel.org/show_bug.cgi?id=220479
> > > >
> > > > Summary: [regression 6.16] mvebu: no pci devices detected on
> > > > turris omnia
> > > > Reporter: jpalus@fastmail.com
> > > >
> > > > Booting kernel 6.16 results in no PCI devices being detected (output of `lspci`
> > > > is completely empty). Bisected to:
> > > >
> > > > 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 is the first new commit
> > > > commit 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 (HEAD)
> > > > Author: Rob Herring (Arm) <robh@kernel.org>
> > > > Date: Thu Nov 7 16:32:55 2024
> > > >
> > > > PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"
> > > >
> > > > The mvebu "ranges" is a bit unusual with its own encoding of addresses,
> > > > but it's still just normal "ranges" as far as parsing is concerned.
> > > > Convert mvebu_get_tgt_attr() to use the for_each_of_range() iterator
> > > > instead of open coding the parsing.
> > > >
> > > > Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> > > > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > > > Link: https://patch.msgid.link/20241107153255.2740610-1-robh@kernel.org
> > > >
> > > > drivers/pci/controller/pci-mvebu.c | 26 +++++++++-----------------
> > > > 1 file changed, 9 insertions(+), 17 deletions(-)
> > > >
> > > >
> > > > kernel 6.16 logs following mesages related to PCI:
> > > >
> > > > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > > > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > > > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > > > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > > > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > > mvebu-pcie soc:pcie: pcie0.0: cannot get tgt/attr for mem window
> > > > mvebu-pcie soc:pcie: pcie1.0: cannot get tgt/attr for mem window
> > > > mvebu-pcie soc:pcie: pcie2.0: cannot get tgt/attr for mem window
> > > > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > > > pci_bus 0000:00: root bus resource [bus 00-ff]
> > > > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > > > [0x00080000-0x00081fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > > > [0x00040000-0x00041fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > > > [0x00044000-0x00045fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > > > [0x00048000-0x00049fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > > > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > > > PCI: bus0: Fast back to back transfers enabled
> > > > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > > > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > > > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > > > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > > > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > > > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> > > >
> > > >
> > > > while kernel 6.15 logs following:
> > > >
> > > > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > > > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > > > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > > > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > > > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > > > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > > > mvebu-pcie soc:pcie: pcie0.0: Slot power limit 10.0W
> > > > mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W
> > > > mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W
> > > > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > > > pci_bus 0000:00: root bus resource [bus 00-ff]
> > > > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > > > [0x00080000-0x00081fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > > > [0x00040000-0x00041fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > > > [0x00044000-0x00045fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > > > [0x00048000-0x00049fff])
> > > > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > > > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > > > pci 0000:00:01.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > > > pci 0000:00:01.0: PCI bridge to [bus 00]
> > > > pci 0000:00:01.0: bridge window [io 0x0000-0x0fff]
> > > > pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff]
> > > > /soc/pcie/pcie@1,0: Fixed dependency cycle(s) with
> > > > /soc/pcie/pcie@1,0/interrupt-controller
> > > > pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > > > pci 0000:00:02.0: PCI bridge to [bus 00]
> > > > pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
> > > > pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
> > > > /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with
> > > > /soc/pcie/pcie@2,0/interrupt-controller
> > > > pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > > > pci 0000:00:03.0: PCI bridge to [bus 00]
> > > > pci 0000:00:03.0: bridge window [io 0x0000-0x0fff]
> > > > pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff]
> > > > /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with
> > > > /soc/pcie/pcie@3,0/interrupt-controller
> > > > PCI: bus0: Fast back to back transfers disabled
> > > > pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > > > pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > > > pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > > > PCI: bus1: Fast back to back transfers enabled
> > > > pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> > > > pci 0000:02:00.0: [168c:003c] type 00 class 0x028000 PCIe Endpoint
> > > > pci 0000:02:00.0: BAR 0 [mem 0x00000000-0x001fffff 64bit]
> > > > pci 0000:02:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > > > pci 0000:02:00.0: supports D1
> > > > pci 0000:02:00.0: PME# supported from D0 D1 D3hot
> > > > pci 0000:00:02.0: ASPM: current common clock configuration is inconsistent,
> > > > reconfiguring
> > > > pci 0000:00:02.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > > > pci 0000:00:02.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > > > PCI: bus2: Fast back to back transfers disabled
> > > > pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
> > > > pci 0000:03:00.0: [168c:0033] type 00 class 0x028000 PCIe Endpoint
> > > > pci 0000:03:00.0: BAR 0 [mem 0x00000000-0x0001ffff 64bit]
> > > > pci 0000:03:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > > > pci 0000:03:00.0: supports D1
> > > > pci 0000:03:00.0: PME# supported from D0 D1 D3hot
> > > > pci 0000:00:03.0: ASPM: current common clock configuration is inconsistent,
> > > > reconfiguring
> > > > pci 0000:00:03.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > > > pci 0000:00:03.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > > > PCI: bus3: Fast back to back transfers disabled
> > > > pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
> > > > pci 0000:00:02.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02]
> > > > add_size 200000 add_align 200000
> > > > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned
> > > > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]: assigned
> > > > pci 0000:00:01.0: PCI bridge to [bus 01]
> > > > pci 0000:02:00.0: BAR 0 [mem 0xe0000000-0xe01fffff 64bit]: assigned
> > > > pci 0000:02:00.0: ROM [mem 0xe0200000-0xe020ffff pref]: assigned
> > > > pci 0000:00:02.0: PCI bridge to [bus 02]
> > > > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]
> > > > pci 0000:03:00.0: BAR 0 [mem 0xe0400000-0xe041ffff 64bit]: assigned
> > > > pci 0000:03:00.0: ROM [mem 0xe0420000-0xe042ffff pref]: assigned
> > > > pci 0000:00:03.0: PCI bridge to [bus 03]
> > > > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]
> > > > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > > > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > > > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > > > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > > > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > > > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> > > > pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe03fffff]
> > > > pci_bus 0000:03: resource 1 [mem 0xe0400000-0xe04fffff]
> > > > pcieport 0000:00:02.0: enabling device (0140 -> 0142)
> > > > pcieport 0000:00:03.0: enabling device (0140 -> 0142)
> > >
> > > #regzbot introduced: 5da3d94a23c6 ("PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"")
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-08-20 18:46 ` [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia Bjorn Helgaas
2025-08-20 19:08 ` Jan Palus
@ 2025-08-21 0:45 ` Jan Palus
2025-09-02 9:09 ` Klaus Kudielka
2025-09-02 20:32 ` Pali Rohár
2 siblings, 1 reply; 11+ messages in thread
From: Jan Palus @ 2025-08-21 0:45 UTC (permalink / raw)
To: Rob Herring
Cc: Bjorn Helgaas, Thomas Petazzoni, Pali Rohár,
linux-arm-kernel, linux-pci, regressions
> On Wed, Aug 20, 2025 at 05:43:39PM +0000, bugzilla-daemon@kernel.org wrote:
> > https://bugzilla.kernel.org/show_bug.cgi?id=220479
> >
> > Summary: [regression 6.16] mvebu: no pci devices detected on
> > turris omnia
> > Reporter: jpalus@fastmail.com
> >
> > Booting kernel 6.16 results in no PCI devices being detected (output of `lspci`
> > is completely empty). Bisected to:
> >
> > 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 is the first new commit
> > commit 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 (HEAD)
> > Author: Rob Herring (Arm) <robh@kernel.org>
> > Date: Thu Nov 7 16:32:55 2024
> >
> > PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"
> >
> > The mvebu "ranges" is a bit unusual with its own encoding of addresses,
> > but it's still just normal "ranges" as far as parsing is concerned.
> > Convert mvebu_get_tgt_attr() to use the for_each_of_range() iterator
> > instead of open coding the parsing.
> >
> > Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Link: https://patch.msgid.link/20241107153255.2740610-1-robh@kernel.org
> >
> > drivers/pci/controller/pci-mvebu.c | 26 +++++++++-----------------
> > 1 file changed, 9 insertions(+), 17 deletions(-)
> >
> >
> > kernel 6.16 logs following mesages related to PCI:
> >
> > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: pcie0.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: pcie1.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: pcie2.0: cannot get tgt/attr for mem window
Relevant fragment of mvebu_get_tgt_attr() in mentioned commit:
+ u32 slot = upper_32_bits(range.bus_addr);
- if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
+ if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_IO)
rtype = IORESOURCE_IO;
- else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
+ else if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_MEM32)
rtype = IORESOURCE_MEM;
else
continue;
if (slot == PCI_SLOT(devfn) && type == rtype) {
mvebu_get_tgt_attr() gets called with type (either 512 or 256) and slot
(1, 2 or 3), after this commit last condition is never met though --
slot is fine but rtype never is.
What appears to be very much different are values of previous 'flags'
and current 'range.flags'. Judging by the code they should still carry
same values but in practice
before: flags=2181038080 end up with rtype=512 (match)
after: range.flags=512 results in no rtype (no match)
before: flags=2164260864 end up with rtype=256 (match)
after: range.flags=256 results in no rtype (no match)
as if now range.flags already represented rtype directly. If I use it
like this situation improves, bridge gets detected, although whole device
reboots without any error on first probe from card driver. Something
that I've noticed during bisect but seems to be an independent
regression.
> > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > pci_bus 0000:00: root bus resource [bus 00-ff]
> > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > [0x00080000-0x00081fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > [0x00040000-0x00041fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > [0x00044000-0x00045fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > [0x00048000-0x00049fff])
> > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > PCI: bus0: Fast back to back transfers enabled
> > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> >
> >
> > while kernel 6.15 logs following:
> >
> > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: pcie0.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > pci_bus 0000:00: root bus resource [bus 00-ff]
> > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > [0x00080000-0x00081fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > [0x00040000-0x00041fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > [0x00044000-0x00045fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > [0x00048000-0x00049fff])
> > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > pci 0000:00:01.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:01.0: PCI bridge to [bus 00]
> > pci 0000:00:01.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@1,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@1,0/interrupt-controller
> > pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:02.0: PCI bridge to [bus 00]
> > pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@2,0/interrupt-controller
> > pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:03.0: PCI bridge to [bus 00]
> > pci 0000:00:03.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@3,0/interrupt-controller
> > PCI: bus0: Fast back to back transfers disabled
> > pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > PCI: bus1: Fast back to back transfers enabled
> > pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> > pci 0000:02:00.0: [168c:003c] type 00 class 0x028000 PCIe Endpoint
> > pci 0000:02:00.0: BAR 0 [mem 0x00000000-0x001fffff 64bit]
> > pci 0000:02:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > pci 0000:02:00.0: supports D1
> > pci 0000:02:00.0: PME# supported from D0 D1 D3hot
> > pci 0000:00:02.0: ASPM: current common clock configuration is inconsistent,
> > reconfiguring
> > pci 0000:00:02.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > pci 0000:00:02.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > PCI: bus2: Fast back to back transfers disabled
> > pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
> > pci 0000:03:00.0: [168c:0033] type 00 class 0x028000 PCIe Endpoint
> > pci 0000:03:00.0: BAR 0 [mem 0x00000000-0x0001ffff 64bit]
> > pci 0000:03:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > pci 0000:03:00.0: supports D1
> > pci 0000:03:00.0: PME# supported from D0 D1 D3hot
> > pci 0000:00:03.0: ASPM: current common clock configuration is inconsistent,
> > reconfiguring
> > pci 0000:00:03.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > pci 0000:00:03.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > PCI: bus3: Fast back to back transfers disabled
> > pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
> > pci 0000:00:02.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02]
> > add_size 200000 add_align 200000
> > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned
> > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]: assigned
> > pci 0000:00:01.0: PCI bridge to [bus 01]
> > pci 0000:02:00.0: BAR 0 [mem 0xe0000000-0xe01fffff 64bit]: assigned
> > pci 0000:02:00.0: ROM [mem 0xe0200000-0xe020ffff pref]: assigned
> > pci 0000:00:02.0: PCI bridge to [bus 02]
> > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]
> > pci 0000:03:00.0: BAR 0 [mem 0xe0400000-0xe041ffff 64bit]: assigned
> > pci 0000:03:00.0: ROM [mem 0xe0420000-0xe042ffff pref]: assigned
> > pci 0000:00:03.0: PCI bridge to [bus 03]
> > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]
> > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> > pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe03fffff]
> > pci_bus 0000:03: resource 1 [mem 0xe0400000-0xe04fffff]
> > pcieport 0000:00:02.0: enabling device (0140 -> 0142)
> > pcieport 0000:00:03.0: enabling device (0140 -> 0142)
>
> #regzbot introduced: 5da3d94a23c6 ("PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"")
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-08-21 0:45 ` Jan Palus
@ 2025-09-02 9:09 ` Klaus Kudielka
2025-09-02 10:33 ` Klaus Kudielka
0 siblings, 1 reply; 11+ messages in thread
From: Klaus Kudielka @ 2025-09-02 9:09 UTC (permalink / raw)
To: Jan Palus, Rob Herring
Cc: Bjorn Helgaas, Thomas Petazzoni, Pali Rohár,
linux-arm-kernel, linux-pci, regressions
On Thu, 2025-08-21 at 02:45 +0200, Jan Palus wrote:
>
> Relevant fragment of mvebu_get_tgt_attr() in mentioned commit:
>
> + u32 slot = upper_32_bits(range.bus_addr);
>
> - if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
> + if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_IO)
> rtype = IORESOURCE_IO;
> - else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
> + else if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_MEM32)
> rtype = IORESOURCE_MEM;
> else
> continue;
>
> if (slot == PCI_SLOT(devfn) && type == rtype) {
>
As far as I understand the situation, of_pci_range_parser_one() inherently uses bus->get_flags()
aka of_bus_pci_get_flags() to determine range.flags (see drivers/of/address.c).
And of_bus_pci_get_flags() does essentially the same thing as the code above in mvebu_get_tgt_attr().
So, now the translation logic is applied twice - which probably was not intended.
To restore the original behaviour, I think the determination of rtype from range.flags must be
completely removed, and rtype must be replaced by range.flags.
Something like this on top of mainline - completely untested, but maybe worth a try.
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 755651f338..3fce4a2b63 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -1168,9 +1168,6 @@ static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
return devm_ioremap_resource(&pdev->dev, &port->regs);
}
-#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
-#define DT_TYPE_IO 0x1
-#define DT_TYPE_MEM32 0x2
#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
#define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
@@ -1189,17 +1186,9 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
return -EINVAL;
for_each_of_range(&parser, &range) {
- unsigned long rtype;
u32 slot = upper_32_bits(range.bus_addr);
- if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_IO)
- rtype = IORESOURCE_IO;
- else if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_MEM32)
- rtype = IORESOURCE_MEM;
- else
- continue;
-
- if (slot == PCI_SLOT(devfn) && type == rtype) {
+ if (slot == PCI_SLOT(devfn) && type == range.flags) {
*tgt = DT_CPUADDR_TO_TARGET(range.cpu_addr);
*attr = DT_CPUADDR_TO_ATTR(range.cpu_addr);
return 0;
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-09-02 9:09 ` Klaus Kudielka
@ 2025-09-02 10:33 ` Klaus Kudielka
0 siblings, 0 replies; 11+ messages in thread
From: Klaus Kudielka @ 2025-09-02 10:33 UTC (permalink / raw)
To: Jan Palus, Rob Herring
Cc: Bjorn Helgaas, Thomas Petazzoni, Pali Rohár,
linux-arm-kernel, linux-pci, regressions
On Tue, 2025-09-02 at 11:09 +0200, Klaus Kudielka wrote:
> Something like this on top of mainline - completely untested, but maybe worth a try.
>
> diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
> index 755651f338..3fce4a2b63 100644
> --- a/drivers/pci/controller/pci-mvebu.c
> +++ b/drivers/pci/controller/pci-mvebu.c
> @@ -1168,9 +1168,6 @@ static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
> return devm_ioremap_resource(&pdev->dev, &port->regs);
> }
>
> -#define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
> -#define DT_TYPE_IO 0x1
> -#define DT_TYPE_MEM32 0x2
> #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
> #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
>
> @@ -1189,17 +1186,9 @@ static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
> return -EINVAL;
>
> for_each_of_range(&parser, &range) {
> - unsigned long rtype;
> u32 slot = upper_32_bits(range.bus_addr);
>
> - if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_IO)
> - rtype = IORESOURCE_IO;
> - else if (DT_FLAGS_TO_TYPE(range.flags) == DT_TYPE_MEM32)
> - rtype = IORESOURCE_MEM;
> - else
> - continue;
> -
> - if (slot == PCI_SLOT(devfn) && type == rtype) {
> + if (slot == PCI_SLOT(devfn) && type == range.flags) {
> *tgt = DT_CPUADDR_TO_TARGET(range.cpu_addr);
> *attr = DT_CPUADDR_TO_ATTR(range.cpu_addr);
> return 0;
>
Following up myself. With this patch on top of 6.17.0-rc4, I do see the PCI bridges for the two free slots on my Turris Omnia.
One slot is occupied by mSATA. I don't have any suitable Mini-PCIe card to test, though.
$ lspci
00:02.0 PCI bridge: Marvell Technology Group Ltd. 88F6820 [Armada 385] ARM SoC (rev 04)
00:03.0 PCI bridge: Marvell Technology Group Ltd. 88F6820 [Armada 385] ARM SoC (rev 04)
$ dmesg | head -5
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 6.17.0-rc4+ (klaus@mars) (arm-linux-gnueabihf-gcc (Debian 14.3.0-5) 14.3.0, GNU ld (GNU Binutils for Debian) 2.45) #10 SMP Tue Sep 2 11:49:13 CEST 2025
[ 0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=10c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Turris Omnia
$ dmesg | grep -i pci
[ 0.015195] PCI: CLS 0 bytes, default 64
[ 0.026199] mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
[ 0.026224] mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
[ 0.026240] mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
[ 0.026253] mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
[ 0.026265] mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
[ 0.026278] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
[ 0.026290] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
[ 0.026302] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
[ 0.026314] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
[ 0.026326] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
[ 0.026338] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
[ 0.026350] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
[ 0.026358] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
[ 0.026554] mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W
[ 0.026743] mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W
[ 0.026955] mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
[ 0.026963] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.026970] pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address [0x00080000-0x00081fff])
[ 0.026976] pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address [0x00040000-0x00041fff])
[ 0.026981] pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address [0x00044000-0x00045fff])
[ 0.026986] pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address [0x00048000-0x00049fff])
[ 0.026991] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
[ 0.026995] pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
[ 0.027113] pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
[ 0.027127] pci 0000:00:02.0: PCI bridge to [bus 00]
[ 0.027134] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
[ 0.027138] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
[ 0.027277] /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with /soc/pcie/pcie@2,0/interrupt-controller
[ 0.027311] pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
[ 0.027323] pci 0000:00:03.0: PCI bridge to [bus 00]
[ 0.027329] pci 0000:00:03.0: bridge window [io 0x0000-0x0fff]
[ 0.027333] pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff]
[ 0.027443] /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with /soc/pcie/pcie@3,0/interrupt-controller
[ 0.028311] PCI: bus0: Fast back to back transfers disabled
[ 0.028319] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 0.028327] pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 0.028418] PCI: bus1: Fast back to back transfers enabled
[ 0.028424] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 0.028506] PCI: bus2: Fast back to back transfers enabled
[ 0.028510] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
[ 0.028526] pci 0000:00:02.0: PCI bridge to [bus 01]
[ 0.028535] pci 0000:00:03.0: PCI bridge to [bus 02]
[ 0.028542] pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
[ 0.028547] pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
[ 0.028552] pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
[ 0.028556] pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
[ 0.028560] pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
[ 0.028564] pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-08-20 18:46 ` [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia Bjorn Helgaas
2025-08-20 19:08 ` Jan Palus
2025-08-21 0:45 ` Jan Palus
@ 2025-09-02 20:32 ` Pali Rohár
2025-09-03 1:35 ` Rob Herring
2 siblings, 1 reply; 11+ messages in thread
From: Pali Rohár @ 2025-09-02 20:32 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Rob Herring, Thomas Petazzoni, Jan Palus, linux-arm-kernel,
linux-pci, regressions
These issues have been discussed more times for last 3 years.
Tested changes which are fixing real bugs and are improving the
pci-mvebu.c driver from people listed as M: in MAINTAINERS are being
rejected or silently ignored. And untested changes which are not going
to fix any bug are being accepted and causing new regressions. People
then reporting bug reports to M: people who cannot do anything with it.
The only advice which they can get is to not use mainline kernel.
This pci-mvebu.c driver in mainline kernel is broken and nobody wanted
to do anything with this situation for last 3 years, I was pointing for
it more times. Due to this I'm ignoring bug reports for pci-mvebu.c
driver for mainline kernel.
On Wednesday 20 August 2025 13:46:03 Bjorn Helgaas wrote:
> [+cc maintainers, regressions list]
>
> Jan, thanks very much for the report and the bisection. Could you
> attach the devicetree you're using to the bugzilla?
>
> On Wed, Aug 20, 2025 at 05:43:39PM +0000, bugzilla-daemon@kernel.org wrote:
> > https://bugzilla.kernel.org/show_bug.cgi?id=220479
> >
> > Summary: [regression 6.16] mvebu: no pci devices detected on
> > turris omnia
> > Reporter: jpalus@fastmail.com
> >
> > Booting kernel 6.16 results in no PCI devices being detected (output of `lspci`
> > is completely empty). Bisected to:
> >
> > 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 is the first new commit
> > commit 5da3d94a23c6c1ee1f896aeeb00965eacf1d0bb3 (HEAD)
> > Author: Rob Herring (Arm) <robh@kernel.org>
> > Date: Thu Nov 7 16:32:55 2024
> >
> > PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"
> >
> > The mvebu "ranges" is a bit unusual with its own encoding of addresses,
> > but it's still just normal "ranges" as far as parsing is concerned.
> > Convert mvebu_get_tgt_attr() to use the for_each_of_range() iterator
> > instead of open coding the parsing.
> >
> > Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> > Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> > Link: https://patch.msgid.link/20241107153255.2740610-1-robh@kernel.org
> >
> > drivers/pci/controller/pci-mvebu.c | 26 +++++++++-----------------
> > 1 file changed, 9 insertions(+), 17 deletions(-)
> >
> >
> > kernel 6.16 logs following mesages related to PCI:
> >
> > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: pcie0.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: pcie1.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: pcie2.0: cannot get tgt/attr for mem window
> > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > pci_bus 0000:00: root bus resource [bus 00-ff]
> > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > [0x00080000-0x00081fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > [0x00040000-0x00041fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > [0x00044000-0x00045fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > [0x00048000-0x00049fff])
> > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > PCI: bus0: Fast back to back transfers enabled
> > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> >
> >
> > while kernel 6.15 logs following:
> >
> > mvebu-pcie soc:pcie: host bridge /soc/pcie ranges:
> > mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> 0x0000080000
> > mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> 0x0000040000
> > mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> 0x0000044000
> > mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> 0x0000048000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0100000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0200000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0300000000
> > mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00fffffffe -> 0x0400000000
> > mvebu-pcie soc:pcie: pcie0.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W
> > mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00
> > pci_bus 0000:00: root bus resource [bus 00-ff]
> > pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081fff] (bus address
> > [0x00080000-0x00081fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041fff] (bus address
> > [0x00040000-0x00041fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045fff] (bus address
> > [0x00044000-0x00045fff])
> > pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049fff] (bus address
> > [0x00048000-0x00049fff])
> > pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: root bus resource [io 0x1000-0xeffff]
> > pci 0000:00:01.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:01.0: PCI bridge to [bus 00]
> > pci 0000:00:01.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:01.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@1,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@1,0/interrupt-controller
> > pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:02.0: PCI bridge to [bus 00]
> > pci 0000:00:02.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@2,0/interrupt-controller
> > pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Root Port
> > pci 0000:00:03.0: PCI bridge to [bus 00]
> > pci 0000:00:03.0: bridge window [io 0x0000-0x0fff]
> > pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff]
> > /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with
> > /soc/pcie/pcie@3,0/interrupt-controller
> > PCI: bus0: Fast back to back transfers disabled
> > pci 0000:00:01.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > pci 0000:00:02.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring
> > PCI: bus1: Fast back to back transfers enabled
> > pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
> > pci 0000:02:00.0: [168c:003c] type 00 class 0x028000 PCIe Endpoint
> > pci 0000:02:00.0: BAR 0 [mem 0x00000000-0x001fffff 64bit]
> > pci 0000:02:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > pci 0000:02:00.0: supports D1
> > pci 0000:02:00.0: PME# supported from D0 D1 D3hot
> > pci 0000:00:02.0: ASPM: current common clock configuration is inconsistent,
> > reconfiguring
> > pci 0000:00:02.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > pci 0000:00:02.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > PCI: bus2: Fast back to back transfers disabled
> > pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02
> > pci 0000:03:00.0: [168c:0033] type 00 class 0x028000 PCIe Endpoint
> > pci 0000:03:00.0: BAR 0 [mem 0x00000000-0x0001ffff 64bit]
> > pci 0000:03:00.0: ROM [mem 0x00000000-0x0000ffff pref]
> > pci 0000:03:00.0: supports D1
> > pci 0000:03:00.0: PME# supported from D0 D1 D3hot
> > pci 0000:00:03.0: ASPM: current common clock configuration is inconsistent,
> > reconfiguring
> > pci 0000:00:03.0: ASPM: Bridge does not support changing Link Speed to 2.5 GT/s
> > pci 0000:00:03.0: ASPM: Retrain Link at higher speed is disallowed by quirk
> > PCI: bus3: Fast back to back transfers disabled
> > pci_bus 0000:03: busn_res: [bus 03-ff] end is updated to 03
> > pci 0000:00:02.0: bridge window [mem 0x00200000-0x003fffff] to [bus 02]
> > add_size 200000 add_align 200000
> > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]: assigned
> > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]: assigned
> > pci 0000:00:01.0: PCI bridge to [bus 01]
> > pci 0000:02:00.0: BAR 0 [mem 0xe0000000-0xe01fffff 64bit]: assigned
> > pci 0000:02:00.0: ROM [mem 0xe0200000-0xe020ffff pref]: assigned
> > pci 0000:00:02.0: PCI bridge to [bus 02]
> > pci 0000:00:02.0: bridge window [mem 0xe0000000-0xe03fffff]
> > pci 0000:03:00.0: BAR 0 [mem 0xe0400000-0xe041ffff 64bit]: assigned
> > pci 0000:03:00.0: ROM [mem 0xe0420000-0xe042ffff pref]: assigned
> > pci 0000:00:03.0: PCI bridge to [bus 03]
> > pci 0000:00:03.0: bridge window [mem 0xe0400000-0xe04fffff]
> > pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff]
> > pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff]
> > pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff]
> > pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff]
> > pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff]
> > pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]
> > pci_bus 0000:02: resource 1 [mem 0xe0000000-0xe03fffff]
> > pci_bus 0000:03: resource 1 [mem 0xe0400000-0xe04fffff]
> > pcieport 0000:00:02.0: enabling device (0140 -> 0142)
> > pcieport 0000:00:03.0: enabling device (0140 -> 0142)
>
> #regzbot introduced: 5da3d94a23c6 ("PCI: mvebu: Use for_each_of_range() iterator for parsing "ranges"")
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-09-02 20:32 ` Pali Rohár
@ 2025-09-03 1:35 ` Rob Herring
2025-09-03 7:35 ` Pali Rohár
0 siblings, 1 reply; 11+ messages in thread
From: Rob Herring @ 2025-09-03 1:35 UTC (permalink / raw)
To: Pali Rohár
Cc: Bjorn Helgaas, Thomas Petazzoni, Jan Palus, linux-arm-kernel,
linux-pci, regressions
On Tue, Sep 2, 2025 at 3:32 PM Pali Rohár <pali@kernel.org> wrote:
>
> These issues have been discussed more times for last 3 years.
> Tested changes which are fixing real bugs and are improving the
> pci-mvebu.c driver from people listed as M: in MAINTAINERS are being
> rejected or silently ignored. And untested changes which are not going
> to fix any bug are being accepted and causing new regressions. People
> then reporting bug reports to M: people who cannot do anything with it.
> The only advice which they can get is to not use mainline kernel.
> This pci-mvebu.c driver in mainline kernel is broken and nobody wanted
> to do anything with this situation for last 3 years, I was pointing for
> it more times. Due to this I'm ignoring bug reports for pci-mvebu.c
> driver for mainline kernel.
This makes no sense. Mainline is broken, but yet there's a regression
in mainline breaking the driver. The pci-mvebu.c maintainers have the
ability to test patches, but refuse to test any submitted patches
other than their own. I guess the only solution here is just remove
the driver...
Rob
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-09-03 1:35 ` Rob Herring
@ 2025-09-03 7:35 ` Pali Rohár
2025-09-03 7:50 ` Manivannan Sadhasivam
0 siblings, 1 reply; 11+ messages in thread
From: Pali Rohár @ 2025-09-03 7:35 UTC (permalink / raw)
To: Rob Herring
Cc: Bjorn Helgaas, Thomas Petazzoni, Jan Palus, linux-arm-kernel,
linux-pci, regressions
On Tuesday 02 September 2025 20:35:14 Rob Herring wrote:
> On Tue, Sep 2, 2025 at 3:32 PM Pali Rohár <pali@kernel.org> wrote:
> >
> > These issues have been discussed more times for last 3 years.
> > Tested changes which are fixing real bugs and are improving the
> > pci-mvebu.c driver from people listed as M: in MAINTAINERS are being
> > rejected or silently ignored. And untested changes which are not going
> > to fix any bug are being accepted and causing new regressions. People
> > then reporting bug reports to M: people who cannot do anything with it.
> > The only advice which they can get is to not use mainline kernel.
> > This pci-mvebu.c driver in mainline kernel is broken and nobody wanted
> > to do anything with this situation for last 3 years, I was pointing for
> > it more times. Due to this I'm ignoring bug reports for pci-mvebu.c
> > driver for mainline kernel.
>
> This makes no sense. Mainline is broken, but yet there's a regression
> in mainline breaking the driver. The pci-mvebu.c maintainers have the
> ability to test patches, but refuse to test any submitted patches
> other than their own. I guess the only solution here is just remove
> the driver...
>
> Rob
This is not the way how to get patches being tested. Ignoring other
people and taking untested patches because you did not wanted to
communicate with maintainers. I have no reason to test other patches if
my own are being ignored. This is fair. In past I spent lot of time on
addressing issues in this driver, preparing fixes for real bugs and
whole time was wasted. And if you expected that it would work in that,
then go ahead and do it, remove the driver.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia
2025-09-03 7:35 ` Pali Rohár
@ 2025-09-03 7:50 ` Manivannan Sadhasivam
0 siblings, 0 replies; 11+ messages in thread
From: Manivannan Sadhasivam @ 2025-09-03 7:50 UTC (permalink / raw)
To: Pali Rohár
Cc: Rob Herring, Bjorn Helgaas, Thomas Petazzoni, Jan Palus,
linux-arm-kernel, linux-pci, regressions
On Wed, Sep 03, 2025 at 09:35:58AM GMT, Pali Rohár wrote:
> On Tuesday 02 September 2025 20:35:14 Rob Herring wrote:
> > On Tue, Sep 2, 2025 at 3:32 PM Pali Rohár <pali@kernel.org> wrote:
> > >
> > > These issues have been discussed more times for last 3 years.
> > > Tested changes which are fixing real bugs and are improving the
> > > pci-mvebu.c driver from people listed as M: in MAINTAINERS are being
> > > rejected or silently ignored. And untested changes which are not going
> > > to fix any bug are being accepted and causing new regressions. People
> > > then reporting bug reports to M: people who cannot do anything with it.
> > > The only advice which they can get is to not use mainline kernel.
> > > This pci-mvebu.c driver in mainline kernel is broken and nobody wanted
> > > to do anything with this situation for last 3 years, I was pointing for
> > > it more times. Due to this I'm ignoring bug reports for pci-mvebu.c
> > > driver for mainline kernel.
> >
> > This makes no sense. Mainline is broken, but yet there's a regression
> > in mainline breaking the driver. The pci-mvebu.c maintainers have the
> > ability to test patches, but refuse to test any submitted patches
> > other than their own. I guess the only solution here is just remove
> > the driver...
> >
> > Rob
>
> This is not the way how to get patches being tested. Ignoring other
> people and taking untested patches because you did not wanted to
> communicate with maintainers. I have no reason to test other patches if
> my own are being ignored. This is fair. In past I spent lot of time on
> addressing issues in this driver, preparing fixes for real bugs and
> whole time was wasted. And if you expected that it would work in that,
> then go ahead and do it, remove the driver.
>
Pali, as I communicated earlier, please send your fixes again and I'll try to
get them merged if we do not have any blocking reasons and the patches make
sense. I do not know what happened earlier with your patches and that's
irrelevant for me.
But if none of the other mainainters oppose your changes (IRQ in specific),
there are no reasons to not merge them IMO. But if there are concerns, then it
is your job to address them.
That being said, if you do not want to send them again and the driver continues
to being untested in mainline, we may need to mark it as Orphan/Obsolete and get
it removed later.
- Mani
--
மணிவண்ணன் சதாசிவம்
^ permalink raw reply [flat|nested] 11+ messages in thread