[PATCH 1/4] arm64: dts: imx8mp: switch usb controller to flattened model

[PATCH 1/4] arm64: dts: imx8mp: switch usb controller to flattened model

[Xu Yang]

Switch to use flattened model for all USB controllers. To enable USB
controllers with restricted DMA access range to work correctly, add a
pseudo simple-bus to constrain the dma address.

Also reorder USB-related nodes.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp.dtsi | 161 ++++++++++------------
 1 file changed, 76 insertions(+), 85 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 90d7bb8f5619..8b3aab14ccf1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -2329,6 +2329,82 @@ gpu2d: gpu@38008000 {
 			power-domains = <&pgc_gpu2d>;
 		};
 
+		bus@38100000 {
+			compatible = "simple-bus";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
+			ranges;
+
+			usb3_0: usb_dwc3_0: usb@38100000 {
+				compatible = "nxp,imx8mp-dwc3";
+				reg = <0x38100000 0x10000>,
+				      <0x32f10100 0x8>,
+				      <0x381f0000 0x20>;
+				reg-names = "core", "blkctl", "glue";
+				clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+					 <&clk IMX8MP_CLK_USB_ROOT>,
+					 <&clk IMX8MP_CLK_USB_CORE_REF>,
+					 <&clk IMX8MP_CLK_USB_SUSP>;
+				clock-names = "hsio", "bus_early", "ref", "suspend";
+				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "dwc_usb3", "wakeup";
+				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
+				phys = <&usb3_phy0>, <&usb3_phy0>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,gfladj-refclk-lpm-sel-quirk;
+				snps,parkmode-disable-ss-quirk;
+				status = "disabled";
+			};
+
+			usb3_1: usb_dwc3_1: usb@38200000 {
+				compatible = "nxp,imx8mp-dwc3";
+				reg = <0x38200000 0x10000>,
+				      <0x32f10108 0x8>,
+				      <0x382f0000 0x20>;
+				reg-names = "core", "blkctl", "glue";
+				clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+					 <&clk IMX8MP_CLK_USB_ROOT>,
+					 <&clk IMX8MP_CLK_USB_CORE_REF>,
+					 <&clk IMX8MP_CLK_USB_SUSP>;
+				clock-names = "hsio", "bus_early", "ref", "suspend";
+				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "dwc_usb3", "wakeup";
+				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
+				phys = <&usb3_phy1>, <&usb3_phy1>;
+				phy-names = "usb2-phy", "usb3-phy";
+				snps,gfladj-refclk-lpm-sel-quirk;
+				snps,parkmode-disable-ss-quirk;
+				status = "disabled";
+			};
+		};
+
+		usb3_phy0: usb-phy@381f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x381f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
+		usb3_phy1: usb-phy@382f0040 {
+			compatible = "fsl,imx8mp-usb-phy";
+			reg = <0x382f0040 0x40>;
+			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
+			clock-names = "phy";
+			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
+			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
+			#phy-cells = <0>;
+			status = "disabled";
+		};
+
 		vpu_g1: video-codec@38300000 {
 			compatible = "nxp,imx8mm-vpu-g1";
 			reg = <0x38300000 0x10000>;
@@ -2407,91 +2483,6 @@ ddr-pmu@3d800000 {
 			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
-		usb3_phy0: usb-phy@381f0040 {
-			compatible = "fsl,imx8mp-usb-phy";
-			reg = <0x381f0040 0x40>;
-			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
-			clock-names = "phy";
-			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
-			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
-			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
-			#phy-cells = <0>;
-			status = "disabled";
-		};
-
-		usb3_0: usb@32f10100 {
-			compatible = "fsl,imx8mp-dwc3";
-			reg = <0x32f10100 0x8>,
-			      <0x381f0000 0x20>;
-			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-				 <&clk IMX8MP_CLK_USB_SUSP>;
-			clock-names = "hsio", "suspend";
-			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
-			ranges;
-			status = "disabled";
-
-			usb_dwc3_0: usb@38100000 {
-				compatible = "snps,dwc3";
-				reg = <0x38100000 0x10000>;
-				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
-					 <&clk IMX8MP_CLK_USB_CORE_REF>,
-					 <&clk IMX8MP_CLK_USB_SUSP>;
-				clock-names = "bus_early", "ref", "suspend";
-				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb3_phy0>, <&usb3_phy0>;
-				phy-names = "usb2-phy", "usb3-phy";
-				snps,gfladj-refclk-lpm-sel-quirk;
-				snps,parkmode-disable-ss-quirk;
-			};
-
-		};
-
-		usb3_phy1: usb-phy@382f0040 {
-			compatible = "fsl,imx8mp-usb-phy";
-			reg = <0x382f0040 0x40>;
-			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
-			clock-names = "phy";
-			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
-			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
-			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
-			#phy-cells = <0>;
-			status = "disabled";
-		};
-
-		usb3_1: usb@32f10108 {
-			compatible = "fsl,imx8mp-dwc3";
-			reg = <0x32f10108 0x8>,
-			      <0x382f0000 0x20>;
-			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
-				 <&clk IMX8MP_CLK_USB_SUSP>;
-			clock-names = "hsio", "suspend";
-			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
-			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
-			ranges;
-			status = "disabled";
-
-			usb_dwc3_1: usb@38200000 {
-				compatible = "snps,dwc3";
-				reg = <0x38200000 0x10000>;
-				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
-					 <&clk IMX8MP_CLK_USB_CORE_REF>,
-					 <&clk IMX8MP_CLK_USB_SUSP>;
-				clock-names = "bus_early", "ref", "suspend";
-				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
-				phys = <&usb3_phy1>, <&usb3_phy1>;
-				phy-names = "usb2-phy", "usb3-phy";
-				snps,gfladj-refclk-lpm-sel-quirk;
-				snps,parkmode-disable-ss-quirk;
-			};
-		};
-
 		dsp: dsp@3b6e8000 {
 			compatible = "fsl,imx8mp-hifi4";
 			reg = <0x3b6e8000 0x88000>;
-- 
2.34.1

[PATCH 2/4] arm64: dts: imx95: switch usb3 controller to flattened model

[Xu Yang]

Switch to use flattened model for USB3 controller. To enable USB
controller with restricted DMA access range to work correctly, add a
pseudo simple-bus to constrain the dma address.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx95.dtsi | 48 ++++++++++++------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
index 71394871d8dd..91048501a692 100644
--- a/arch/arm64/boot/dts/freescale/imx95.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
@@ -1772,45 +1772,45 @@ smmu: iommu@490d0000 {
 			};
 		};
 
-		usb3: usb@4c010010 {
-			compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";
-			reg = <0x0 0x4c010010 0x0 0x04>,
-			      <0x0 0x4c1f0000 0x0 0x20>;
-			clocks = <&scmi_clk IMX95_CLK_HSIO>,
-				 <&scmi_clk IMX95_CLK_32K>;
-			clock-names = "hsio", "suspend";
-			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+		hsio_blk_ctl: syscon@4c0100c0 {
+			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
+			reg = <0x0 0x4c0100c0 0x0 0x1>;
+			#clock-cells = <1>;
+			clocks = <&clk_sys100m>;
+			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
+		};
+
+		bus@4c100000 {
+			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;
-			ranges;
-			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
 			dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
-			status = "disabled";
+			ranges;
 
-			usb3_dwc3: usb@4c100000 {
-				compatible = "snps,dwc3";
-				reg = <0x0 0x4c100000 0x0 0x10000>;
+			usb3: usb3_dwc3: usb@4c100000 {
+				compatible = "nxp,imx8mp-dwc3";
+				reg = <0x0 0x4c100000 0x0 0x10000>,
+				      <0x0 0x4c010010 0x0 0x04>,
+				      <0x0 0x4c1f0000 0x0 0x20>;
+				reg-names = "core", "blkctl", "glue";
 				clocks = <&scmi_clk IMX95_CLK_HSIO>,
+					 <&scmi_clk IMX95_CLK_HSIO>,
 					 <&scmi_clk IMX95_CLK_24M>,
 					 <&scmi_clk IMX95_CLK_32K>;
-				clock-names = "bus_early", "ref", "suspend";
-				interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+				clock-names = "hsio", "bus_early", "ref", "suspend";
+				interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
+					     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "dwc_usb3", "wakeup";
+				power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
 				phys = <&usb3_phy>, <&usb3_phy>;
 				phy-names = "usb2-phy", "usb3-phy";
 				snps,gfladj-refclk-lpm-sel-quirk;
 				snps,parkmode-disable-ss-quirk;
 				iommus = <&smmu 0xe>;
+				status = "disabled";
 			};
 		};
 
-		hsio_blk_ctl: syscon@4c0100c0 {
-			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
-			reg = <0x0 0x4c0100c0 0x0 0x1>;
-			#clock-cells = <1>;
-			clocks = <&clk_sys100m>;
-			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
-		};
-
 		usb3_phy: phy@4c1f0040 {
 			compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";
 			reg = <0x0 0x4c1f0040 0x0 0x40>,
-- 
2.34.1

[PATCH 3/4] arm64: dts: imx8mp-evk: add typec node

[Xu Yang]

The first USB port features a Type-C connector with dual data role
and dual power role capabilities. Add the Type-C device node and
enable the corresponding USB controller node.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 67 ++++++++++++++++++++
 1 file changed, 67 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index d0a2bd975a18..1d9e9a8f5e5b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -6,6 +6,7 @@
 /dts-v1/;
 
 #include <dt-bindings/phy/phy-imx8-pcie.h>
+#include <dt-bindings/usb/pd.h>
 #include "imx8mp.dtsi"
 
 / {
@@ -636,6 +637,35 @@ adv7535_out: endpoint {
 
 		};
 	};
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110", "tcpci";
+		reg = <0x50>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+		orientation-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+
+			port {
+				typec_con_hs: endpoint {
+					remote-endpoint = <&usb3_data_hs>;
+				};
+			};
+		};
+	};
 };
 
 &i2c3 {
@@ -846,7 +876,37 @@ &uart2 {
 	status = "okay";
 };
 
+&usb3_phy0 {
+	fsl,phy-tx-vref-tune-percent = <122>;
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vboost-level-microvolt = <1156>;
+	fsl,phy-comp-dis-tune-percent = <115>;
+	fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <33>;
+	fsl,phy-pcs-tx-swing-full-percent = <100>;
+	status = "okay";
+};
+
+&usb3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	role-switch-default-mode = "peripheral";
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	status = "okay";
+
+	port {
+		usb3_data_hs: endpoint {
+			remote-endpoint = <&typec_con_hs>;
+		};
+	};
+};
+
 &usb3_phy1 {
+	fsl,phy-tx-preemp-amp-tune-microamp = <1800>;
+	fsl,phy-tx-vref-tune-percent = <116>;
 	status = "okay";
 };
 
@@ -1174,6 +1234,13 @@ MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX	0x140
 		>;
 	};
 
+	pinctrl_typec: typecgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1c4
+			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x16
+		>;
+	};
+
 	pinctrl_usb1_vbus: usb1grp {
 		fsl,pins = <
 			MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR	0x10
-- 
2.34.1

[PATCH 4/4] arm64: dts: imx8mq-evk: add typec node

[Xu Yang]

The first USB port features a Type-C connector with dual data role
and dual power role capabilities. Add the Type-C device node and
enable the corresponding USB controller node.

Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 59 ++++++++++++++++++++
 1 file changed, 59 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index d48f901487d4..1b93d80744be 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/usb/pd.h>
 #include "imx8mq.dtsi"
 
 / {
@@ -330,6 +331,35 @@ vgen6_reg: vgen6 {
 			};
 		};
 	};
+
+	ptn5110: tcpc@50 {
+		compatible = "nxp,ptn5110", "tcpci";
+		reg = <0x50>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_typec>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+		orientation-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
+
+		usb_con: connector {
+			compatible = "usb-c-connector";
+			label = "USB-C";
+			power-role = "dual";
+			data-role = "dual";
+			try-power-role = "sink";
+			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+			sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+				     PDO_VAR(5000, 20000, 3000)>;
+			op-sink-microwatt = <15000000>;
+			self-powered;
+
+			port {
+				typec_con_hs: endpoint {
+					remote-endpoint = <&usb3_data_hs>;
+				};
+			};
+		};
+	};
 };
 
 &lcdif {
@@ -488,6 +518,28 @@ &uart1 {
 	status = "okay";
 };
 
+&usb3_phy0 {
+	status = "okay";
+};
+
+&usb_dwc3_0 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	role-switch-default-mode = "peripheral";
+	snps,dis-u1-entry-quirk;
+	snps,dis-u2-entry-quirk;
+	status = "okay";
+
+	port {
+		usb3_data_hs: endpoint {
+			remote-endpoint = <&typec_con_hs>;
+		};
+	};
+};
+
 &usb3_phy1 {
 	status = "okay";
 };
@@ -640,6 +692,13 @@ MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN		0xd6
 		>;
 	};
 
+	pinctrl_typec: typecgrp {
+		fsl,pins = <
+			MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3		0x17059
+			MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15		0x16
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX		0x49
-- 
2.34.1

Re: [PATCH 1/4] arm64: dts: imx8mp: switch usb controller to flattened model

[Frank Li]

On Tue, Apr 21, 2026 at 06:55:00PM +0800, Xu Yang wrote:
> Switch to use flattened model for all USB controllers. To enable USB
> controllers with restricted DMA access range to work correctly, add a
> pseudo simple-bus to constrain the dma address.

This should not "pseudo", and bus is physical existed, which limited dma
range since it transparent to SW, which may not mention in spec.

>
> Also reorder USB-related nodes.

this need new patch to just do reorder.

>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 161 ++++++++++------------
>  1 file changed, 76 insertions(+), 85 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 90d7bb8f5619..8b3aab14ccf1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -2329,6 +2329,82 @@ gpu2d: gpu@38008000 {
>  			power-domains = <&pgc_gpu2d>;
>  		};
>
> +		bus@38100000 {
> +			compatible = "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> +			ranges;
> +
> +			usb3_0: usb_dwc3_0: usb@38100000 {
> +				compatible = "nxp,imx8mp-dwc3";
> +				reg = <0x38100000 0x10000>,
> +				      <0x32f10100 0x8>,
> +				      <0x381f0000 0x20>;
> +				reg-names = "core", "blkctl", "glue";
> +				clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +					 <&clk IMX8MP_CLK_USB_ROOT>,
> +					 <&clk IMX8MP_CLK_USB_CORE_REF>,
> +					 <&clk IMX8MP_CLK_USB_SUSP>;
> +				clock-names = "hsio", "bus_early", "ref", "suspend";
> +				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "dwc_usb3", "wakeup";
> +				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> +				phys = <&usb3_phy0>, <&usb3_phy0>;
> +				phy-names = "usb2-phy", "usb3-phy";
> +				snps,gfladj-refclk-lpm-sel-quirk;
> +				snps,parkmode-disable-ss-quirk;
> +				status = "disabled";
> +			};
> +
> +			usb3_1: usb_dwc3_1: usb@38200000 {
> +				compatible = "nxp,imx8mp-dwc3";
> +				reg = <0x38200000 0x10000>,
> +				      <0x32f10108 0x8>,
> +				      <0x382f0000 0x20>;
> +				reg-names = "core", "blkctl", "glue";
> +				clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> +					 <&clk IMX8MP_CLK_USB_ROOT>,
> +					 <&clk IMX8MP_CLK_USB_CORE_REF>,
> +					 <&clk IMX8MP_CLK_USB_SUSP>;
> +				clock-names = "hsio", "bus_early", "ref", "suspend";
> +				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "dwc_usb3", "wakeup";
> +				power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> +				phys = <&usb3_phy1>, <&usb3_phy1>;
> +				phy-names = "usb2-phy", "usb3-phy";
> +				snps,gfladj-refclk-lpm-sel-quirk;
> +				snps,parkmode-disable-ss-quirk;
> +				status = "disabled";
> +			};
> +		};
> +
> +		usb3_phy0: usb-phy@381f0040 {
> +			compatible = "fsl,imx8mp-usb-phy";
> +			reg = <0x381f0040 0x40>;
> +			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
> +			clock-names = "phy";
> +			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> +			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> +			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
> +		usb3_phy1: usb-phy@382f0040 {
> +			compatible = "fsl,imx8mp-usb-phy";
> +			reg = <0x382f0040 0x40>;
> +			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
> +			clock-names = "phy";
> +			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> +			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> +			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
> +			#phy-cells = <0>;
> +			status = "disabled";
> +		};
> +
>  		vpu_g1: video-codec@38300000 {
>  			compatible = "nxp,imx8mm-vpu-g1";
>  			reg = <0x38300000 0x10000>;
> @@ -2407,91 +2483,6 @@ ddr-pmu@3d800000 {
>  			interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>
> -		usb3_phy0: usb-phy@381f0040 {
> -			compatible = "fsl,imx8mp-usb-phy";
> -			reg = <0x381f0040 0x40>;
> -			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
> -			clock-names = "phy";
> -			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> -			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> -			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
> -		usb3_0: usb@32f10100 {
> -			compatible = "fsl,imx8mp-dwc3";

Delete these will broken back compatible. You can delete later or descript
impact judgement in commit message.

Frank

> -			reg = <0x32f10100 0x8>,
> -			      <0x381f0000 0x20>;
> -			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> -				 <&clk IMX8MP_CLK_USB_SUSP>;
> -			clock-names = "hsio", "suspend";
> -			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> -			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> -			ranges;
> -			status = "disabled";
> -
> -			usb_dwc3_0: usb@38100000 {
> -				compatible = "snps,dwc3";
> -				reg = <0x38100000 0x10000>;
> -				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> -					 <&clk IMX8MP_CLK_USB_CORE_REF>,
> -					 <&clk IMX8MP_CLK_USB_SUSP>;
> -				clock-names = "bus_early", "ref", "suspend";
> -				interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> -				phys = <&usb3_phy0>, <&usb3_phy0>;
> -				phy-names = "usb2-phy", "usb3-phy";
> -				snps,gfladj-refclk-lpm-sel-quirk;
> -				snps,parkmode-disable-ss-quirk;
> -			};
> -
> -		};
> -
> -		usb3_phy1: usb-phy@382f0040 {
> -			compatible = "fsl,imx8mp-usb-phy";
> -			reg = <0x382f0040 0x40>;
> -			clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
> -			clock-names = "phy";
> -			assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> -			assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> -			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
> -			#phy-cells = <0>;
> -			status = "disabled";
> -		};
> -
> -		usb3_1: usb@32f10108 {
> -			compatible = "fsl,imx8mp-dwc3";
> -			reg = <0x32f10108 0x8>,
> -			      <0x382f0000 0x20>;
> -			clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
> -				 <&clk IMX8MP_CLK_USB_SUSP>;
> -			clock-names = "hsio", "suspend";
> -			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> -			power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> -			ranges;
> -			status = "disabled";
> -
> -			usb_dwc3_1: usb@38200000 {
> -				compatible = "snps,dwc3";
> -				reg = <0x38200000 0x10000>;
> -				clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> -					 <&clk IMX8MP_CLK_USB_CORE_REF>,
> -					 <&clk IMX8MP_CLK_USB_SUSP>;
> -				clock-names = "bus_early", "ref", "suspend";
> -				interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> -				phys = <&usb3_phy1>, <&usb3_phy1>;
> -				phy-names = "usb2-phy", "usb3-phy";
> -				snps,gfladj-refclk-lpm-sel-quirk;
> -				snps,parkmode-disable-ss-quirk;
> -			};
> -		};
> -
>  		dsp: dsp@3b6e8000 {
>  			compatible = "fsl,imx8mp-hifi4";
>  			reg = <0x3b6e8000 0x88000>;
> --
> 2.34.1
>

Re: [PATCH 2/4] arm64: dts: imx95: switch usb3 controller to flattened model

[Frank Li]

On Tue, Apr 21, 2026 at 06:55:01PM +0800, Xu Yang wrote:
> Switch to use flattened model for USB3 controller. To enable USB
> controller with restricted DMA access range to work correctly, add a
> pseudo simple-bus to constrain the dma address.

i.mx95 should fix >4G dma space's problem. Does it impact other no-nxp
boards?

Need do break compatible judgement such as

i.MX95 is new SoC and still is heave development. The break compatible is
accepable at development early phase.

You can rephrase it.

Frank

>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx95.dtsi | 48 ++++++++++++------------
>  1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx95.dtsi b/arch/arm64/boot/dts/freescale/imx95.dtsi
> index 71394871d8dd..91048501a692 100644
> --- a/arch/arm64/boot/dts/freescale/imx95.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx95.dtsi
> @@ -1772,45 +1772,45 @@ smmu: iommu@490d0000 {
>  			};
>  		};
>
> -		usb3: usb@4c010010 {
> -			compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3";
> -			reg = <0x0 0x4c010010 0x0 0x04>,
> -			      <0x0 0x4c1f0000 0x0 0x20>;
> -			clocks = <&scmi_clk IMX95_CLK_HSIO>,
> -				 <&scmi_clk IMX95_CLK_32K>;
> -			clock-names = "hsio", "suspend";
> -			interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> +		hsio_blk_ctl: syscon@4c0100c0 {
> +			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
> +			reg = <0x0 0x4c0100c0 0x0 0x1>;
> +			#clock-cells = <1>;
> +			clocks = <&clk_sys100m>;
> +			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> +		};
> +
> +		bus@4c100000 {
> +			compatible = "simple-bus";
>  			#address-cells = <2>;
>  			#size-cells = <2>;
> -			ranges;
> -			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
>  			dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
> -			status = "disabled";
> +			ranges;
>
> -			usb3_dwc3: usb@4c100000 {
> -				compatible = "snps,dwc3";
> -				reg = <0x0 0x4c100000 0x0 0x10000>;
> +			usb3: usb3_dwc3: usb@4c100000 {
> +				compatible = "nxp,imx8mp-dwc3";
> +				reg = <0x0 0x4c100000 0x0 0x10000>,
> +				      <0x0 0x4c010010 0x0 0x04>,
> +				      <0x0 0x4c1f0000 0x0 0x20>;
> +				reg-names = "core", "blkctl", "glue";
>  				clocks = <&scmi_clk IMX95_CLK_HSIO>,
> +					 <&scmi_clk IMX95_CLK_HSIO>,
>  					 <&scmi_clk IMX95_CLK_24M>,
>  					 <&scmi_clk IMX95_CLK_32K>;
> -				clock-names = "bus_early", "ref", "suspend";
> -				interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> +				clock-names = "hsio", "bus_early", "ref", "suspend";
> +				interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
> +					     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
> +				interrupt-names = "dwc_usb3", "wakeup";
> +				power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
>  				phys = <&usb3_phy>, <&usb3_phy>;
>  				phy-names = "usb2-phy", "usb3-phy";
>  				snps,gfladj-refclk-lpm-sel-quirk;
>  				snps,parkmode-disable-ss-quirk;
>  				iommus = <&smmu 0xe>;
> +				status = "disabled";
>  			};
>  		};
>
> -		hsio_blk_ctl: syscon@4c0100c0 {
> -			compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
> -			reg = <0x0 0x4c0100c0 0x0 0x1>;
> -			#clock-cells = <1>;
> -			clocks = <&clk_sys100m>;
> -			power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>;
> -		};
> -
>  		usb3_phy: phy@4c1f0040 {
>  			compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy";
>  			reg = <0x0 0x4c1f0040 0x0 0x40>,
> --
> 2.34.1
>

Re: [PATCH 1/4] arm64: dts: imx8mp: switch usb controller to flattened model

[Xu Yang]

On Tue, Apr 21, 2026 at 11:45:32PM -0400, Frank Li wrote:
> On Tue, Apr 21, 2026 at 06:55:00PM +0800, Xu Yang wrote:
> > Switch to use flattened model for all USB controllers. To enable USB
> > controllers with restricted DMA access range to work correctly, add a
> > pseudo simple-bus to constrain the dma address.
> 
> This should not "pseudo", and bus is physical existed, which limited dma
> range since it transparent to SW, which may not mention in spec.

OK. Will remove the word "pseudo" in v2.

> 
> >
> > Also reorder USB-related nodes.
> 
> this need new patch to just do reorder.

OK. Will add a separate patch.

Thanks,
Xu Yang

Re: [PATCH 2/4] arm64: dts: imx95: switch usb3 controller to flattened model

[Xu Yang]

On Tue, Apr 21, 2026 at 11:53:12PM -0400, Frank Li wrote:
> On Tue, Apr 21, 2026 at 06:55:01PM +0800, Xu Yang wrote:
> > Switch to use flattened model for USB3 controller. To enable USB
> > controller with restricted DMA access range to work correctly, add a
> > pseudo simple-bus to constrain the dma address.
> 
> i.mx95 should fix >4G dma space's problem. Does it impact other no-nxp
> boards?

Yes, i.MX95 has fixed >3G address DMA access problem.

It's another issue. HSIO domain only support 36 bit bus access. If not use smmu,
no any issue. If use smmu, it will allocate memory space of 36 bit < iova < 48bit.
HSIO can't handle this case.

> 
> Need do break compatible judgement such as
> 
> i.MX95 is new SoC and still is heave development. The break compatible is
> accepable at development early phase.
> 
> You can rephrase it.

OK.

Thanks,
Xu Yang

RE: [PATCH 2/4] arm64: dts: imx95: switch usb3 controller to flattened model

[Peng Fan]

> Subject: Re: [PATCH 2/4] arm64: dts: imx95: switch usb3 controller to
> flattened model
> 
> On Tue, Apr 21, 2026 at 11:53:12PM -0400, Frank Li wrote:
> > On Tue, Apr 21, 2026 at 06:55:01PM +0800, Xu Yang wrote:
> > > Switch to use flattened model for USB3 controller. To enable USB
> > > controller with restricted DMA access range to work correctly, add
> a
> > > pseudo simple-bus to constrain the dma address.
> >
> > i.mx95 should fix >4G dma space's problem. Does it impact other no-
> nxp
> > boards?
> 
> Yes, i.MX95 has fixed >3G address DMA access problem.
> 
> It's another issue. HSIO domain only support 36 bit bus access. If not
> use smmu, no any issue. If use smmu, it will allocate memory space of
> 36 bit < iova < 48bit.
> HSIO can't handle this case.

If using smmu, iova will be in range {36bit, 48bit}? How?

Thanks
Peng

> 
> >
> > Need do break compatible judgement such as
> >
> > i.MX95 is new SoC and still is heave development. The break
> compatible
> > is accepable at development early phase.
> >
> > You can rephrase it.
> 
> OK.
> 
> Thanks,
> Xu Yang

Re: [PATCH 2/4] arm64: dts: imx95: switch usb3 controller to flattened model

[Xu Yang]

On Thu, Apr 23, 2026 at 12:07:42PM +0000, Peng Fan wrote:
> > Subject: Re: [PATCH 2/4] arm64: dts: imx95: switch usb3 controller to
> > flattened model
> > 
> > On Tue, Apr 21, 2026 at 11:53:12PM -0400, Frank Li wrote:
> > > On Tue, Apr 21, 2026 at 06:55:01PM +0800, Xu Yang wrote:
> > > > Switch to use flattened model for USB3 controller. To enable USB
> > > > controller with restricted DMA access range to work correctly, add
> > a
> > > > pseudo simple-bus to constrain the dma address.
> > >
> > > i.mx95 should fix >4G dma space's problem. Does it impact other no-
> > nxp
> > > boards?
> > 
> > Yes, i.MX95 has fixed >3G address DMA access problem.
> > 
> > It's another issue. HSIO domain only support 36 bit bus access. If not
> > use smmu, no any issue. If use smmu, it will allocate memory space of
> > 36 bit < iova < 48bit.
> > HSIO can't handle this case.
> 
> If using smmu, iova will be in range {36bit, 48bit}? How?

Yes, if use smmu and not set dma-range:

[    3.139529] dwc3 4c100000.usb: dwc3_alloc_one_event_buffer evt->dma:0x0000fffffffff000 len:4096

if use smmu and set dma-range:

[    3.136849] dwc3 4c100000.usb: dwc3_alloc_one_event_buffer evt->dma:0x0000000ffffff000 len:4096

Thanks,
Xu Yang