From: Joey Gouly <joey.gouly@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oupton@kernel.org>,
Zenghui Yu <yuzenghui@huawei.com>,
Sascha Bischoff <sascha.bischoff@arm.com>
Subject: Re: [PATCH 06/18] KVM: arm64: vgic: Consolidate vgic_allocate_private_irqs_locked()
Date: Tue, 21 Apr 2026 16:22:07 +0100 [thread overview]
Message-ID: <20260421152207.GA3862683@e124191.cambridge.arm.com> (raw)
In-Reply-To: <20260415115559.2227718-7-maz@kernel.org>
On Wed, Apr 15, 2026 at 12:55:47PM +0100, Marc Zyngier wrote:
> vgic_allocate_private_irqs_locked() calls two helpers, oddly named
> vgic_{,v5_}allocate_private_irq().
>
> Not only these helpers don't allocate anything, but they also
> contain duplicate init code that would be better placed in the
> caller.
>
> Consolidate the common init code in the caller, rename the helpers
> to vgic_{,v5_}setup_private_irq(), and pass the irq pointer around
> instead of the index of the interrupt.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/kvm/vgic/vgic-init.c | 45 +++++++++++++--------------------
> 1 file changed, 18 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
> index 933983bb20052..907057881b26a 100644
> --- a/arch/arm64/kvm/vgic/vgic-init.c
> +++ b/arch/arm64/kvm/vgic/vgic-init.c
> @@ -271,18 +271,12 @@ int kvm_vgic_vcpu_nv_init(struct kvm_vcpu *vcpu)
> return ret;
> }
>
> -static void vgic_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type)
> +static void vgic_setup_private_irq(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
> + u32 type)
> {
> - struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i];
> + irq->intid = irq - &vcpu->arch.vgic_cpu.private_irqs[0];
These are allocated in one block with kzalloc_objs(), so this pointer offsetting is fine!
>
> - INIT_LIST_HEAD(&irq->ap_list);
> - raw_spin_lock_init(&irq->irq_lock);
> - irq->vcpu = NULL;
> - irq->target_vcpu = vcpu;
> - refcount_set(&irq->refcount, 0);
> -
> - irq->intid = i;
> - if (vgic_irq_is_sgi(i)) {
> + if (vgic_irq_is_sgi(irq->intid)) {
> /* SGIs */
> irq->enabled = 1;
> irq->config = VGIC_CONFIG_EDGE;
> @@ -303,18 +297,11 @@ static void vgic_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type)
> }
> }
>
> -static void vgic_v5_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type)
> +static void vgic_v5_setup_private_irq(struct kvm_vcpu *vcpu, struct vgic_irq *irq)
> {
> - struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i];
> - u32 intid = vgic_v5_make_ppi(i);
> -
> - INIT_LIST_HEAD(&irq->ap_list);
> - raw_spin_lock_init(&irq->irq_lock);
> - irq->vcpu = NULL;
> - irq->target_vcpu = vcpu;
> - refcount_set(&irq->refcount, 0);
> + int i = irq - &vcpu->arch.vgic_cpu.private_irqs[0];
>
> - irq->intid = intid;
> + irq->intid = vgic_v5_make_ppi(i);
>
> /* The only Edge architected PPI is the SW_PPI */
> if (i == GICV5_ARCH_PPI_SW_PPI)
> @@ -323,7 +310,7 @@ static void vgic_v5_allocate_private_irq(struct kvm_vcpu *vcpu, int i, u32 type)
> irq->config = VGIC_CONFIG_LEVEL;
>
> /* Register the GICv5-specific PPI ops */
> - vgic_v5_set_ppi_ops(vcpu, intid);
> + vgic_v5_set_ppi_ops(vcpu, irq->intid);
> }
>
> static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type)
> @@ -349,15 +336,19 @@ static int vgic_allocate_private_irqs_locked(struct kvm_vcpu *vcpu, u32 type)
> if (!vgic_cpu->private_irqs)
> return -ENOMEM;
>
> - /*
> - * Enable and configure all SGIs to be edge-triggered and
> - * configure all PPIs as level-triggered.
> - */
> for (i = 0; i < num_private_irqs; i++) {
> + struct vgic_irq *irq = &vcpu->arch.vgic_cpu.private_irqs[i];
> +
> + INIT_LIST_HEAD(&irq->ap_list);
> + raw_spin_lock_init(&irq->irq_lock);
> + irq->vcpu = NULL;
> + irq->target_vcpu = vcpu;
> + refcount_set(&irq->refcount, 0);
> +
> if (vgic_is_v5(vcpu->kvm))
> - vgic_v5_allocate_private_irq(vcpu, i, type);
> + vgic_v5_setup_private_irq(vcpu, irq);
> else
> - vgic_allocate_private_irq(vcpu, i, type);
> + vgic_setup_private_irq(vcpu, irq, type);
> }
>
> return 0;
Reviewed-by: Joey Gouly <joey.gouly@arm.com>
Thanks,
Joey
next prev parent reply other threads:[~2026-04-21 15:22 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-15 11:55 [PATCH 00/18] KVM: arm64: Second batch of vgic fixes for 7.1 Marc Zyngier
2026-04-15 11:55 ` [PATCH 01/18] KVM: arm64: vgic-v5: Add for_each_visible_v5_ppi() iterator Marc Zyngier
2026-04-15 11:55 ` [PATCH 02/18] KVM: arm64: vgic-v5: Move PPI caps into kvm_vgic_global_state Marc Zyngier
2026-04-15 11:55 ` [PATCH 03/18] KVM: arm64: vgic-v5: Remove use of __assign_bit() with a constant Marc Zyngier
2026-04-15 11:55 ` [PATCH 04/18] KVM: arm64: vgic-v5: Drop pointless ARM64_HAS_GICV5_CPUIF check Marc Zyngier
2026-04-15 11:55 ` [PATCH 05/18] KVM: arm64: vgic: Constify struct irq_ops usage Marc Zyngier
2026-04-21 15:54 ` Joey Gouly
2026-04-15 11:55 ` [PATCH 06/18] KVM: arm64: vgic: Consolidate vgic_allocate_private_irqs_locked() Marc Zyngier
2026-04-21 15:22 ` Joey Gouly [this message]
2026-04-15 11:55 ` [PATCH 07/18] KVM: arm64: vgic-v5: Drop defensive checks from vgic_v5_ppi_queue_irq_unlock() Marc Zyngier
2026-04-15 11:55 ` [PATCH 08/18] KVM: arm64: vgic: Rationalise per-CPU irq accessor Marc Zyngier
2026-04-17 15:21 ` Joey Gouly
2026-04-15 11:55 ` [PATCH 09/18] KVM: arm64: vgic-v5: Limit support to 64 PPIs Marc Zyngier
2026-04-17 16:10 ` Joey Gouly
2026-04-15 11:55 ` [PATCH 10/18] KVM: arm64: vgic-v5: Add missing trap handing for NV triage Marc Zyngier
2026-04-15 11:55 ` [PATCH 11/18] KVM: arm64: vgic-v5: Atomically assign bits to PPI DVI bitmap Marc Zyngier
2026-04-15 11:55 ` [PATCH 12/18] KVM: arm64: selftests: Add missing GIC CDEN to no-vgic-v5 selftest Marc Zyngier
2026-04-21 16:02 ` Joey Gouly
2026-04-15 11:55 ` [PATCH 13/18] KVM: arm64: selftests: Cleanup unused vars in GICv5 PPI selftest Marc Zyngier
2026-04-15 11:55 ` [PATCH 14/18] KVM: arm64: selftests: Improve error handling for " Marc Zyngier
2026-04-15 11:55 ` [PATCH 15/18] Documentation: KVM: Fix typos in VGICv5 documentation Marc Zyngier
2026-04-17 15:29 ` Joey Gouly
2026-04-15 11:55 ` [PATCH 16/18] Documentation: KVM: Clarify that PMU_V3_IRQ IntID requirements for GICv5 Marc Zyngier
2026-04-15 11:55 ` [PATCH 17/18] irqchip/gic-v5: Immediately exec priority drop following activate Marc Zyngier
2026-04-15 11:55 ` [PATCH 18/18] KVM: arm64: Fix arch timer interrupts for GICv3-on-GICv5 guests Marc Zyngier
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