From: Jason Gunthorpe <jgg@ziepe.ca>
To: Will Deacon <will@kernel.org>
Cc: Evangelos Petrongonas <epetron@amazon.de>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>,
Nicolin Chen <nicolinc@nvidia.com>,
Pranjal Shrivastava <praan@google.com>,
Lu Baolu <baolu.lu@linux.intel.com>,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, nh-open-source@amazon.com,
Zeev Zilberman <zeev@amazon.com>
Subject: Re: [PATCH] iommu/arm-smmu-v3: Allow disabling Stage 1 translation
Date: Thu, 23 Apr 2026 19:37:16 -0300 [thread overview]
Message-ID: <20260423223716.GS3611611@ziepe.ca> (raw)
In-Reply-To: <aepRy7Gp7Ng85Zr7@willie-the-truck>
On Thu, Apr 23, 2026 at 06:07:23PM +0100, Will Deacon wrote:
> I don't think it's that odd given that the STE/CD entries are bigger
> than PTEs and the SMMU permits a lot more relaxations about how they are
> accessed and cached compared to the PTW.
Well I'm not sure bigger really matters, but I wasn't aware there was
a spec relaxation here that would make the cachable path not viable
for STE but not PTW...
> Having said that, the page-table code looks broken to me even in the
> coherent case:
>
> ptep[i] = pte | paddr_to_iopte(paddr + i * sz, data);
>
> as the compiler can theoretically make a right mess of that.
Heh, great. The iommupt stuff does better.. It does a 64 bit cmpxchg
to store a table pointer and a 64 bit WRITE_ONCE to store the pte,
then a CMO through the DMA API.
DMA API has to guarentee the right ordering, so we only have the
question below:
> > STE/CD is pretty simple now, there is only one place to put the CMO
> > and the ordering is all handled with that shared code. We no longer
> > care about ordering beyond all the writes must be visible to HW before
> > issuing the CMDQ invalidation command - which is the same environment
> > as the pagetable.
>
> You presumably rely on 64-bit single-copy atomicity for hitless updates,
> no?
Yes, just like the page table does..
I hope that's not a problem or we have a issue with the PTW :)
> > I also don't like this "lot of systems thing". I don't want these
> > powerful capabilities locked up in some giant CSP's proprietary
> > kernel. I want all the companies in the cloud market to have access
> > to the same feature set. That's what open source is supposed to be
> > driving toward. I have several interesting use cases for this
> > functionality already.
>
> Sorry, the point here was definitely _not_ about keeping this out of
> tree, nor was I trying to say that this stuff isn't important. But the
> mobile world doesn't give a hoot about KHO and _does_ tend to care about
> the impact of CMO, so we have to find a way to balance the two worlds.
Yes, that make sense.
My argument is that the CMO on STE/CD shouldn't bother mobile, you
could even view it as an micro-optimization because we do occasionally
read-back the STE/CD fields.
But if you say the SMM STE/CD fetch doesn't have to follow the single
copy rules and PTW does, then ok..
And if Samiullah can tackle dma_alloc_coherent then maybe the whole
question is moot.
Jason
next prev parent reply other threads:[~2026-04-23 22:37 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 12:32 [PATCH] iommu/arm-smmu-v3: Allow disabling Stage 1 translation Evangelos Petrongonas
2026-04-20 12:40 ` Jason Gunthorpe
2026-04-22 6:44 ` Evangelos Petrongonas
2026-04-22 15:44 ` Pranjal Shrivastava
2026-04-22 16:23 ` Jason Gunthorpe
2026-04-22 16:36 ` Robin Murphy
2026-04-23 9:44 ` Will Deacon
2026-04-23 9:47 ` Will Deacon
2026-04-23 14:23 ` Jason Gunthorpe
2026-04-23 17:07 ` Will Deacon
2026-04-23 18:43 ` Samiullah Khawaja
2026-04-23 22:37 ` Jason Gunthorpe [this message]
2026-04-24 15:16 ` Will Deacon
2026-04-24 15:42 ` Jason Gunthorpe
2026-04-24 16:01 ` Will Deacon
2026-04-24 16:39 ` Jason Gunthorpe
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