* [PATCH 00/15] MT8189: Add support for system and base clock controllers
@ 2026-07-01 13:11 Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 01/15] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
` (14 more replies)
0 siblings, 15 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud, Irving-CH Lin
This series is a continuation by AngeloGioacchino Del Regno and I of a
previous series ([1]), that adds the clock controller support for
the Mediatek MT8189 SoC and its variants (MT8371, MT8391).
The first major changes is the split of the series in two:
- one for all basic clock controllers including system ones (this
series)
- one for the multimedia and graphics related clock controllers (to be
send in the future)
We chose to separate the multimedia clock drivers from the base system
ones, as there is currently an unsolvable inter-dependency between the
power domains and multimedia clocks; the power domains need a
dual-stage bring-up, where only a part of the multimedia clocks are
accessible in the first power domain powerup stage, and the rest when
the second stage (SRAM enablement) is done.
The current workarounds for this issue, such as removing the is_enabled
operation from the impacted clock controllers clk_ops table or
let the multimedia power domain always on, were quickly discarded
for upstream.
The second major change is the dt-bindings patch that got heavily
reworked, not only because of the split choice. We took the opportunity
to regroup in the MT8186 clock and system clock dt-bindings the
description of several other Mediatek SoC (MT8188, MT8192 and MT8195)
and add in them the MT8189 new ones.
The rationale is to ease maintainability and have common files for
several currently supported SoC or new future ones, that have the same
kind of clock controller design.
Finally the pending remarks from peer reviews on the v6 revision of [1]
were also taken into account and new fixes and cleanups were also
added.
A more detailed changelog between [1] and this series:
- Removed multimedia and graphics related clock controllers code and
definitions from series
- Added new dt-bindings patches to factorise existing MT8188, MT8192
and MT8195 in MT8186 clock dt-bindings
- Heavily modified the MT8189 dt-bindings to add new compatibles
in MT8186 clock dt-bindings
- Created a new dt-bindings include for the MT8189 reset controller
definitions (include/dt-bindings/reset/mediatek,mt8189-resets.h)
- Removed unnecessary `syscon` compatible fallback from MT8189 base
clock controllers
- Added missing 'mediatek,mt8189-fhctl' compatible declaration in
dt-bindings
- Modified Kconfig to COMMON_CLK_MT8189 be tristate (and not bool) to
allow all MT8189 clock controller drivers to be built as modules (it
was partial)
- Fix pll unregisters in clk_mt8189_apmixed_probe error case
- Reparent several clocks to correct 26M references in clk-mt8189-bus.c,
clk-mt8189-topckgen.c and clk-mt8189-vlpckgen.c
- Removed CLK_SET_RATE_NO_REPARENT flag from mfg_sel_mfgpll
- Rename TOPCKGEN_fmipi_csi_up26m clock to fmipi_csi_up26m to remove caps usage
- Implemented reset controllers in clk-mt8189-ufs.c
- Updated all file headers to update copyrights and add all authors
- Added all co-developed-by trailers
The series is based on linux-next tree (tag: next-20260630) and has
been tested on Mediatek Genio 520-EVK (MT8371) and 720-EVK (MT8391) boards
with board hardware enablement patch series (new series revision for
those boards to be sent soon after this one).
[1]: https://lore.kernel.org/linux-mediatek/20260309120512.3624804-1-irving-ch.lin@mediatek.com/
[2]: https://lore.kernel.org/linux-mediatek/20260309120512.3624804-2-irving-ch.lin@mediatek.com/
---
Louis-Alexis Eyraud (15):
dt-bindings: clock: mediatek: reorder MT8186 compatibles
dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186
dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186
dt-bindings: clock: mediatek: regroup MT8195 dt-bindings into MT8186
dt-bindings: clock: mediatek: Add MT8189 clocks
clk: mediatek: Add MT8189 apmixedsys clock support
clk: mediatek: Add MT8189 topckgen clock support
clk: mediatek: Add MT8189 vlpckgen clock support
clk: mediatek: Add MT8189 vlpcfg clock support
clk: mediatek: Add MT8189 bus clock support
clk: mediatek: Add MT8189 dbgao clock support
clk: mediatek: Add MT8189 dvfsrc clock support
clk: mediatek: Add MT8189 i2c clock support
clk: mediatek: Add MT8189 scp clock support
clk: mediatek: Add MT8189 ufs clock support
.../bindings/clock/mediatek,mt8186-clock.yaml | 171 +++-
.../bindings/clock/mediatek,mt8186-fhctl.yaml | 1 +
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 42 +-
.../bindings/clock/mediatek,mt8188-clock.yaml | 93 --
.../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 --
.../bindings/clock/mediatek,mt8192-clock.yaml | 191 ----
.../bindings/clock/mediatek,mt8192-sys-clock.yaml | 68 --
.../bindings/clock/mediatek,mt8195-clock.yaml | 238 -----
.../bindings/clock/mediatek,mt8195-sys-clock.yaml | 76 --
drivers/clk/mediatek/Kconfig | 79 ++
drivers/clk/mediatek/Makefile | 8 +
drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 196 ++++
drivers/clk/mediatek/clk-mt8189-bus.c | 200 ++++
drivers/clk/mediatek/clk-mt8189-dbgao.c | 98 ++
drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 58 ++
drivers/clk/mediatek/clk-mt8189-iic.c | 122 +++
drivers/clk/mediatek/clk-mt8189-scp.c | 77 ++
drivers/clk/mediatek/clk-mt8189-topckgen.c | 1024 ++++++++++++++++++++
drivers/clk/mediatek/clk-mt8189-ufs.c | 133 +++
drivers/clk/mediatek/clk-mt8189-vlpcfg.c | 115 +++
drivers/clk/mediatek/clk-mt8189-vlpckgen.c | 284 ++++++
include/dt-bindings/clock/mediatek,mt8189-clk.h | 433 +++++++++
include/dt-bindings/reset/mediatek,mt8189-resets.h | 17 +
23 files changed, 3046 insertions(+), 736 deletions(-)
---
base-commit: ba7c57499e5999aeae8dd4f954eb2600589d80aa
change-id: 20260630-mt8189-clocks-system-base-70714e4ff2aa
Best regards,
--
Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 01/15] dt-bindings: clock: mediatek: reorder MT8186 compatibles
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
` (13 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
In order to prepare regrouping several Mediatek SoC clock controller
dt-bindings files into the MT8186 ones, reorder the MT8186 clock
controller compatibles so they are sorted alphanumerically.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 17 +++++++++--------
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 ++--
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index f4e58bfa504f..37e1d7487ab4 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -23,18 +23,19 @@ properties:
compatible:
items:
- enum:
- - mediatek,mt8186-imp_iic_wrap
- - mediatek,mt8186-mfgsys
- - mediatek,mt8186-wpesys
- - mediatek,mt8186-imgsys1
- - mediatek,mt8186-imgsys2
- - mediatek,mt8186-vdecsys
- - mediatek,mt8186-vencsys
- mediatek,mt8186-camsys
- mediatek,mt8186-camsys_rawa
- mediatek,mt8186-camsys_rawb
- - mediatek,mt8186-mdpsys
+ - mediatek,mt8186-imgsys1
+ - mediatek,mt8186-imgsys2
+ - mediatek,mt8186-imp_iic_wrap
- mediatek,mt8186-ipesys
+ - mediatek,mt8186-mdpsys
+ - mediatek,mt8186-mfgsys
+ - mediatek,mt8186-vdecsys
+ - mediatek,mt8186-vencsys
+ - mediatek,mt8186-wpesys
+
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index 1c446fbc5108..c857a40ca2f0 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -27,10 +27,10 @@ properties:
compatible:
items:
- enum:
+ - mediatek,mt8186-apmixedsys
+ - mediatek,mt8186-infracfg_ao
- mediatek,mt8186-mcusys
- mediatek,mt8186-topckgen
- - mediatek,mt8186-infracfg_ao
- - mediatek,mt8186-apmixedsys
- const: syscon
reg:
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 01/15] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 16:24 ` Rob Herring (Arm)
2026-07-01 19:33 ` Rob Herring
2026-07-01 13:11 ` [PATCH 03/15] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
` (12 subsequent siblings)
14 siblings, 2 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
Regroup the MT8188 clock and system clock dt-bindings into MT8186 ones
to ease maintainability and have common files for several currently
supported SoC or new future ones, that have the same kind of clock
controller design.
Note:
The `#clock-cells` property is a required property for all compatibles
declared in MT8188 clock and system clock dt-bindings but not in MT8186
ones.
To avoid ABI breakage, conditional blocks to check this requirement
for MT8188 compatibles are added, rather than enforcing it for MT8186
compatibles.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 82 ++++++++++++++++++-
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 20 ++++-
.../bindings/clock/mediatek,mt8188-clock.yaml | 93 ----------------------
.../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 --------------
4 files changed, 100 insertions(+), 153 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 37e1d7487ab4..28e05b5fb23b 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: MediaTek Functional Clock Controller for MT8186
+title: MediaTek Functional Clock Controller for Mediatek SoCs
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
@@ -35,6 +35,30 @@ properties:
- mediatek,mt8186-vdecsys
- mediatek,mt8186-vencsys
- mediatek,mt8186-wpesys
+ - mediatek,mt8188-adsp-audio26m
+ - mediatek,mt8188-camsys
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-ccusys
+ - mediatek,mt8188-imgsys
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-imp-iic-wrap-c
+ - mediatek,mt8188-imp-iic-wrap-en
+ - mediatek,mt8188-imp-iic-wrap-w
+ - mediatek,mt8188-ipesys
+ - mediatek,mt8188-mfgcfg
+ - mediatek,mt8188-vdecsys
+ - mediatek,mt8188-vdecsys-soc
+ - mediatek,mt8188-vencsys
+ - mediatek,mt8188-wpesys
+ - mediatek,mt8188-wpesys-vpp0
+
reg:
maxItems: 1
@@ -42,10 +66,66 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-adsp-audio26m
+ - mediatek,mt8188-camsys
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-ccusys
+ - mediatek,mt8188-imgsys
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-imp-iic-wrap-c
+ - mediatek,mt8188-imp-iic-wrap-en
+ - mediatek,mt8188-imp-iic-wrap-w
+ - mediatek,mt8188-ipesys
+ - mediatek,mt8188-mfgcfg
+ - mediatek,mt8188-vdecsys
+ - mediatek,mt8188-vdecsys-soc
+ - mediatek,mt8188-vencsys
+ - mediatek,mt8188-wpesys
+ - mediatek,mt8188-wpesys-vpp0
+ then:
+ required:
+ - '#clock-cells'
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-ipesys
+ then:
+ required:
+ - '#reset-cells'
+ else:
+ properties:
+ reset-cells: false
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index c857a40ca2f0..edf9562ca8b9 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: MediaTek System Clock Controller for MT8186
+title: MediaTek System Clock Controller for Mediatek SoCs
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
@@ -31,6 +31,10 @@ properties:
- mediatek,mt8186-infracfg_ao
- mediatek,mt8186-mcusys
- mediatek,mt8186-topckgen
+ - mediatek,mt8188-apmixedsys
+ - mediatek,mt8188-infracfg-ao
+ - mediatek,mt8188-pericfg-ao
+ - mediatek,mt8188-topckgen
- const: syscon
reg:
@@ -46,6 +50,20 @@ required:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8188-apmixedsys
+ - mediatek,mt8188-infracfg-ao
+ - mediatek,mt8188-pericfg-ao
+ - mediatek,mt8188-topckgen
+ then:
+ required:
+ - '#clock-cells'
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
deleted file mode 100644
index 5403242545ab..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
+++ /dev/null
@@ -1,93 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek Functional Clock Controller for MT8188
-
-maintainers:
- - Garmin Chang <garmin.chang@mediatek.com>
-
-description: |
- The clock architecture in MediaTek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The devices provide clock gate control in different IP blocks.
-
-properties:
- compatible:
- enum:
- - mediatek,mt8188-adsp-audio26m
- - mediatek,mt8188-camsys
- - mediatek,mt8188-camsys-rawa
- - mediatek,mt8188-camsys-rawb
- - mediatek,mt8188-camsys-yuva
- - mediatek,mt8188-camsys-yuvb
- - mediatek,mt8188-ccusys
- - mediatek,mt8188-imgsys
- - mediatek,mt8188-imgsys-wpe1
- - mediatek,mt8188-imgsys-wpe2
- - mediatek,mt8188-imgsys-wpe3
- - mediatek,mt8188-imgsys1-dip-nr
- - mediatek,mt8188-imgsys1-dip-top
- - mediatek,mt8188-imp-iic-wrap-c
- - mediatek,mt8188-imp-iic-wrap-en
- - mediatek,mt8188-imp-iic-wrap-w
- - mediatek,mt8188-ipesys
- - mediatek,mt8188-mfgcfg
- - mediatek,mt8188-vdecsys
- - mediatek,mt8188-vdecsys-soc
- - mediatek,mt8188-vencsys
- - mediatek,mt8188-wpesys
- - mediatek,mt8188-wpesys-vpp0
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
- - '#clock-cells'
-
-allOf:
- - if:
- properties:
- compatible:
- contains:
- enum:
- - mediatek,mt8188-camsys-rawa
- - mediatek,mt8188-camsys-rawb
- - mediatek,mt8188-camsys-yuva
- - mediatek,mt8188-camsys-yuvb
- - mediatek,mt8188-imgsys-wpe1
- - mediatek,mt8188-imgsys-wpe2
- - mediatek,mt8188-imgsys-wpe3
- - mediatek,mt8188-imgsys1-dip-nr
- - mediatek,mt8188-imgsys1-dip-top
- - mediatek,mt8188-ipesys
-
- then:
- required:
- - '#reset-cells'
-
-additionalProperties: false
-
-examples:
- - |
- clock-controller@11283000 {
- compatible = "mediatek,mt8188-imp-iic-wrap-c";
- reg = <0x11283000 0x1000>;
- #clock-cells = <1>;
- };
-
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
deleted file mode 100644
index db13d51a4903..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
+++ /dev/null
@@ -1,58 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek System Clock Controller for MT8188
-
-maintainers:
- - Garmin Chang <garmin.chang@mediatek.com>
-
-description: |
- The clock architecture in MediaTek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The apmixedsys provides most of PLLs which generated from SoC 26m.
- The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
- The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
- The mcusys provides mux control to select the clock source in AP MCU.
- The device nodes also provide the system control capacity for configuration.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8188-apmixedsys
- - mediatek,mt8188-infracfg-ao
- - mediatek,mt8188-pericfg-ao
- - mediatek,mt8188-topckgen
- - const: syscon
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
- - '#clock-cells'
-
-additionalProperties: false
-
-examples:
- - |
- clock-controller@10000000 {
- compatible = "mediatek,mt8188-topckgen", "syscon";
- reg = <0x10000000 0x1000>;
- #clock-cells = <1>;
- };
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 03/15] dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 01/15] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 04/15] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
` (11 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
Regroup the MT8192 clock and system clock dt-bindings into MT8186 ones
to ease maintainability and have common files for several currently
supported SoC or new future ones, that have the same kind of clock
controller design.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 21 ++-
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 +
.../bindings/clock/mediatek,mt8192-clock.yaml | 191 ---------------------
.../bindings/clock/mediatek,mt8192-sys-clock.yaml | 68 --------
4 files changed, 24 insertions(+), 260 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 28e05b5fb23b..3b543c810f18 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -58,7 +58,26 @@ properties:
- mediatek,mt8188-vencsys
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
-
+ - mediatek,mt8192-camsys
+ - mediatek,mt8192-camsys_rawa
+ - mediatek,mt8192-camsys_rawb
+ - mediatek,mt8192-camsys_rawc
+ - mediatek,mt8192-imgsys
+ - mediatek,mt8192-imgsys2
+ - mediatek,mt8192-imp_iic_wrap_c
+ - mediatek,mt8192-imp_iic_wrap_e
+ - mediatek,mt8192-imp_iic_wrap_s
+ - mediatek,mt8192-imp_iic_wrap_ws
+ - mediatek,mt8192-imp_iic_wrap_w
+ - mediatek,mt8192-imp_iic_wrap_n
+ - mediatek,mt8192-ipesys
+ - mediatek,mt8192-mdpsys
+ - mediatek,mt8192-mfgcfg
+ - mediatek,mt8192-msdc_top
+ - mediatek,mt8192-scp_adsp
+ - mediatek,mt8192-vdecsys_soc
+ - mediatek,mt8192-vdecsys
+ - mediatek,mt8192-vencsys
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index edf9562ca8b9..4500842b20de 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -35,6 +35,10 @@ properties:
- mediatek,mt8188-infracfg-ao
- mediatek,mt8188-pericfg-ao
- mediatek,mt8188-topckgen
+ - mediatek,mt8192-apmixedsys
+ - mediatek,mt8192-infracfg
+ - mediatek,mt8192-pericfg
+ - mediatek,mt8192-topckgen
- const: syscon
reg:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml
deleted file mode 100644
index b8d690e28bdc..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml
+++ /dev/null
@@ -1,191 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek Functional Clock Controller for MT8192
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The Mediatek functional clock controller provides various clocks on MT8192.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8192-scp_adsp
- - mediatek,mt8192-imp_iic_wrap_c
- - mediatek,mt8192-imp_iic_wrap_e
- - mediatek,mt8192-imp_iic_wrap_s
- - mediatek,mt8192-imp_iic_wrap_ws
- - mediatek,mt8192-imp_iic_wrap_w
- - mediatek,mt8192-imp_iic_wrap_n
- - mediatek,mt8192-msdc_top
- - mediatek,mt8192-mfgcfg
- - mediatek,mt8192-imgsys
- - mediatek,mt8192-imgsys2
- - mediatek,mt8192-vdecsys_soc
- - mediatek,mt8192-vdecsys
- - mediatek,mt8192-vencsys
- - mediatek,mt8192-camsys
- - mediatek,mt8192-camsys_rawa
- - mediatek,mt8192-camsys_rawb
- - mediatek,mt8192-camsys_rawc
- - mediatek,mt8192-ipesys
- - mediatek,mt8192-mdpsys
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- scp_adsp: clock-controller@10720000 {
- compatible = "mediatek,mt8192-scp_adsp";
- reg = <0x10720000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_c: clock-controller@11007000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_c";
- reg = <0x11007000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_e: clock-controller@11cb1000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_e";
- reg = <0x11cb1000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_s: clock-controller@11d03000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_s";
- reg = <0x11d03000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_ws: clock-controller@11d23000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_ws";
- reg = <0x11d23000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_w: clock-controller@11e01000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_w";
- reg = <0x11e01000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_n: clock-controller@11f02000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_n";
- reg = <0x11f02000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- msdc_top: clock-controller@11f10000 {
- compatible = "mediatek,mt8192-msdc_top";
- reg = <0x11f10000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- mfgcfg: clock-controller@13fbf000 {
- compatible = "mediatek,mt8192-mfgcfg";
- reg = <0x13fbf000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys: clock-controller@15020000 {
- compatible = "mediatek,mt8192-imgsys";
- reg = <0x15020000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys2: clock-controller@15820000 {
- compatible = "mediatek,mt8192-imgsys2";
- reg = <0x15820000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys_soc: clock-controller@1600f000 {
- compatible = "mediatek,mt8192-vdecsys_soc";
- reg = <0x1600f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys: clock-controller@1602f000 {
- compatible = "mediatek,mt8192-vdecsys";
- reg = <0x1602f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vencsys: clock-controller@17000000 {
- compatible = "mediatek,mt8192-vencsys";
- reg = <0x17000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys: clock-controller@1a000000 {
- compatible = "mediatek,mt8192-camsys";
- reg = <0x1a000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawa: clock-controller@1a04f000 {
- compatible = "mediatek,mt8192-camsys_rawa";
- reg = <0x1a04f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawb: clock-controller@1a06f000 {
- compatible = "mediatek,mt8192-camsys_rawb";
- reg = <0x1a06f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawc: clock-controller@1a08f000 {
- compatible = "mediatek,mt8192-camsys_rawc";
- reg = <0x1a08f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- ipesys: clock-controller@1b000000 {
- compatible = "mediatek,mt8192-ipesys";
- reg = <0x1b000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- mdpsys: clock-controller@1f000000 {
- compatible = "mediatek,mt8192-mdpsys";
- reg = <0x1f000000 0x1000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml
deleted file mode 100644
index bf8c9aacdf1e..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml
+++ /dev/null
@@ -1,68 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek System Clock Controller for MT8192
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The Mediatek system clock controller provides various clocks and system configuration
- like reset and bus protection on MT8192.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8192-topckgen
- - mediatek,mt8192-infracfg
- - mediatek,mt8192-pericfg
- - mediatek,mt8192-apmixedsys
- - const: syscon
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- topckgen: syscon@10000000 {
- compatible = "mediatek,mt8192-topckgen", "syscon";
- reg = <0x10000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- infracfg: syscon@10001000 {
- compatible = "mediatek,mt8192-infracfg", "syscon";
- reg = <0x10001000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- pericfg: syscon@10003000 {
- compatible = "mediatek,mt8192-pericfg", "syscon";
- reg = <0x10003000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- apmixedsys: syscon@1000c000 {
- compatible = "mediatek,mt8192-apmixedsys", "syscon";
- reg = <0x1000c000 0x1000>;
- #clock-cells = <1>;
- };
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 04/15] dt-bindings: clock: mediatek: regroup MT8195 dt-bindings into MT8186
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (2 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 03/15] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 05/15] dt-bindings: clock: mediatek: Add MT8189 clocks Louis-Alexis Eyraud
` (10 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
Regroup the MT8195 clock and system clock dt-bindings into MT8186 ones
to ease maintainability and have common files for several currently
supported SoC or new future ones, that have the same kind of clock
controller design.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 25 +++
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 +
.../bindings/clock/mediatek,mt8195-clock.yaml | 238 ---------------------
.../bindings/clock/mediatek,mt8195-sys-clock.yaml | 76 -------
4 files changed, 29 insertions(+), 314 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 3b543c810f18..84e602c7d326 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -78,6 +78,31 @@ properties:
- mediatek,mt8192-vdecsys_soc
- mediatek,mt8192-vdecsys
- mediatek,mt8192-vencsys
+ - mediatek,mt8195-apusys_pll
+ - mediatek,mt8195-camsys
+ - mediatek,mt8195-camsys_rawa
+ - mediatek,mt8195-camsys_yuva
+ - mediatek,mt8195-camsys_rawb
+ - mediatek,mt8195-camsys_yuvb
+ - mediatek,mt8195-camsys_mraw
+ - mediatek,mt8195-ccusys
+ - mediatek,mt8195-imgsys
+ - mediatek,mt8195-imgsys1_dip_top
+ - mediatek,mt8195-imgsys1_dip_nr
+ - mediatek,mt8195-imgsys1_wpe
+ - mediatek,mt8195-imp_iic_wrap_s
+ - mediatek,mt8195-imp_iic_wrap_w
+ - mediatek,mt8195-ipesys
+ - mediatek,mt8195-mfgcfg
+ - mediatek,mt8195-scp_adsp
+ - mediatek,mt8195-vdecsys_soc
+ - mediatek,mt8195-vdecsys
+ - mediatek,mt8195-vdecsys_core1
+ - mediatek,mt8195-vencsys
+ - mediatek,mt8195-vencsys_core1
+ - mediatek,mt8195-wpesys
+ - mediatek,mt8195-wpesys_vpp0
+ - mediatek,mt8195-wpesys_vpp1
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index 4500842b20de..c4288b91e6b6 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -39,6 +39,10 @@ properties:
- mediatek,mt8192-infracfg
- mediatek,mt8192-pericfg
- mediatek,mt8192-topckgen
+ - mediatek,mt8195-apmixedsys
+ - mediatek,mt8195-infracfg_ao
+ - mediatek,mt8195-pericfg_ao
+ - mediatek,mt8195-topckgen
- const: syscon
reg:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml
deleted file mode 100644
index fcc963aff087..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml
+++ /dev/null
@@ -1,238 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek Functional Clock Controller for MT8195
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The clock architecture in Mediatek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The devices except apusys_pll provide clock gate control in different IP blocks.
- The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8195-scp_adsp
- - mediatek,mt8195-imp_iic_wrap_s
- - mediatek,mt8195-imp_iic_wrap_w
- - mediatek,mt8195-mfgcfg
- - mediatek,mt8195-wpesys
- - mediatek,mt8195-wpesys_vpp0
- - mediatek,mt8195-wpesys_vpp1
- - mediatek,mt8195-imgsys
- - mediatek,mt8195-imgsys1_dip_top
- - mediatek,mt8195-imgsys1_dip_nr
- - mediatek,mt8195-imgsys1_wpe
- - mediatek,mt8195-ipesys
- - mediatek,mt8195-camsys
- - mediatek,mt8195-camsys_rawa
- - mediatek,mt8195-camsys_yuva
- - mediatek,mt8195-camsys_rawb
- - mediatek,mt8195-camsys_yuvb
- - mediatek,mt8195-camsys_mraw
- - mediatek,mt8195-ccusys
- - mediatek,mt8195-vdecsys_soc
- - mediatek,mt8195-vdecsys
- - mediatek,mt8195-vdecsys_core1
- - mediatek,mt8195-vencsys
- - mediatek,mt8195-vencsys_core1
- - mediatek,mt8195-apusys_pll
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- scp_adsp: clock-controller@10720000 {
- compatible = "mediatek,mt8195-scp_adsp";
- reg = <0x10720000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_s: clock-controller@11d03000 {
- compatible = "mediatek,mt8195-imp_iic_wrap_s";
- reg = <0x11d03000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_w: clock-controller@11e05000 {
- compatible = "mediatek,mt8195-imp_iic_wrap_w";
- reg = <0x11e05000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- mfgcfg: clock-controller@13fbf000 {
- compatible = "mediatek,mt8195-mfgcfg";
- reg = <0x13fbf000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- wpesys: clock-controller@14e00000 {
- compatible = "mediatek,mt8195-wpesys";
- reg = <0x14e00000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- wpesys_vpp0: clock-controller@14e02000 {
- compatible = "mediatek,mt8195-wpesys_vpp0";
- reg = <0x14e02000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- wpesys_vpp1: clock-controller@14e03000 {
- compatible = "mediatek,mt8195-wpesys_vpp1";
- reg = <0x14e03000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys: clock-controller@15000000 {
- compatible = "mediatek,mt8195-imgsys";
- reg = <0x15000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys1_dip_top: clock-controller@15110000 {
- compatible = "mediatek,mt8195-imgsys1_dip_top";
- reg = <0x15110000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys1_dip_nr: clock-controller@15130000 {
- compatible = "mediatek,mt8195-imgsys1_dip_nr";
- reg = <0x15130000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys1_wpe: clock-controller@15220000 {
- compatible = "mediatek,mt8195-imgsys1_wpe";
- reg = <0x15220000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- ipesys: clock-controller@15330000 {
- compatible = "mediatek,mt8195-ipesys";
- reg = <0x15330000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys: clock-controller@16000000 {
- compatible = "mediatek,mt8195-camsys";
- reg = <0x16000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawa: clock-controller@1604f000 {
- compatible = "mediatek,mt8195-camsys_rawa";
- reg = <0x1604f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_yuva: clock-controller@1606f000 {
- compatible = "mediatek,mt8195-camsys_yuva";
- reg = <0x1606f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawb: clock-controller@1608f000 {
- compatible = "mediatek,mt8195-camsys_rawb";
- reg = <0x1608f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_yuvb: clock-controller@160af000 {
- compatible = "mediatek,mt8195-camsys_yuvb";
- reg = <0x160af000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_mraw: clock-controller@16140000 {
- compatible = "mediatek,mt8195-camsys_mraw";
- reg = <0x16140000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- ccusys: clock-controller@17200000 {
- compatible = "mediatek,mt8195-ccusys";
- reg = <0x17200000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys_soc: clock-controller@1800f000 {
- compatible = "mediatek,mt8195-vdecsys_soc";
- reg = <0x1800f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys: clock-controller@1802f000 {
- compatible = "mediatek,mt8195-vdecsys";
- reg = <0x1802f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys_core1: clock-controller@1803f000 {
- compatible = "mediatek,mt8195-vdecsys_core1";
- reg = <0x1803f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vencsys: clock-controller@1a000000 {
- compatible = "mediatek,mt8195-vencsys";
- reg = <0x1a000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vencsys_core1: clock-controller@1b000000 {
- compatible = "mediatek,mt8195-vencsys_core1";
- reg = <0x1b000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- apusys_pll: clock-controller@190f3000 {
- compatible = "mediatek,mt8195-apusys_pll";
- reg = <0x190f3000 0x1000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml
deleted file mode 100644
index 69f096eb168d..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml
+++ /dev/null
@@ -1,76 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek System Clock Controller for MT8195
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The clock architecture in Mediatek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The apmixedsys provides most of PLLs which generated from SoC 26m.
- The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
- The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8195-topckgen
- - mediatek,mt8195-infracfg_ao
- - mediatek,mt8195-apmixedsys
- - mediatek,mt8195-pericfg_ao
- - const: syscon
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- topckgen: syscon@10000000 {
- compatible = "mediatek,mt8195-topckgen", "syscon";
- reg = <0x10000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- infracfg_ao: syscon@10001000 {
- compatible = "mediatek,mt8195-infracfg_ao", "syscon";
- reg = <0x10001000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- apmixedsys: syscon@1000c000 {
- compatible = "mediatek,mt8195-apmixedsys", "syscon";
- reg = <0x1000c000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- pericfg_ao: syscon@11003000 {
- compatible = "mediatek,mt8195-pericfg_ao", "syscon";
- reg = <0x11003000 0x1000>;
- #clock-cells = <1>;
- };
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 05/15] dt-bindings: clock: mediatek: Add MT8189 clocks
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (3 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 04/15] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 06/15] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
` (9 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add dt schema and IDs for the clocks of MediaTek MT8189 SoC.
The MT8189 clock IP provide clock control for main system
(apmixedsys, topcksys and vlpcksys) and subsys (eg. peri, scp,
ufs...).
Also, add compatible for frequency hopping and spread spectrum clock
functionality and reset controller header file for MT8189 UFS reset
controller support.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 28 ++
.../bindings/clock/mediatek,mt8186-fhctl.yaml | 1 +
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 10 +
include/dt-bindings/clock/mediatek,mt8189-clk.h | 433 +++++++++++++++++++++
include/dt-bindings/reset/mediatek,mt8189-resets.h | 17 +
5 files changed, 489 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 84e602c7d326..e30ed16f321d 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -58,6 +58,19 @@ properties:
- mediatek,mt8188-vencsys
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
+ - mediatek,mt8189-dbg-ao
+ - mediatek,mt8189-dem
+ - mediatek,mt8189-dvfsrc-top
+ - mediatek,mt8189-iic-wrap-e
+ - mediatek,mt8189-iic-wrap-en
+ - mediatek,mt8189-iic-wrap-s
+ - mediatek,mt8189-iic-wrap-ws
+ - mediatek,mt8189-scp-clk
+ - mediatek,mt8189-scp-i2c-clk
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
+ - mediatek,mt8189-vlpcfg
+ - mediatek,mt8189-vlpcfg-ao
- mediatek,mt8192-camsys
- mediatek,mt8192-camsys_rawa
- mediatek,mt8192-camsys_rawb
@@ -145,6 +158,19 @@ allOf:
- mediatek,mt8188-vencsys
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
+ - mediatek,mt8189-dbg-ao
+ - mediatek,mt8189-dem
+ - mediatek,mt8189-dvfsrc-top
+ - mediatek,mt8189-iic-wrap-e
+ - mediatek,mt8189-iic-wrap-en
+ - mediatek,mt8189-iic-wrap-s
+ - mediatek,mt8189-iic-wrap-ws
+ - mediatek,mt8189-scp-clk
+ - mediatek,mt8189-scp-i2c-clk
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
+ - mediatek,mt8189-vlpcfg
+ - mediatek,mt8189-vlpcfg-ao
then:
required:
- '#clock-cells'
@@ -163,6 +189,8 @@ allOf:
- mediatek,mt8188-imgsys1-dip-nr
- mediatek,mt8188-imgsys1-dip-top
- mediatek,mt8188-ipesys
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
then:
required:
- '#reset-cells'
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
index d00327d12e1e..824e3b2bd6c0 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
@@ -20,6 +20,7 @@ properties:
- mediatek,mt6795-fhctl
- mediatek,mt8173-fhctl
- mediatek,mt8186-fhctl
+ - mediatek,mt8189-fhctl
- mediatek,mt8192-fhctl
- mediatek,mt8195-fhctl
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index c4288b91e6b6..35094ed68548 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -35,6 +35,11 @@ properties:
- mediatek,mt8188-infracfg-ao
- mediatek,mt8188-pericfg-ao
- mediatek,mt8188-topckgen
+ - mediatek,mt8189-apmixedsys
+ - mediatek,mt8189-infra-ao
+ - mediatek,mt8189-peri-ao
+ - mediatek,mt8189-topckgen
+ - mediatek,mt8189-vlpckgen
- mediatek,mt8192-apmixedsys
- mediatek,mt8192-infracfg
- mediatek,mt8192-pericfg
@@ -68,6 +73,11 @@ allOf:
- mediatek,mt8188-infracfg-ao
- mediatek,mt8188-pericfg-ao
- mediatek,mt8188-topckgen
+ - mediatek,mt8189-apmixedsys
+ - mediatek,mt8189-infra-ao
+ - mediatek,mt8189-peri-ao
+ - mediatek,mt8189-topckgen
+ - mediatek,mt8189-vlpckgen
then:
required:
- '#clock-cells'
diff --git a/include/dt-bindings/clock/mediatek,mt8189-clk.h b/include/dt-bindings/clock/mediatek,mt8189-clk.h
new file mode 100644
index 000000000000..ca433f969698
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt8189-clk.h
@@ -0,0 +1,433 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8189_H
+#define _DT_BINDINGS_CLK_MT8189_H
+
+/* TOPCKGEN */
+#define CLK_TOP_AXI_SEL 0
+#define CLK_TOP_AXI_PERI_SEL 1
+#define CLK_TOP_AXI_U_SEL 2
+#define CLK_TOP_BUS_AXIMEM_SEL 3
+#define CLK_TOP_DISP0_SEL 4
+#define CLK_TOP_MMINFRA_SEL 5
+#define CLK_TOP_UART_SEL 6
+#define CLK_TOP_SPI0_SEL 7
+#define CLK_TOP_SPI1_SEL 8
+#define CLK_TOP_SPI2_SEL 9
+#define CLK_TOP_SPI3_SEL 10
+#define CLK_TOP_SPI4_SEL 11
+#define CLK_TOP_SPI5_SEL 12
+#define CLK_TOP_MSDC_MACRO_0P_SEL 13
+#define CLK_TOP_MSDC50_0_HCLK_SEL 14
+#define CLK_TOP_MSDC50_0_SEL 15
+#define CLK_TOP_AES_MSDCFDE_SEL 16
+#define CLK_TOP_MSDC_MACRO_1P_SEL 17
+#define CLK_TOP_MSDC30_1_SEL 18
+#define CLK_TOP_MSDC30_1_HCLK_SEL 19
+#define CLK_TOP_MSDC_MACRO_2P_SEL 20
+#define CLK_TOP_MSDC30_2_SEL 21
+#define CLK_TOP_MSDC30_2_HCLK_SEL 22
+#define CLK_TOP_AUD_INTBUS_SEL 23
+#define CLK_TOP_ATB_SEL 24
+#define CLK_TOP_DISP_PWM_SEL 25
+#define CLK_TOP_USB_TOP_P0_SEL 26
+#define CLK_TOP_USB_XHCI_P0_SEL 27
+#define CLK_TOP_USB_TOP_P1_SEL 28
+#define CLK_TOP_USB_XHCI_P1_SEL 29
+#define CLK_TOP_USB_TOP_P2_SEL 30
+#define CLK_TOP_USB_XHCI_P2_SEL 31
+#define CLK_TOP_USB_TOP_P3_SEL 32
+#define CLK_TOP_USB_XHCI_P3_SEL 33
+#define CLK_TOP_USB_TOP_P4_SEL 34
+#define CLK_TOP_USB_XHCI_P4_SEL 35
+#define CLK_TOP_I2C_SEL 36
+#define CLK_TOP_SENINF_SEL 37
+#define CLK_TOP_SENINF1_SEL 38
+#define CLK_TOP_AUD_ENGEN1_SEL 39
+#define CLK_TOP_AUD_ENGEN2_SEL 40
+#define CLK_TOP_AES_UFSFDE_SEL 41
+#define CLK_TOP_U_SEL 42
+#define CLK_TOP_U_MBIST_SEL 43
+#define CLK_TOP_AUD_1_SEL 44
+#define CLK_TOP_AUD_2_SEL 45
+#define CLK_TOP_VENC_SEL 46
+#define CLK_TOP_VDEC_SEL 47
+#define CLK_TOP_PWM_SEL 48
+#define CLK_TOP_AUDIO_H_SEL 49
+#define CLK_TOP_MCUPM_SEL 50
+#define CLK_TOP_MEM_SUB_SEL 51
+#define CLK_TOP_MEM_SUB_PERI_SEL 52
+#define CLK_TOP_MEM_SUB_U_SEL 53
+#define CLK_TOP_EMI_N_SEL 54
+#define CLK_TOP_DSI_OCC_SEL 55
+#define CLK_TOP_AP2CONN_HOST_SEL 56
+#define CLK_TOP_IMG1_SEL 57
+#define CLK_TOP_IPE_SEL 58
+#define CLK_TOP_CAM_SEL 59
+#define CLK_TOP_CAMTM_SEL 60
+#define CLK_TOP_DSP_SEL 61
+#define CLK_TOP_SR_PKA_SEL 62
+#define CLK_TOP_DXCC_SEL 63
+#define CLK_TOP_MFG_REF_SEL 64
+#define CLK_TOP_MDP0_SEL 65
+#define CLK_TOP_DP_SEL 66
+#define CLK_TOP_EDP_SEL 67
+#define CLK_TOP_EDP_FAVT_SEL 68
+#define CLK_TOP_ETH_250M_SEL 69
+#define CLK_TOP_ETH_62P4M_PTP_SEL 70
+#define CLK_TOP_ETH_50M_RMII_SEL 71
+#define CLK_TOP_SFLASH_SEL 72
+#define CLK_TOP_GCPU_SEL 73
+#define CLK_TOP_MAC_TL_SEL 74
+#define CLK_TOP_VDSTX_DG_CTS_SEL 75
+#define CLK_TOP_PLL_DPIX_SEL 76
+#define CLK_TOP_ECC_SEL 77
+#define CLK_TOP_APLL_I2SIN0_MCK_SEL 78
+#define CLK_TOP_APLL_I2SIN1_MCK_SEL 79
+#define CLK_TOP_APLL_I2SIN2_MCK_SEL 80
+#define CLK_TOP_APLL_I2SIN3_MCK_SEL 81
+#define CLK_TOP_APLL_I2SIN4_MCK_SEL 82
+#define CLK_TOP_APLL_I2SIN6_MCK_SEL 83
+#define CLK_TOP_APLL_I2SOUT0_MCK_SEL 84
+#define CLK_TOP_APLL_I2SOUT1_MCK_SEL 85
+#define CLK_TOP_APLL_I2SOUT2_MCK_SEL 86
+#define CLK_TOP_APLL_I2SOUT3_MCK_SEL 87
+#define CLK_TOP_APLL_I2SOUT4_MCK_SEL 88
+#define CLK_TOP_APLL_I2SOUT6_MCK_SEL 89
+#define CLK_TOP_APLL_FMI2S_MCK_SEL 90
+#define CLK_TOP_APLL_TDMOUT_MCK_SEL 91
+#define CLK_TOP_MFG_SEL_MFGPLL 92
+#define CLK_TOP_APLL12_CK_DIV_I2SIN0 93
+#define CLK_TOP_APLL12_CK_DIV_I2SIN1 94
+#define CLK_TOP_APLL12_CK_DIV_I2SOUT0 95
+#define CLK_TOP_APLL12_CK_DIV_I2SOUT1 96
+#define CLK_TOP_APLL12_CK_DIV_FMI2S 97
+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 98
+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 99
+#define CLK_TOP_MAINPLL_D3 100
+#define CLK_TOP_MAINPLL_D4 101
+#define CLK_TOP_MAINPLL_D4_D2 102
+#define CLK_TOP_MAINPLL_D4_D4 103
+#define CLK_TOP_MAINPLL_D4_D8 104
+#define CLK_TOP_MAINPLL_D5 105
+#define CLK_TOP_MAINPLL_D5_D2 106
+#define CLK_TOP_MAINPLL_D5_D4 107
+#define CLK_TOP_MAINPLL_D5_D8 108
+#define CLK_TOP_MAINPLL_D6 109
+#define CLK_TOP_MAINPLL_D6_D2 110
+#define CLK_TOP_MAINPLL_D6_D4 111
+#define CLK_TOP_MAINPLL_D6_D8 112
+#define CLK_TOP_MAINPLL_D7 113
+#define CLK_TOP_MAINPLL_D7_D2 114
+#define CLK_TOP_MAINPLL_D7_D4 115
+#define CLK_TOP_MAINPLL_D7_D8 116
+#define CLK_TOP_MAINPLL_D9 117
+#define CLK_TOP_UNIVPLL_D2 118
+#define CLK_TOP_UNIVPLL_D3 119
+#define CLK_TOP_UNIVPLL_D4 120
+#define CLK_TOP_UNIVPLL_D4_D2 121
+#define CLK_TOP_UNIVPLL_D4_D4 122
+#define CLK_TOP_UNIVPLL_D4_D8 123
+#define CLK_TOP_UNIVPLL_D5 124
+#define CLK_TOP_UNIVPLL_D5_D2 125
+#define CLK_TOP_UNIVPLL_D5_D4 126
+#define CLK_TOP_UNIVPLL_D6 127
+#define CLK_TOP_UNIVPLL_D6_D2 128
+#define CLK_TOP_UNIVPLL_D6_D4 129
+#define CLK_TOP_UNIVPLL_D6_D8 130
+#define CLK_TOP_UNIVPLL_D6_D16 131
+#define CLK_TOP_UNIVPLL_D7 132
+#define CLK_TOP_UNIVPLL_D7_D2 133
+#define CLK_TOP_UNIVPLL_D7_D3 134
+#define CLK_TOP_LVDSTX_DG_CTS 135
+#define CLK_TOP_UNIVPLL_192M 136
+#define CLK_TOP_UNIVPLL_192M_D2 137
+#define CLK_TOP_UNIVPLL_192M_D4 138
+#define CLK_TOP_UNIVPLL_192M_D8 139
+#define CLK_TOP_UNIVPLL_192M_D10 140
+#define CLK_TOP_UNIVPLL_192M_D16 141
+#define CLK_TOP_UNIVPLL_192M_D32 142
+#define CLK_TOP_APLL1_D2 143
+#define CLK_TOP_APLL1_D4 144
+#define CLK_TOP_APLL1_D8 145
+#define CLK_TOP_APLL1_D3 146
+#define CLK_TOP_APLL2_D2 147
+#define CLK_TOP_APLL2_D4 148
+#define CLK_TOP_APLL2_D8 149
+#define CLK_TOP_APLL2_D3 150
+#define CLK_TOP_MMPLL_D4 151
+#define CLK_TOP_MMPLL_D4_D2 152
+#define CLK_TOP_MMPLL_D4_D4 153
+#define CLK_TOP_VPLL_DPIX 154
+#define CLK_TOP_MMPLL_D5 155
+#define CLK_TOP_MMPLL_D5_D2 156
+#define CLK_TOP_MMPLL_D5_D4 157
+#define CLK_TOP_MMPLL_D6 158
+#define CLK_TOP_MMPLL_D6_D2 159
+#define CLK_TOP_MMPLL_D7 160
+#define CLK_TOP_MMPLL_D9 161
+#define CLK_TOP_TVDPLL1_D2 162
+#define CLK_TOP_TVDPLL1_D4 163
+#define CLK_TOP_TVDPLL1_D8 164
+#define CLK_TOP_TVDPLL1_D16 165
+#define CLK_TOP_TVDPLL2_D2 166
+#define CLK_TOP_TVDPLL2_D4 167
+#define CLK_TOP_TVDPLL2_D8 168
+#define CLK_TOP_TVDPLL2_D16 169
+#define CLK_TOP_ETHPLL_D2 170
+#define CLK_TOP_ETHPLL_D8 171
+#define CLK_TOP_ETHPLL_D10 172
+#define CLK_TOP_MSDCPLL_D2 173
+#define CLK_TOP_UFSPLL_D2 174
+#define CLK_TOP_F26M_CK_D2 175
+#define CLK_TOP_OSC_D2 176
+#define CLK_TOP_OSC_D4 177
+#define CLK_TOP_OSC_D8 178
+#define CLK_TOP_OSC_D16 179
+#define CLK_TOP_OSC_D3 180
+#define CLK_TOP_OSC_D7 181
+#define CLK_TOP_OSC_D10 182
+#define CLK_TOP_OSC_D20 183
+#define CLK_TOP_FMCNT_P0_EN 184
+#define CLK_TOP_FMCNT_P1_EN 185
+#define CLK_TOP_FMCNT_P2_EN 186
+#define CLK_TOP_FMCNT_P3_EN 187
+#define CLK_TOP_FMCNT_P4_EN 188
+#define CLK_TOP_USB_F26M_CK_EN 189
+#define CLK_TOP_SSPXTP_F26M_CK_EN 190
+#define CLK_TOP_USB2_PHY_RF_P0_EN 191
+#define CLK_TOP_USB2_PHY_RF_P1_EN 192
+#define CLK_TOP_USB2_PHY_RF_P2_EN 193
+#define CLK_TOP_USB2_PHY_RF_P3_EN 194
+#define CLK_TOP_USB2_PHY_RF_P4_EN 195
+#define CLK_TOP_USB2_26M_CK_P0_EN 196
+#define CLK_TOP_USB2_26M_CK_P1_EN 197
+#define CLK_TOP_USB2_26M_CK_P2_EN 198
+#define CLK_TOP_USB2_26M_CK_P3_EN 199
+#define CLK_TOP_USB2_26M_CK_P4_EN 200
+#define CLK_TOP_F26M_CK_EN 201
+#define CLK_TOP_AP2CON_EN 202
+#define CLK_TOP_EINT_N_EN 203
+#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN 204
+#define CLK_TOP_EINT_E_EN 205
+#define CLK_TOP_EINT_W_EN 206
+#define CLK_TOP_EINT_S_EN 207
+
+/* INFRACFG_AO */
+#define CLK_IFRAO_CQ_DMA_FPC 0
+#define CLK_IFRAO_DEBUGSYS 1
+#define CLK_IFRAO_DBG_TRACE 2
+#define CLK_IFRAO_CQ_DMA 3
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL 0
+#define CLK_APMIXED_ARMPLL_BL 1
+#define CLK_APMIXED_CCIPLL 2
+#define CLK_APMIXED_MAINPLL 3
+#define CLK_APMIXED_UNIVPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_MFGPLL 6
+#define CLK_APMIXED_APLL1 7
+#define CLK_APMIXED_APLL2 8
+#define CLK_APMIXED_EMIPLL 9
+#define CLK_APMIXED_APUPLL2 10
+#define CLK_APMIXED_APUPLL 11
+#define CLK_APMIXED_TVDPLL1 12
+#define CLK_APMIXED_TVDPLL2 13
+#define CLK_APMIXED_ETHPLL 14
+#define CLK_APMIXED_MSDCPLL 15
+#define CLK_APMIXED_UFSPLL 16
+
+/* PERICFG_AO */
+#define CLK_PERAO_UART0 0
+#define CLK_PERAO_UART1 1
+#define CLK_PERAO_UART2 2
+#define CLK_PERAO_UART3 3
+#define CLK_PERAO_PWM_H 4
+#define CLK_PERAO_PWM_B 5
+#define CLK_PERAO_PWM_FB1 6
+#define CLK_PERAO_PWM_FB2 7
+#define CLK_PERAO_PWM_FB3 8
+#define CLK_PERAO_PWM_FB4 9
+#define CLK_PERAO_DISP_PWM0 10
+#define CLK_PERAO_DISP_PWM1 11
+#define CLK_PERAO_SPI0_B 12
+#define CLK_PERAO_SPI1_B 13
+#define CLK_PERAO_SPI2_B 14
+#define CLK_PERAO_SPI3_B 15
+#define CLK_PERAO_SPI4_B 16
+#define CLK_PERAO_SPI5_B 17
+#define CLK_PERAO_SPI0_H 18
+#define CLK_PERAO_SPI1_H 19
+#define CLK_PERAO_SPI2_H 20
+#define CLK_PERAO_SPI3_H 21
+#define CLK_PERAO_SPI4_H 22
+#define CLK_PERAO_SPI5_H 23
+#define CLK_PERAO_AXI 24
+#define CLK_PERAO_AHB_APB 25
+#define CLK_PERAO_TL 26
+#define CLK_PERAO_REF 27
+#define CLK_PERAO_I2C 28
+#define CLK_PERAO_DMA_B 29
+#define CLK_PERAO_SSUSB0_REF 30
+#define CLK_PERAO_SSUSB0_FRMCNT 31
+#define CLK_PERAO_SSUSB0_SYS 32
+#define CLK_PERAO_SSUSB0_XHCI 33
+#define CLK_PERAO_SSUSB0_F 34
+#define CLK_PERAO_SSUSB0_H 35
+#define CLK_PERAO_SSUSB1_REF 36
+#define CLK_PERAO_SSUSB1_FRMCNT 37
+#define CLK_PERAO_SSUSB1_SYS 38
+#define CLK_PERAO_SSUSB1_XHCI 39
+#define CLK_PERAO_SSUSB1_F 40
+#define CLK_PERAO_SSUSB1_H 41
+#define CLK_PERAO_SSUSB2_REF 42
+#define CLK_PERAO_SSUSB2_FRMCNT 43
+#define CLK_PERAO_SSUSB2_SYS 44
+#define CLK_PERAO_SSUSB2_XHCI 45
+#define CLK_PERAO_SSUSB2_F 46
+#define CLK_PERAO_SSUSB2_H 47
+#define CLK_PERAO_SSUSB3_REF 48
+#define CLK_PERAO_SSUSB3_FRMCNT 49
+#define CLK_PERAO_SSUSB3_SYS 50
+#define CLK_PERAO_SSUSB3_XHCI 51
+#define CLK_PERAO_SSUSB3_F 52
+#define CLK_PERAO_SSUSB3_H 53
+#define CLK_PERAO_SSUSB4_REF 54
+#define CLK_PERAO_SSUSB4_FRMCNT 55
+#define CLK_PERAO_SSUSB4_SYS 56
+#define CLK_PERAO_SSUSB4_XHCI 57
+#define CLK_PERAO_SSUSB4_F 58
+#define CLK_PERAO_SSUSB4_H 59
+#define CLK_PERAO_MSDC0 60
+#define CLK_PERAO_MSDC0_H 61
+#define CLK_PERAO_MSDC0_FAES 62
+#define CLK_PERAO_MSDC0_MST_F 63
+#define CLK_PERAO_MSDC0_SLV_H 64
+#define CLK_PERAO_MSDC1 65
+#define CLK_PERAO_MSDC1_H 66
+#define CLK_PERAO_MSDC1_MST_F 67
+#define CLK_PERAO_MSDC1_SLV_H 68
+#define CLK_PERAO_MSDC2 69
+#define CLK_PERAO_MSDC2_H 70
+#define CLK_PERAO_MSDC2_MST_F 71
+#define CLK_PERAO_MSDC2_SLV_H 72
+#define CLK_PERAO_SFLASH 73
+#define CLK_PERAO_SFLASH_F 74
+#define CLK_PERAO_SFLASH_H 75
+#define CLK_PERAO_SFLASH_P 76
+#define CLK_PERAO_AUDIO0 77
+#define CLK_PERAO_AUDIO1 78
+#define CLK_PERAO_AUDIO2 79
+#define CLK_PERAO_AUXADC_26M 80
+
+/* UFSCFG_AO_REG */
+#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM 0
+#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0 1
+#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1 2
+#define CLK_UFSCFG_AO_REG_UNIPRO_SYS 3
+#define CLK_UFSCFG_AO_REG_U_SAP_CFG 4
+#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS 5
+
+/* UFSCFG_PDN_REG */
+#define CLK_UFSCFG_REG_UFSHCI_UFS 0
+#define CLK_UFSCFG_REG_UFSHCI_AES 1
+#define CLK_UFSCFG_REG_UFSHCI_U_AHB 2
+#define CLK_UFSCFG_REG_UFSHCI_U_AXI 3
+
+/* IMP_IIC_WRAP_WS */
+#define CLK_IMPWS_I2C2 0
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_I2C0 0
+#define CLK_IMPE_I2C1 1
+
+/* IMP_IIC_WRAP_S */
+#define CLK_IMPS_I2C3 0
+#define CLK_IMPS_I2C4 1
+#define CLK_IMPS_I2C5 2
+#define CLK_IMPS_I2C6 3
+
+/* IMP_IIC_WRAP_EN */
+#define CLK_IMPEN_I2C7 0
+#define CLK_IMPEN_I2C8 1
+
+/* VLPCFG_REG */
+#define CLK_VLPCFG_REG_SCP 0
+#define CLK_VLPCFG_REG_RG_R_APXGPT_26M 1
+#define CLK_VLPCFG_REG_DPMSRCK_TEST 2
+#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST 3
+#define CLK_VLPCFG_REG_DPMSRULP_TEST 4
+#define CLK_VLPCFG_REG_SPMI_P_MST 5
+#define CLK_VLPCFG_REG_SPMI_P_MST_32K 6
+#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS 7
+#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR 8
+#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS 9
+#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR 10
+#define CLK_VLPCFG_REG_DVFSRC 11
+#define CLK_VLPCFG_REG_PWM_VLP 12
+#define CLK_VLPCFG_REG_SRCK 13
+#define CLK_VLPCFG_REG_SSPM_F26M 14
+#define CLK_VLPCFG_REG_SSPM_F32K 15
+#define CLK_VLPCFG_REG_SSPM_ULPOSC 16
+#define CLK_VLPCFG_REG_VLP_32K_COM 17
+#define CLK_VLPCFG_REG_VLP_26M_COM 18
+
+/* VLP_CKSYS */
+#define CLK_VLP_CK_SCP_SEL 0
+#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1
+#define CLK_VLP_CK_SPMI_P_MST_SEL 2
+#define CLK_VLP_CK_DVFSRC_SEL 3
+#define CLK_VLP_CK_PWM_VLP_SEL 4
+#define CLK_VLP_CK_AXI_VLP_SEL 5
+#define CLK_VLP_CK_SYSTIMER_26M_SEL 6
+#define CLK_VLP_CK_SSPM_SEL 7
+#define CLK_VLP_CK_SSPM_F26M_SEL 8
+#define CLK_VLP_CK_SRCK_SEL 9
+#define CLK_VLP_CK_SCP_SPI_SEL 10
+#define CLK_VLP_CK_SCP_IIC_SEL 11
+#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL 12
+#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 13
+#define CLK_VLP_CK_SSPM_ULPOSC_SEL 14
+#define CLK_VLP_CK_APXGPT_26M_SEL 15
+#define CLK_VLP_CK_VADSP_SEL 16
+#define CLK_VLP_CK_VADSP_VOWPLL_SEL 17
+#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL 18
+#define CLK_VLP_CK_CAMTG0_SEL 19
+#define CLK_VLP_CK_CAMTG1_SEL 20
+#define CLK_VLP_CK_CAMTG2_SEL 21
+#define CLK_VLP_CK_AUD_ADC_SEL 22
+#define CLK_VLP_CK_KP_IRQ_GEN_SEL 23
+#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24
+#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 25
+
+/* SCP_IIC */
+#define CLK_SCP_IIC_I2C0_W1S 0
+#define CLK_SCP_IIC_I2C1_W1S 1
+
+/* SCP */
+#define CLK_SCP_SET_SPI0 0
+#define CLK_SCP_SET_SPI1 1
+
+/* VLPCFG_AO_REG */
+#define CLK_VLPCFG_AO_APEINT_RX 0
+
+/* DVFSRC_TOP */
+#define CLK_DVFSRC_TOP_DVFSRC_EN 0
+
+/* DBGAO */
+#define CLK_DBGAO_ATB_EN 0
+
+/* DEM */
+#define CLK_DEM_ATB_EN 0
+#define CLK_DEM_BUSCLK_EN 1
+#define CLK_DEM_SYSCLK_EN 2
+
+#endif /* _DT_BINDINGS_CLK_MT8189_H */
diff --git a/include/dt-bindings/reset/mediatek,mt8189-resets.h b/include/dt-bindings/reset/mediatek,mt8189-resets.h
new file mode 100644
index 000000000000..0f31984374be
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt8189-resets.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2026 Collabora Ltd.
+ * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8189
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8189
+
+/* UFS resets */
+#define MT8189_UFSAO_RST_UFS_MPHY 0
+
+#define MT8189_UFSPDN_RST_UFS_UNIPRO 0
+#define MT8189_UFSPDN_RST_UFS_CRYPTO 1
+#define MT8189_UFSPDN_RST_UFS_HCI 2
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8189 */
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 06/15] clk: mediatek: Add MT8189 apmixedsys clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (4 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 05/15] dt-bindings: clock: mediatek: Add MT8189 clocks Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 07/15] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
` (8 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 apmixedsys clock controller, which provides
PLLs generated from SoC 26m.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 13 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 196 +++++++++++++++++++++++++++
3 files changed, 210 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 2c09fd729bab..f67dfb6cd019 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -815,6 +815,19 @@ config COMMON_CLK_MT8188_WPESYS
help
This driver supports MediaTek MT8188 Warp Engine clocks.
+config COMMON_CLK_MT8189
+ tristate "Clock driver for MediaTek MT8189"
+ depends on ARM64 || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ select COMMON_CLK_MEDIATEK_FHCTL
+ default ARCH_MEDIATEK
+ help
+ Enable this option to support the clock management for MediaTek MT8189 SoC. This
+ includes handling of all primary clock functions and features specific to the MT8189
+ platform. Enabling this driver ensures that the system's clock functionality aligns
+ with the MediaTek MT8189 hardware capabilities, providing efficient management of
+ clock speeds and power consumption.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index d8736a060dbd..66577ccb9b93 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
+obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-apmixedsys.c b/drivers/clk/mediatek/clk-mt8189-apmixedsys.c
new file mode 100644
index 000000000000..0657a50c30d9
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-apmixedsys.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-fhctl.h"
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+#define MT8189_PLL_FMAX (3800UL * MHZ)
+#define MT8189_PLL_FMIN (1500UL * MHZ)
+#define MT8189_PLLEN_OFS 0x70
+#define MT8189_INTEGER_BITS 8
+
+#define PLL_SETCLR(_id, _name, _reg, _en_setclr_bit, \
+ _rstb_setclr_bit, _flags, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcwbits) { \
+ .id = _id, \
+ .name = _name, \
+ .en_reg = MT8189_PLLEN_OFS, \
+ .reg = _reg, \
+ .pll_en_bit = _en_setclr_bit, \
+ .rst_bar_mask = BIT(_rstb_setclr_bit), \
+ .flags = _flags, \
+ .fmax = MT8189_PLL_FMAX, \
+ .fmin = MT8189_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8189_INTEGER_BITS, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL_SETCLR(CLK_APMIXED_ARMPLL_LL, "armpll-ll", 0x204, 18,
+ 0, PLL_AO, 0x208, 24, 0, 0, 0, 0x208, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_ARMPLL_BL, "armpll-bl", 0x214, 17,
+ 0, PLL_AO, 0x218, 24, 0, 0, 0, 0x218, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_CCIPLL, "ccipll", 0x224, 16,
+ 0, PLL_AO, 0x228, 24, 0, 0, 0, 0x228, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MAINPLL, "mainpll", 0x304, 15,
+ 23, HAVE_RST_BAR | PLL_AO,
+ 0x308, 24, 0, 0, 0, 0x308, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_UNIVPLL, "univpll", 0x314, 14,
+ 23, HAVE_RST_BAR, 0x318, 24, 0, 0, 0, 0x318, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MMPLL, "mmpll", 0x324, 13,
+ 23, HAVE_RST_BAR, 0x328, 24, 0, 0, 0, 0x328, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MFGPLL, "mfgpll", 0x504, 7,
+ 0, 0, 0x508, 24, 0, 0, 0, 0x508, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_APLL1, "apll1", 0x404, 11,
+ 0, 0, 0x408, 24, 0x040, 0x00c, 0, 0x40c, 0, 32),
+ PLL_SETCLR(CLK_APMIXED_APLL2, "apll2", 0x418, 10,
+ 0, 0, 0x41c, 24, 0x044, 0x00c, 1, 0x420, 0, 32),
+ PLL_SETCLR(CLK_APMIXED_EMIPLL, "emipll", 0x334, 12,
+ 0, PLL_AO, 0x338, 24, 0, 0, 0, 0x338, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_APUPLL2, "apupll2", 0x614, 2,
+ 0, 0, 0x618, 24, 0, 0, 0, 0x618, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_APUPLL, "apupll", 0x604, 3,
+ 0, 0, 0x608, 24, 0, 0, 0, 0x608, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x42c, 9,
+ 0, 0, 0x430, 24, 0, 0, 0, 0x430, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x43c, 8,
+ 0, 0, 0x440, 24, 0, 0, 0, 0x440, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_ETHPLL, "ethpll", 0x514, 6,
+ 0, 0, 0x518, 24, 0, 0, 0, 0x518, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MSDCPLL, "msdcpll", 0x524, 5,
+ 0, 0, 0x528, 24, 0, 0, 0, 0x528, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_UFSPLL, "ufspll", 0x534, 4,
+ 0, 0, 0x538, 24, 0, 0, 0, 0x538, 0, 22),
+};
+
+#define FH(_pllid, _fhid, _offset) { \
+ .data = { \
+ .pll_id = _pllid, \
+ .fh_id = _fhid, \
+ .fh_ver = FHCTL_PLLFH_V2, \
+ .fhx_offset = _offset, \
+ .dds_mask = GENMASK(21, 0), \
+ .slope0_value = 0x6003c97, \
+ .slope1_value = 0x6003c97, \
+ .sfstrx_en = BIT(2), \
+ .frddsx_en = BIT(1), \
+ .fhctlx_en = BIT(0), \
+ .tgl_org = BIT(31), \
+ .dvfs_tri = BIT(31), \
+ .pcwchg = BIT(31), \
+ .dt_val = 0x0, \
+ .df_val = 0x9, \
+ .updnlmt_shft = 16, \
+ .msk_frddsx_dys = GENMASK(23, 20), \
+ .msk_frddsx_dts = GENMASK(19, 16), \
+ }, \
+ }
+
+static struct mtk_pllfh_data pllfhs[] = {
+ FH(CLK_APMIXED_ARMPLL_LL, 0, 0x003C),
+ FH(CLK_APMIXED_ARMPLL_BL, 1, 0x0050),
+ FH(CLK_APMIXED_CCIPLL, 2, 0x0064),
+ FH(CLK_APMIXED_MAINPLL, 3, 0x0078),
+ FH(CLK_APMIXED_MMPLL, 4, 0x008C),
+ FH(CLK_APMIXED_MFGPLL, 5, 0x00A0),
+ FH(CLK_APMIXED_EMIPLL, 6, 0x00B4),
+ FH(CLK_APMIXED_TVDPLL1, 7, 0x00C8),
+ FH(CLK_APMIXED_TVDPLL2, 8, 0x00DC),
+ FH(CLK_APMIXED_MSDCPLL, 9, 0x00F0),
+ FH(CLK_APMIXED_UFSPLL, 10, 0x0104),
+ FH(CLK_APMIXED_APUPLL, 11, 0x0118),
+ FH(CLK_APMIXED_APUPLL2, 12, 0x012c),
+};
+
+static const struct of_device_id of_match_clk_mt8189_apmixed[] = {
+ { .compatible = "mediatek,mt8189-apmixedsys" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_apmixed);
+
+static int clk_mt8189_apmixed_probe(struct platform_device *pdev)
+{
+ int r;
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ const u8 *fhctl_node = "mediatek,mt8189-fhctl";
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
+ if (!clk_data)
+ return -ENOMEM;
+
+ fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+
+ r = mtk_clk_register_pllfhs(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls),
+ pllfhs, ARRAY_SIZE(pllfhs), clk_data);
+ if (r)
+ goto free_apmixed_data;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_plls;
+
+ platform_set_drvdata(pdev, clk_data);
+
+ return 0;
+
+unregister_plls:
+ mtk_clk_unregister_pllfhs(apmixed_plls, ARRAY_SIZE(apmixed_plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
+free_apmixed_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static void clk_mt8189_apmixed_remove(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_pllfhs(apmixed_plls, ARRAY_SIZE(apmixed_plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static struct platform_driver clk_mt8189_apmixed_drv = {
+ .probe = clk_mt8189_apmixed_probe,
+ .remove = clk_mt8189_apmixed_remove,
+ .driver = {
+ .name = "clk-mt8189-apmixed",
+ .of_match_table = of_match_clk_mt8189_apmixed,
+ },
+};
+module_platform_driver(clk_mt8189_apmixed_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 apmixed clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 07/15] clk: mediatek: Add MT8189 topckgen clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (5 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 06/15] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 08/15] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
` (7 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 topckgen clock controller, which provides
muxes and dividers for clock selection in other IP blocks.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8189-topckgen.c | 1024 ++++++++++++++++++++++++++++
2 files changed, 1025 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 66577ccb9b93..9d3d2983bfb2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -123,7 +123,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
-obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o
+obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-topckgen.c b/drivers/clk/mediatek/clk-mt8189-topckgen.c
new file mode 100644
index 000000000000..62d292f5b8b8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-topckgen.c
@@ -0,0 +1,1024 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static DEFINE_SPINLOCK(mt8189_clk_lock);
+
+static const struct mtk_fixed_factor top_divs[] = {
+ FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll", 1, 3),
+ FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll", 1, 4),
+ FACTOR(CLK_TOP_MAINPLL_D4_D2, "mainpll_d4_d2", "mainpll", 1, 8),
+ FACTOR(CLK_TOP_MAINPLL_D4_D4, "mainpll_d4_d4", "mainpll", 1, 16),
+ FACTOR(CLK_TOP_MAINPLL_D4_D8, "mainpll_d4_d8", "mainpll", 43, 1375),
+ FACTOR(CLK_TOP_MAINPLL_D5, "mainpll_d5", "mainpll", 1, 5),
+ FACTOR(CLK_TOP_MAINPLL_D5_D2, "mainpll_d5_d2", "mainpll", 1, 10),
+ FACTOR(CLK_TOP_MAINPLL_D5_D4, "mainpll_d5_d4", "mainpll", 1, 20),
+ FACTOR(CLK_TOP_MAINPLL_D5_D8, "mainpll_d5_d8", "mainpll", 1, 40),
+ FACTOR(CLK_TOP_MAINPLL_D6, "mainpll_d6", "mainpll", 1, 6),
+ FACTOR(CLK_TOP_MAINPLL_D6_D2, "mainpll_d6_d2", "mainpll", 1, 12),
+ FACTOR(CLK_TOP_MAINPLL_D6_D4, "mainpll_d6_d4", "mainpll", 1, 24),
+ FACTOR(CLK_TOP_MAINPLL_D6_D8, "mainpll_d6_d8", "mainpll", 1, 48),
+ FACTOR(CLK_TOP_MAINPLL_D7, "mainpll_d7", "mainpll", 1, 7),
+ FACTOR(CLK_TOP_MAINPLL_D7_D2, "mainpll_d7_d2", "mainpll", 1, 14),
+ FACTOR(CLK_TOP_MAINPLL_D7_D4, "mainpll_d7_d4", "mainpll", 1, 28),
+ FACTOR(CLK_TOP_MAINPLL_D7_D8, "mainpll_d7_d8", "mainpll", 1, 56),
+ FACTOR(CLK_TOP_MAINPLL_D9, "mainpll_d9", "mainpll", 1, 9),
+ FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
+ FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
+ FACTOR(CLK_TOP_UNIVPLL_D4, "univpll_d4", "univpll", 1, 4),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D2, "univpll_d4_d2", "univpll", 1, 8),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D4, "univpll_d4_d4", "univpll", 1, 16),
+ FACTOR(CLK_TOP_UNIVPLL_D4_D8, "univpll_d4_d8", "univpll", 1, 32),
+ FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D2, "univpll_d5_d2", "univpll", 1, 10),
+ FACTOR(CLK_TOP_UNIVPLL_D5_D4, "univpll_d5_d4", "univpll", 1, 20),
+ FACTOR(CLK_TOP_UNIVPLL_D6, "univpll_d6", "univpll", 1, 6),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D2, "univpll_d6_d2", "univpll", 1, 12),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D4, "univpll_d6_d4", "univpll", 1, 24),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D8, "univpll_d6_d8", "univpll", 1, 48),
+ FACTOR(CLK_TOP_UNIVPLL_D6_D16, "univpll_d6_d16", "univpll", 1, 96),
+ FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
+ FACTOR(CLK_TOP_UNIVPLL_D7_D2, "univpll_d7_d2", "univpll", 1, 14),
+ FACTOR(CLK_TOP_UNIVPLL_D7_D3, "univpll_d7_d3", "univpll", 1, 21),
+ FACTOR(CLK_TOP_LVDSTX_DG_CTS, "lvdstx_dg_cts", "univpll", 1, 21),
+ FACTOR(CLK_TOP_UNIVPLL_192M, "univpll_192m", "univpll", 1, 13),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D2, "univpll_192m_d2", "univpll", 1, 26),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D4, "univpll_192m_d4", "univpll", 1, 52),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D8, "univpll_192m_d8", "univpll", 1, 104),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D10, "univpll_192m_d10", "univpll", 1, 130),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D16, "univpll_192m_d16", "univpll", 1, 208),
+ FACTOR(CLK_TOP_UNIVPLL_192M_D32, "univpll_192m_d32", "univpll", 1, 416),
+ FACTOR(CLK_TOP_APLL1_D2, "apll1_d2", "apll1", 1, 2),
+ FACTOR(CLK_TOP_APLL1_D4, "apll1_d4", "apll1", 1, 4),
+ FACTOR(CLK_TOP_APLL1_D8, "apll1_d8", "apll1", 1, 8),
+ FACTOR(CLK_TOP_APLL1_D3, "apll1_d3", "apll1", 1, 3),
+ FACTOR(CLK_TOP_APLL2_D2, "apll2_d2", "apll2", 1, 2),
+ FACTOR(CLK_TOP_APLL2_D4, "apll2_d4", "apll2", 1, 4),
+ FACTOR(CLK_TOP_APLL2_D8, "apll2_d8", "apll2", 1, 8),
+ FACTOR(CLK_TOP_APLL2_D3, "apll2_d3", "apll2", 1, 3),
+ FACTOR(CLK_TOP_MMPLL_D4, "mmpll_d4", "mmpll", 1, 4),
+ FACTOR(CLK_TOP_MMPLL_D4_D2, "mmpll_d4_d2", "mmpll", 1, 8),
+ FACTOR(CLK_TOP_MMPLL_D4_D4, "mmpll_d4_d4", "mmpll", 1, 16),
+ FACTOR(CLK_TOP_VPLL_DPIX, "vpll_dpix", "mmpll", 1, 16),
+ FACTOR(CLK_TOP_MMPLL_D5, "mmpll_d5", "mmpll", 1, 5),
+ FACTOR(CLK_TOP_MMPLL_D5_D2, "mmpll_d5_d2", "mmpll", 1, 10),
+ FACTOR(CLK_TOP_MMPLL_D5_D4, "mmpll_d5_d4", "mmpll", 1, 20),
+ FACTOR(CLK_TOP_MMPLL_D6, "mmpll_d6", "mmpll", 1, 6),
+ FACTOR(CLK_TOP_MMPLL_D6_D2, "mmpll_d6_d2", "mmpll", 1, 12),
+ FACTOR(CLK_TOP_MMPLL_D7, "mmpll_d7", "mmpll", 1, 7),
+ FACTOR(CLK_TOP_MMPLL_D9, "mmpll_d9", "mmpll", 1, 9),
+ FACTOR(CLK_TOP_TVDPLL1_D2, "tvdpll1_d2", "tvdpll1", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL1_D4, "tvdpll1_d4", "tvdpll1", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL1_D8, "tvdpll1_d8", "tvdpll1", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL1_D16, "tvdpll1_d16", "tvdpll1", 92, 1473),
+ FACTOR(CLK_TOP_TVDPLL2_D2, "tvdpll2_d2", "tvdpll2", 1, 2),
+ FACTOR(CLK_TOP_TVDPLL2_D4, "tvdpll2_d4", "tvdpll2", 1, 4),
+ FACTOR(CLK_TOP_TVDPLL2_D8, "tvdpll2_d8", "tvdpll2", 1, 8),
+ FACTOR(CLK_TOP_TVDPLL2_D16, "tvdpll2_d16", "tvdpll2", 92, 1473),
+ FACTOR(CLK_TOP_ETHPLL_D2, "ethpll_d2", "ethpll", 1, 2),
+ FACTOR(CLK_TOP_ETHPLL_D8, "ethpll_d8", "ethpll", 1, 8),
+ FACTOR(CLK_TOP_ETHPLL_D10, "ethpll_d10", "ethpll", 1, 10),
+ FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
+ FACTOR(CLK_TOP_UFSPLL_D2, "ufspll_d2", "ufspll", 1, 2),
+ FACTOR(CLK_TOP_F26M_CK_D2, "f26m_d2", "clk26m", 1, 2),
+ FACTOR(CLK_TOP_OSC_D2, "osc_d2", "ulposc", 1, 2),
+ FACTOR(CLK_TOP_OSC_D4, "osc_d4", "ulposc", 1, 4),
+ FACTOR(CLK_TOP_OSC_D8, "osc_d8", "ulposc", 1, 8),
+ FACTOR(CLK_TOP_OSC_D16, "osc_d16", "ulposc", 61, 973),
+ FACTOR(CLK_TOP_OSC_D3, "osc_d3", "ulposc", 1, 3),
+ FACTOR(CLK_TOP_OSC_D7, "osc_d7", "ulposc", 1, 7),
+ FACTOR(CLK_TOP_OSC_D10, "osc_d10", "ulposc", 1, 10),
+ FACTOR(CLK_TOP_OSC_D20, "osc_d20", "ulposc", 1, 20),
+};
+
+static const char * const ap2conn_host_parents[] = {
+ "clk26m",
+ "mainpll_d7_d4"
+};
+
+static const char * const apll_m_parents[] = {
+ "aud_1_sel",
+ "aud_2_sel"
+};
+
+static const char * const aud_1_parents[] = {
+ "clk26m",
+ "apll1"
+};
+
+static const char * const aud_2_parents[] = {
+ "clk26m",
+ "apll2"
+};
+
+static const char * const mfg_sel_mfgpll_parents[] = {
+ "mfg_ref_sel",
+ "mfgpll"
+};
+
+static const char * const pwm_parents[] = {
+ "clk26m",
+ "univpll_d4_d8"
+};
+
+static const char * const snps_eth_250m_parents[] = {
+ "clk26m",
+ "ethpll_d2"
+};
+
+static const char * const snps_eth_50m_rmii_parents[] = {
+ "clk26m",
+ "ethpll_d10"
+};
+
+static const char * const uart_parents[] = {
+ "clk26m",
+ "univpll_d6_d8"
+};
+
+static const char * const atb_parents[] = {
+ "clk26m",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2"
+};
+
+static const char * const aud_intbus_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "mainpll_d7_d4"
+};
+
+static const char * const msdc5hclk_parents[] = {
+ "clk26m",
+ "mainpll_d4_d2",
+ "mainpll_d6_d2"
+};
+
+static const char * const pcie_mac_tl_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "univpll_d5_d4"
+};
+
+static const char * const pll_dpix_parents[] = {
+ "clk26m",
+ "vpll_dpix",
+ "mmpll_d4_d4"
+};
+
+static const char * const usb_parents[] = {
+ "clk26m",
+ "univpll_d5_d4",
+ "univpll_d6_d4"
+};
+
+static const char * const vdstx_dg_cts_parents[] = {
+ "clk26m",
+ "lvdstx_dg_cts",
+ "univpll_d7_d3"
+};
+
+static const char * const audio_h_parents[] = {
+ "clk26m",
+ "univpll_d7_d2",
+ "apll1",
+ "apll2"
+};
+
+static const char * const aud_engen1_parents[] = {
+ "clk26m",
+ "apll1_d2",
+ "apll1_d4",
+ "apll1_d8"
+};
+
+static const char * const aud_engen2_parents[] = {
+ "clk26m",
+ "apll2_d2",
+ "apll2_d4",
+ "apll2_d8"
+};
+
+static const char * const axi_peri_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "mainpll_d7_d2",
+ "osc_d4"
+};
+
+static const char * const axi_u_parents[] = {
+ "clk26m",
+ "mainpll_d4_d8",
+ "mainpll_d7_d4",
+ "osc_d8"
+};
+
+static const char * const camtm_parents[] = {
+ "clk26m",
+ "osc_d2",
+ "univpll_d6_d2",
+ "univpll_d6_d4"
+};
+
+static const char * const dsi_occ_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d5_d2",
+ "univpll_d4_d2"
+};
+
+static const char * const dxcc_parents[] = {
+ "clk26m",
+ "mainpll_d4_d8",
+ "mainpll_d4_d4",
+ "mainpll_d4_d2"
+};
+
+static const char * const i2c_parents[] = {
+ "clk26m",
+ "mainpll_d4_d8",
+ "univpll_d5_d4",
+ "mainpll_d4_d4"
+};
+
+static const char * const mcupm_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2"
+};
+
+static const char * const mfg_ref_parents[] = {
+ "clk26m",
+ "mainpll_d6_d2",
+ "mainpll_d6",
+ "mainpll_d5_d2"
+};
+
+static const char * const msdc30_h_parents[] = {
+ "clk26m",
+ "msdcpll_d2",
+ "mainpll_d4_d4",
+ "mainpll_d6_d4"
+};
+
+static const char * const msdc_macro_p_parents[] = {
+ "clk26m",
+ "msdcpll",
+ "mmpll_d5_d4",
+ "univpll_d4_d2"
+};
+
+static const char * const snps_eth_62p4m_ptp_parents[] = {
+ "clk26m",
+ "ethpll_d8",
+ "apll1_d3",
+ "apll2_d3"
+};
+
+static const char * const ufs_mbist_parents[] = {
+ "clk26m",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "ufspll_d2"
+};
+
+static const char * const aes_msdcfde_parents[] = {
+ "clk26m",
+ "mainpll_d4_d2",
+ "mainpll_d6",
+ "mainpll_d4_d4",
+ "msdcpll"
+};
+
+static const char * const bus_aximem_parents[] = {
+ "clk26m",
+ "mainpll_d7_d2",
+ "mainpll_d5_d2",
+ "mainpll_d4_d2",
+ "mainpll_d6"
+};
+
+static const char * const dp_parents[] = {
+ "clk26m",
+ "tvdpll1_d16",
+ "tvdpll1_d8",
+ "tvdpll1_d4",
+ "tvdpll1_d2"
+};
+
+static const char * const msdc30_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "mainpll_d6_d2",
+ "mainpll_d7_d2",
+ "msdcpll_d2"
+};
+
+static const char * const ecc_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_d4_d2",
+ "univpll_d6",
+ "mainpll_d4",
+ "univpll_d4"
+};
+
+static const char * const emi_n_parents[] = {
+ "clk26m",
+ "osc_d2",
+ "mainpll_d9",
+ "mainpll_d6",
+ "mainpll_d5",
+ "emipll"
+};
+
+static const char * const sr_pka_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "mainpll_d4_d2",
+ "mainpll_d7",
+ "mainpll_d6",
+ "mainpll_d5"
+};
+
+static const char * const aes_ufsfde_parents[] = {
+ "clk26m",
+ "mainpll_d4",
+ "mainpll_d4_d2",
+ "mainpll_d6",
+ "mainpll_d4_d4",
+ "univpll_d4_d2",
+ "univpll_d6"
+};
+
+static const char * const axi_parents[] = {
+ "clk26m",
+ "mainpll_d4_d4",
+ "mainpll_d7_d2",
+ "mainpll_d4_d2",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2",
+ "osc_d4"
+};
+
+static const char * const disp_pwm_parents[] = {
+ "clk26m",
+ "univpll_d6_d4",
+ "osc_d2",
+ "osc_d4",
+ "osc_d16",
+ "univpll_d5_d4",
+ "mainpll_d4_d4"
+};
+
+static const char * const edp_parents[] = {
+ "clk26m",
+ "tvdpll2_d16",
+ "tvdpll2_d8",
+ "tvdpll2_d4",
+ "tvdpll2_d2"
+};
+
+static const char * const gcpu_parents[] = {
+ "clk26m",
+ "mainpll_d6",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "univpll_d5_d2",
+ "univpll_d5_d4",
+ "univpll_d6"
+};
+
+static const char * const msdc50_0_parents[] = {
+ "clk26m",
+ "msdcpll",
+ "msdcpll_d2",
+ "mainpll_d6_d2",
+ "mainpll_d4_d4",
+ "mainpll_d6",
+ "univpll_d4_d4"
+};
+
+static const char * const ufs_parents[] = {
+ "clk26m",
+ "mainpll_d4_d8",
+ "mainpll_d4_d4",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2",
+ "univpll_d6_d2",
+ "msdcpll_d2"
+};
+
+static const char * const dsp_parents[] = {
+ "clk26m",
+ "osc_d4",
+ "osc_d3",
+ "osc_d2",
+ "univpll_d7_d2",
+ "univpll_d6_d2",
+ "mainpll_d6",
+ "univpll_d5"
+};
+
+static const char * const mem_sub_peri_u_parents[] = {
+ "clk26m",
+ "univpll_d4_d4",
+ "mainpll_d5_d2",
+ "mainpll_d4_d2",
+ "mainpll_d6",
+ "mainpll_d5",
+ "univpll_d5",
+ "mainpll_d4"
+};
+
+static const char * const seninf_parents[] = {
+ "clk26m",
+ "osc_d2",
+ "univpll_d6_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "mmpll_d7",
+ "univpll_d6",
+ "univpll_d5"
+};
+
+static const char * const sflash_parents[] = {
+ "clk26m",
+ "mainpll_d7_d8",
+ "univpll_d6_d8",
+ "mainpll_d7_d4",
+ "mainpll_d6_d4",
+ "univpll_d6_d4",
+ "univpll_d7_d3",
+ "univpll_d5_d4"
+};
+
+static const char * const spi_parents[] = {
+ "clk26m",
+ "univpll_d6_d2",
+ "univpll_192m",
+ "mainpll_d6_d2",
+ "univpll_d4_d4",
+ "mainpll_d4_d4",
+ "univpll_d5_d4",
+ "univpll_d6_d4"
+};
+
+static const char * const img1_parents[] = {
+ "clk26m",
+ "univpll_d4",
+ "mmpll_d5",
+ "mmpll_d6",
+ "univpll_d6",
+ "mmpll_d7",
+ "mmpll_d4_d2",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "mmpll_d6_d2",
+ "mmpll_d5_d2"
+};
+
+static const char * const ipe_parents[] = {
+ "clk26m",
+ "univpll_d4",
+ "mainpll_d4",
+ "mmpll_d6",
+ "univpll_d6",
+ "mainpll_d6",
+ "mmpll_d4_d2",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "mmpll_d6_d2",
+ "mmpll_d5_d2"
+};
+
+static const char * const mem_sub_parents[] = {
+ "clk26m",
+ "univpll_d4_d4",
+ "mainpll_d6_d2",
+ "mainpll_d5_d2",
+ "mainpll_d4_d2",
+ "mainpll_d6",
+ "mmpll_d7",
+ "mainpll_d5",
+ "univpll_d5",
+ "mainpll_d4",
+ "univpll_d4"
+};
+
+static const char * const cam_parents[] = {
+ "clk26m",
+ "mainpll_d4",
+ "mmpll_d4",
+ "univpll_d4",
+ "univpll_d5",
+ "mmpll_d7",
+ "mmpll_d6",
+ "univpll_d6",
+ "univpll_d4_d2",
+ "mmpll_d9",
+ "mainpll_d4_d2",
+ "osc_d2"
+};
+
+static const char * const mmsys_parents[] = {
+ "clk26m",
+ "mainpll_d5_d2",
+ "univpll_d5_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "mainpll_d6",
+ "univpll_d6",
+ "mmpll_d6",
+ "tvdpll1",
+ "tvdpll2",
+ "univpll_d4",
+ "mmpll_d4"
+};
+
+static const char * const mminfra_parents[] = {
+ "clk26m",
+ "osc_d2",
+ "mainpll_d5_d2",
+ "mmpll_d6_d2",
+ "mainpll_d4_d2",
+ "mmpll_d4_d2",
+ "mainpll_d6",
+ "mmpll_d7",
+ "univpll_d6",
+ "mainpll_d5",
+ "mmpll_d6",
+ "univpll_d5",
+ "mainpll_d4",
+ "univpll_d4",
+ "mmpll_d4",
+ "emipll"
+};
+
+static const char * const vdec_parents[] = {
+ "clk26m",
+ "univpll_192m_d2",
+ "univpll_d5_d4",
+ "mainpll_d5",
+ "mainpll_d5_d2",
+ "mmpll_d6_d2",
+ "univpll_d5_d2",
+ "mainpll_d4_d2",
+ "univpll_d4_d2",
+ "univpll_d7",
+ "mmpll_d7",
+ "mmpll_d6",
+ "univpll_d6",
+ "mainpll_d4",
+ "univpll_d4",
+ "mmpll_d5_d2"
+};
+
+static const char * const venc_parents[] = {
+ "clk26m",
+ "mmpll_d4_d2",
+ "mainpll_d6",
+ "univpll_d4_d2",
+ "mainpll_d4_d2",
+ "univpll_d6",
+ "mmpll_d6",
+ "mainpll_d5_d2",
+ "mainpll_d6_d2",
+ "mmpll_d9",
+ "mmpll_d4",
+ "mainpll_d4",
+ "univpll_d4",
+ "univpll_d5",
+ "univpll_d5_d2",
+ "mainpll_d5"
+};
+
+static const struct mtk_mux top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel",
+ axi_parents, 0x010, 0x014, 0x018, 0, 3, 0x04, 0),
+ MUX_CLR_SET_UPD(CLK_TOP_AXI_PERI_SEL, "axi_peri_sel",
+ axi_peri_parents, 0x010, 0x014, 0x018,
+ 8, 2, 0x04, 1),
+ MUX_CLR_SET_UPD(CLK_TOP_AXI_U_SEL, "axi_u_sel",
+ axi_u_parents, 0x010, 0x014, 0x018,
+ 16, 2, 0x04, 2),
+ MUX_CLR_SET_UPD(CLK_TOP_BUS_AXIMEM_SEL, "bus_aximem_sel",
+ bus_aximem_parents, 0x010, 0x014, 0x018,
+ 24, 3, 0x04, 3),
+ /* CLK_CFG_1 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP0_SEL, "disp0_sel",
+ mmsys_parents, 0x020, 0x024, 0x028,
+ 0, 4, 7, 0x04, 4),
+ MUX_CLR_SET_UPD(CLK_TOP_MMINFRA_SEL, "mminfra_sel",
+ mminfra_parents, 0x020, 0x024, 0x028,
+ 8, 4, 0x04, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_UART_SEL, "uart_sel",
+ uart_parents, 0x020, 0x024, 0x028,
+ 16, 1, 23, 0x04, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI0_SEL, "spi0_sel",
+ spi_parents, 0x020, 0x024, 0x028,
+ 24, 3, 31, 0x04, 7),
+ /* CLK_CFG_2 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI1_SEL, "spi1_sel",
+ spi_parents, 0x030, 0x034, 0x038,
+ 0, 3, 7, 0x04, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI2_SEL, "spi2_sel",
+ spi_parents, 0x030, 0x034, 0x038,
+ 8, 3, 15, 0x04, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI3_SEL, "spi3_sel",
+ spi_parents, 0x030, 0x034, 0x038,
+ 16, 3, 23, 0x04, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI4_SEL, "spi4_sel",
+ spi_parents, 0x030, 0x034, 0x038,
+ 24, 3, 31, 0x04, 11),
+ /* CLK_CFG_3 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SPI5_SEL, "spi5_sel",
+ spi_parents, 0x040, 0x044, 0x048,
+ 0, 3, 7, 0x04, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_0P_SEL, "msdc_macro_0p_sel",
+ msdc_macro_p_parents, 0x040, 0x044, 0x048,
+ 8, 2, 15, 0x04, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_HCLK_SEL, "msdc5hclk_sel",
+ msdc5hclk_parents, 0x040, 0x044, 0x048,
+ 16, 2, 23, 0x04, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC50_0_SEL, "msdc50_0_sel",
+ msdc50_0_parents, 0x040, 0x044, 0x048,
+ 24, 3, 31, 0x04, 15),
+ /* CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_MSDCFDE_SEL, "aes_msdcfde_sel",
+ aes_msdcfde_parents, 0x050, 0x054, 0x058,
+ 0, 3, 7, 0x04, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_1P_SEL, "msdc_macro_1p_sel",
+ msdc_macro_p_parents, 0x050, 0x054, 0x058,
+ 8, 2, 15, 0x04, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel",
+ msdc30_parents, 0x050, 0x054, 0x058,
+ 16, 3, 23, 0x04, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_1_HCLK_SEL, "msdc30_1_h_sel",
+ msdc30_h_parents, 0x050, 0x054, 0x058,
+ 24, 2, 31, 0x04, 19),
+ /* CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC_MACRO_2P_SEL, "msdc_macro_2p_sel",
+ msdc_macro_p_parents, 0x060, 0x064, 0x068,
+ 0, 2, 7, 0x04, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel",
+ msdc30_parents, 0x060, 0x064, 0x068,
+ 8, 3, 15, 0x04, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MSDC30_2_HCLK_SEL, "msdc30_2_h_sel",
+ msdc30_h_parents, 0x060, 0x064, 0x068,
+ 16, 2, 23, 0x04, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_INTBUS_SEL, "aud_intbus_sel",
+ aud_intbus_parents, 0x060, 0x064, 0x068,
+ 24, 2, 31, 0x04, 23),
+ /* CLK_CFG_6 */
+ MUX_CLR_SET_UPD(CLK_TOP_ATB_SEL, "atb_sel",
+ atb_parents, 0x070, 0x074, 0x078, 0, 2, 0x04, 24),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DISP_PWM_SEL, "disp_pwm_sel",
+ disp_pwm_parents, 0x070, 0x074, 0x078,
+ 8, 3, 15, 0x04, 25),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P0_SEL, "usb_p0_sel",
+ usb_parents, 0x070, 0x074, 0x078,
+ 16, 2, 23, 0x04, 26),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P0_SEL, "ssusb_xhci_p0_sel",
+ usb_parents, 0x070, 0x074, 0x078,
+ 24, 2, 31, 0x04, 27),
+ /* CLK_CFG_7 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P1_SEL, "usb_p1_sel",
+ usb_parents, 0x080, 0x084, 0x088,
+ 0, 2, 7, 0x04, 28),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P1_SEL, "ssusb_xhci_p1_sel",
+ usb_parents, 0x080, 0x084, 0x088,
+ 8, 2, 15, 0x04, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P2_SEL, "usb_p2_sel",
+ usb_parents, 0x080, 0x084, 0x088,
+ 16, 2, 23, 0x04, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P2_SEL, "ssusb_xhci_p2_sel",
+ usb_parents, 0x080, 0x084, 0x088,
+ 24, 2, 31, 0x08, 0),
+ /* CLK_CFG_8 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P3_SEL, "usb_p3_sel",
+ usb_parents, 0x090, 0x094, 0x098,
+ 0, 2, 7, 0x08, 1),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P3_SEL, "ssusb_xhci_p3_sel",
+ usb_parents, 0x090, 0x094, 0x098,
+ 8, 2, 15, 0x08, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_TOP_P4_SEL, "usb_p4_sel",
+ usb_parents, 0x090, 0x094, 0x098,
+ 16, 2, 23, 0x08, 3),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_USB_XHCI_P4_SEL, "ssusb_xhci_p4_sel",
+ usb_parents, 0x090, 0x094, 0x098,
+ 24, 2, 31, 0x08, 4),
+ /* CLK_CFG_9 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_I2C_SEL, "i2c_sel",
+ i2c_parents, 0x0a0, 0x0a4, 0x0a8,
+ 0, 2, 7, 0x08, 5),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF_SEL, "seninf_sel",
+ seninf_parents, 0x0a0, 0x0a4, 0x0a8,
+ 8, 3, 15, 0x08, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SENINF1_SEL, "seninf1_sel",
+ seninf_parents, 0x0a0, 0x0a4, 0x0a8,
+ 16, 3, 23, 0x08, 7),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN1_SEL, "aud_engen1_sel",
+ aud_engen1_parents, 0x0a0, 0x0a4, 0x0a8,
+ 24, 2, 31, 0x08, 8),
+ /* CLK_CFG_10 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_ENGEN2_SEL, "aud_engen2_sel",
+ aud_engen2_parents, 0x0b0, 0x0b4, 0x0b8,
+ 0, 2, 7, 0x08, 9),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AES_UFSFDE_SEL, "aes_ufsfde_sel",
+ aes_ufsfde_parents, 0x0b0, 0x0b4, 0x0b8,
+ 8, 3, 15, 0x08, 10),
+ MUX_CLR_SET_UPD(CLK_TOP_U_SEL, "ufs_sel",
+ ufs_parents, 0x0b0, 0x0b4, 0x0b8,
+ 16, 3, 0x08, 11),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_U_MBIST_SEL, "ufs_mbist_sel",
+ ufs_mbist_parents, 0x0b0, 0x0b4, 0x0b8,
+ 24, 2, 31, 0x08, 12),
+ /* CLK_CFG_11 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_1_SEL, "aud_1_sel",
+ aud_1_parents, 0x0c0, 0x0c4, 0x0c8,
+ 0, 1, 7, 0x08, 13),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_2_SEL, "aud_2_sel",
+ aud_2_parents, 0x0c0, 0x0c4, 0x0c8,
+ 8, 1, 15, 0x08, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VENC_SEL, "venc_sel",
+ venc_parents, 0x0c0, 0x0c4, 0x0c8,
+ 16, 4, 23, 0x08, 15),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VDEC_SEL, "vdec_sel",
+ vdec_parents, 0x0c0, 0x0c4, 0x0c8,
+ 24, 4, 31, 0x08, 16),
+ /* CLK_CFG_12 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PWM_SEL, "pwm_sel",
+ pwm_parents, 0x0d0, 0x0d4, 0x0d8,
+ 0, 1, 7, 0x08, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_AUDIO_H_SEL, "audio_h_sel",
+ audio_h_parents, 0x0d0, 0x0d4, 0x0d8,
+ 8, 2, 15, 0x08, 18),
+ MUX_CLR_SET_UPD(CLK_TOP_MCUPM_SEL, "mcupm_sel",
+ mcupm_parents, 0x0d0, 0x0d4, 0x0d8,
+ 16, 2, 0x08, 19),
+ MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_SEL, "mem_sub_sel",
+ mem_sub_parents, 0x0d0, 0x0d4, 0x0d8,
+ 24, 4, 0x08, 20),
+ /* CLK_CFG_13 */
+ MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_PERI_SEL, "mem_sub_peri_sel",
+ mem_sub_peri_u_parents, 0x0e0, 0x0e4, 0x0e8,
+ 0, 3, 0x08, 21),
+ MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB_U_SEL, "mem_sub_u_sel",
+ mem_sub_peri_u_parents, 0x0e0, 0x0e4, 0x0e8,
+ 8, 3, 0x08, 22),
+ MUX_CLR_SET_UPD(CLK_TOP_EMI_N_SEL, "emi_n_sel",
+ emi_n_parents, 0x0e0, 0x0e4, 0x0e8,
+ 16, 3, 0x08, 23),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSI_OCC_SEL, "dsi_occ_sel",
+ dsi_occ_parents, 0x0e0, 0x0e4, 0x0e8,
+ 24, 2, 31, 0x08, 24),
+ /* CLK_CFG_14 */
+ MUX_CLR_SET_UPD(CLK_TOP_AP2CONN_HOST_SEL, "ap2conn_host_sel",
+ ap2conn_host_parents, 0x0f0, 0x0f4, 0x0f8,
+ 0, 1, 0x08, 25),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IMG1_SEL, "img1_sel",
+ img1_parents, 0x0f0, 0x0f4, 0x0f8,
+ 8, 4, 15, 0x08, 26),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_IPE_SEL, "ipe_sel",
+ ipe_parents, 0x0f0, 0x0f4, 0x0f8,
+ 16, 4, 23, 0x08, 27),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAM_SEL, "cam_sel",
+ cam_parents, 0x0f0, 0x0f4, 0x0f8,
+ 24, 4, 31, 0x08, 28),
+ /* CLK_CFG_15 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTM_SEL, "camtm_sel",
+ camtm_parents, 0x100, 0x104, 0x108,
+ 0, 2, 7, 0x08, 29),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel",
+ dsp_parents, 0x100, 0x104, 0x108,
+ 8, 3, 15, 0x08, 30),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_SR_PKA_SEL, "sr_pka_sel",
+ sr_pka_parents, 0x100, 0x104, 0x108,
+ 16, 3, 23, 0x0c, 0),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DXCC_SEL, "dxcc_sel",
+ dxcc_parents, 0x100, 0x104, 0x108,
+ 24, 2, 31, 0x0c, 1),
+ /* CLK_CFG_16 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
+ mfg_ref_parents, 0x110, 0x114, 0x118,
+ 0, 2, 7, 0x0c, 2),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MDP0_SEL, "mdp0_sel",
+ mmsys_parents, 0x110, 0x114, 0x118,
+ 8, 4, 15, 0x0c, 3),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_DP_SEL, "dp_sel",
+ dp_parents, 0x110, 0x114, 0x118,
+ 16, 3, 23, 0x0c, 4),
+ MUX_CLR_SET_UPD(CLK_TOP_EDP_SEL, "edp_sel",
+ edp_parents, 0x110, 0x114, 0x118,
+ 24, 3, 0x0c, 5),
+ /* CLK_CFG_17 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_EDP_FAVT_SEL, "edp_favt_sel",
+ edp_parents, 0x180, 0x184, 0x188,
+ 0, 3, 7, 0x0c, 6),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_250M_SEL, "snps_eth_250m_sel",
+ snps_eth_250m_parents, 0x180, 0x184, 0x188,
+ 8, 1, 15, 0x0c, 7),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_62P4M_PTP_SEL,
+ "snps_eth_62p4m_ptp_sel",
+ snps_eth_62p4m_ptp_parents,
+ 0x180, 0x184, 0x188, 16, 2, 23, 0x0c, 8),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ETH_50M_RMII_SEL,
+ "snps_eth_50m_rmii_sel",
+ snps_eth_50m_rmii_parents,
+ 0x180, 0x184, 0x188, 24, 1, 31, 0x0c, 9),
+ /* CLK_CFG_18 */
+ MUX_CLR_SET_UPD(CLK_TOP_SFLASH_SEL, "sflash_sel",
+ sflash_parents, 0x190, 0x194, 0x198,
+ 0, 3, 0x0c, 10),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_GCPU_SEL, "gcpu_sel",
+ gcpu_parents, 0x190, 0x194, 0x198,
+ 8, 3, 15, 0x0c, 11),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_MAC_TL_SEL, "pcie_mac_tl_sel",
+ pcie_mac_tl_parents, 0x190, 0x194, 0x198,
+ 16, 2, 23, 0x0c, 12),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_VDSTX_DG_CTS_SEL, "vdstx_dg_cts_sel",
+ vdstx_dg_cts_parents, 0x190, 0x194, 0x198,
+ 24, 2, 31, 0x0c, 13),
+ /* CLK_CFG_19 */
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_PLL_DPIX_SEL, "pll_dpix_sel",
+ pll_dpix_parents, 0x240, 0x244, 0x248,
+ 0, 2, 7, 0x0c, 14),
+ MUX_GATE_CLR_SET_UPD(CLK_TOP_ECC_SEL, "ecc_sel",
+ ecc_parents, 0x240, 0x244, 0x248,
+ 8, 3, 15, 0x0c, 15),
+ /* CLK_MISC_CFG_3 */
+ GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MFG_SEL_MFGPLL, "mfg_sel_mfgpll",
+ mfg_sel_mfgpll_parents,
+ 0x510, 0x514, 0x0518, 16, 1, 0, -1, -1,
+ CLK_SET_RATE_PARENT,
+ mtk_mux_clr_set_upd_ops)
+};
+
+static const struct mtk_composite top_composites[] = {
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL_I2SIN0_MCK_SEL, "apll_i2sin0_m_sel",
+ apll_m_parents, 0x0320, 16, 1),
+ MUX(CLK_TOP_APLL_I2SIN1_MCK_SEL, "apll_i2sin1_m_sel",
+ apll_m_parents, 0x0320, 17, 1),
+ MUX(CLK_TOP_APLL_I2SIN2_MCK_SEL, "apll_i2sin2_m_sel",
+ apll_m_parents, 0x0320, 18, 1),
+ MUX(CLK_TOP_APLL_I2SIN3_MCK_SEL, "apll_i2sin3_m_sel",
+ apll_m_parents, 0x0320, 19, 1),
+ MUX(CLK_TOP_APLL_I2SIN4_MCK_SEL, "apll_i2sin4_m_sel",
+ apll_m_parents, 0x0320, 20, 1),
+ MUX(CLK_TOP_APLL_I2SIN6_MCK_SEL, "apll_i2sin6_m_sel",
+ apll_m_parents, 0x0320, 21, 1),
+ MUX(CLK_TOP_APLL_I2SOUT0_MCK_SEL, "apll_i2sout0_m_sel",
+ apll_m_parents, 0x0320, 22, 1),
+ MUX(CLK_TOP_APLL_I2SOUT1_MCK_SEL, "apll_i2sout1_m_sel",
+ apll_m_parents, 0x0320, 23, 1),
+ MUX(CLK_TOP_APLL_I2SOUT2_MCK_SEL, "apll_i2sout2_m_sel",
+ apll_m_parents, 0x0320, 24, 1),
+ MUX(CLK_TOP_APLL_I2SOUT3_MCK_SEL, "apll_i2sout3_m_sel",
+ apll_m_parents, 0x0320, 25, 1),
+ MUX(CLK_TOP_APLL_I2SOUT4_MCK_SEL, "apll_i2sout4_m_sel",
+ apll_m_parents, 0x0320, 26, 1),
+ MUX(CLK_TOP_APLL_I2SOUT6_MCK_SEL, "apll_i2sout6_m_sel",
+ apll_m_parents, 0x0320, 27, 1),
+ MUX(CLK_TOP_APLL_FMI2S_MCK_SEL, "apll_fmi2s_m_sel",
+ apll_m_parents, 0x0320, 28, 1),
+ MUX(CLK_TOP_APLL_TDMOUT_MCK_SEL, "apll_tdmout_m_sel",
+ apll_m_parents, 0x0320, 29, 1),
+ /* CLK_AUDDIV_2 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SIN0, "apll12_div_i2sin0",
+ "apll_i2sin0_m_sel", 0x0320, 0, 0x0328, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SIN1, "apll12_div_i2sin1",
+ "apll_i2sin1_m_sel", 0x0320, 1, 0x0328, 8, 8),
+ /* CLK_AUDDIV_3 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SOUT0, "apll12_div_i2sout0",
+ "apll_i2sout0_m_sel", 0x0320, 6, 0x0334, 8, 16),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_I2SOUT1, "apll12_div_i2sout1",
+ "apll_i2sout1_m_sel", 0x0320, 7, 0x0334, 8, 24),
+ /* CLK_AUDDIV_5 */
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_FMI2S, "apll12_div_fmi2s",
+ "apll_fmi2s_m_sel", 0x0320, 12, 0x033c, 8, 0),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_M, "apll12_div_tdmout_m",
+ "apll_tdmout_m_sel", 0x0320, 13, 0x033c, 8, 8),
+ DIV_GATE(CLK_TOP_APLL12_CK_DIV_TDMOUT_B, "apll12_div_tdmout_b",
+ "apll12_div_tdmout_m", 0x0320, 14, 0x033c, 8, 16),
+};
+
+static const struct mtk_gate_regs top_cg_regs = {
+ .set_ofs = 0x514,
+ .clr_ofs = 0x518,
+ .sta_ofs = 0x510,
+};
+
+#define GATE_TOP_FLAGS(_id, _name, _parent, _shift, _flag) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &top_cg_regs, \
+ .shift = _shift, \
+ .flags = _flag, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_TOP(_id, _name, _parent, _shift) \
+ GATE_TOP_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate top_clks[] = {
+ GATE_TOP_FLAGS(CLK_TOP_FMCNT_P0_EN, "fmcnt_p0_en", "univpll_192m_d4", 0, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_FMCNT_P1_EN, "fmcnt_p1_en", "univpll_192m_d4", 1, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_FMCNT_P2_EN, "fmcnt_p2_en", "univpll_192m_d4", 2, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_FMCNT_P3_EN, "fmcnt_p3_en", "univpll_192m_d4", 3, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_FMCNT_P4_EN, "fmcnt_p4_en", "univpll_192m_d4", 4, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_USB_F26M_CK_EN, "ssusb_f26m", "clk26m", 5, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_SSPXTP_F26M_CK_EN, "sspxtp_f26m", "clk26m", 6, CLK_IS_CRITICAL),
+ GATE_TOP(CLK_TOP_USB2_PHY_RF_P0_EN, "usb2_phy_rf_p0_en", "ssusb_f26m", 7),
+ GATE_TOP(CLK_TOP_USB2_PHY_RF_P1_EN, "usb2_phy_rf_p1_en", "ssusb_f26m", 10),
+ GATE_TOP(CLK_TOP_USB2_PHY_RF_P2_EN, "usb2_phy_rf_p2_en", "ssusb_f26m", 11),
+ GATE_TOP(CLK_TOP_USB2_PHY_RF_P3_EN, "usb2_phy_rf_p3_en", "ssusb_f26m", 12),
+ GATE_TOP(CLK_TOP_USB2_PHY_RF_P4_EN, "usb2_phy_rf_p4_en", "ssusb_f26m", 13),
+ GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P0_EN, "usb2_26m_p0_en", "ssusb_f26m", 14, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P1_EN, "usb2_26m_p1_en", "ssusb_f26m", 15, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P2_EN, "usb2_26m_p2_en", "ssusb_f26m", 18, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P3_EN, "usb2_26m_p3_en", "ssusb_f26m", 19, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_USB2_26M_CK_P4_EN, "usb2_26m_p4_en", "ssusb_f26m", 20, CLK_IS_CRITICAL),
+ GATE_TOP(CLK_TOP_F26M_CK_EN, "pcie_f26m", "sspxtp_f26m", 21),
+ GATE_TOP_FLAGS(CLK_TOP_AP2CON_EN, "ap2con", "clk26m", 24, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_EINT_N_EN, "eint_n", "clk26m", 25, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN,
+ "fmipi_csi_up26m", "osc_d10", 26, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_EINT_E_EN, "eint_e", "clk26m", 28, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_EINT_W_EN, "eint_w", "clk26m", 30, CLK_IS_CRITICAL),
+ GATE_TOP_FLAGS(CLK_TOP_EINT_S_EN, "eint_s", "clk26m", 31, CLK_IS_CRITICAL),
+};
+
+/* Register mux notifier for MFG mux */
+static int clk_mt8189_reg_mfg_mux_notifier(struct device *dev,
+ struct clk *clk)
+{
+ struct mtk_mux_nb *mfg_mux_nb;
+
+ mfg_mux_nb = devm_kzalloc(dev, sizeof(*mfg_mux_nb), GFP_KERNEL);
+ if (!mfg_mux_nb)
+ return -ENOMEM;
+
+ mfg_mux_nb->ops = &mtk_mux_clr_set_upd_ops;
+ mfg_mux_nb->bypass_index = 0; /* Bypass to CLK_TOP_MFG_REF_SEL */
+
+ return devm_mtk_clk_mux_notifier_register(dev, clk, mfg_mux_nb);
+}
+
+static const struct mtk_clk_desc topck_desc = {
+ .factor_clks = top_divs,
+ .num_factor_clks = ARRAY_SIZE(top_divs),
+ .mux_clks = top_muxes,
+ .num_mux_clks = ARRAY_SIZE(top_muxes),
+ .composite_clks = top_composites,
+ .num_composite_clks = ARRAY_SIZE(top_composites),
+ .clks = top_clks,
+ .num_clks = ARRAY_SIZE(top_clks),
+ .clk_notifier_func = clk_mt8189_reg_mfg_mux_notifier,
+ .mfg_clk_idx = CLK_TOP_MFG_SEL_MFGPLL,
+ .clk_lock = &mt8189_clk_lock,
+};
+
+static const struct of_device_id of_match_clk_mt8189_topck[] = {
+ { .compatible = "mediatek,mt8189-topckgen", .data = &topck_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8189_topck_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-topck",
+ .of_match_table = of_match_clk_mt8189_topck,
+ },
+};
+module_platform_driver(clk_mt8189_topck_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 topckgen clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 08/15] clk: mediatek: Add MT8189 vlpckgen clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (6 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 07/15] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 09/15] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
` (6 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 vlpckgen clock controller, which provides
muxes and dividers for clock selection in vlp domain for other IP blocks.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8189-vlpckgen.c | 284 +++++++++++++++++++++++++++++
2 files changed, 286 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9d3d2983bfb2..3b25df9e7b50 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -123,7 +123,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
-obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \
+ clk-mt8189-vlpckgen.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-vlpckgen.c b/drivers/clk/mediatek/clk-mt8189-vlpckgen.c
new file mode 100644
index 000000000000..39ca051b9ef8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-vlpckgen.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static DEFINE_SPINLOCK(mt8189_vlpclk_lock);
+
+static const char * const vlp_26m_oscd10_parents[] = {
+ "clk26m",
+ "osc_d10"
+};
+
+static const char * const vlp_vadsp_vowpll_parents[] = {
+ "clk26m",
+ "vowpll"
+};
+
+static const char * const vlp_sspm_ulposc_parents[] = {
+ "ulposc",
+ "univpll_d5_d2",
+ "osc_d10"
+};
+
+static const char * const vlp_aud_adc_parents[] = {
+ "clk26m",
+ "vowpll",
+ "aud_adc_ext",
+ "osc_d10"
+};
+
+static const char * const vlp_scp_iic_spi_parents[] = {
+ "clk26m",
+ "mainpll_d5_d4",
+ "mainpll_d7_d2",
+ "osc_d10"
+};
+
+static const char * const vlp_vadsp_uarthub_b_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "univpll_d6_d4",
+ "univpll_d6_d2"
+};
+
+static const char * const vlp_axi_kp_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "osc_d2",
+ "mainpll_d7_d4",
+ "mainpll_d7_d2"
+};
+
+static const char * const vlp_sspm_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "mainpll_d5_d2",
+ "ulposc",
+ "mainpll_d6"
+};
+
+static const char * const vlp_pwm_vlp_parents[] = {
+ "clk26m",
+ "osc_d4",
+ "clk32k",
+ "osc_d10",
+ "mainpll_d4_d8"
+};
+
+static const char * const vlp_pwrap_ulposc_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "osc_d7",
+ "osc_d8",
+ "osc_d16",
+ "mainpll_d7_d8"
+};
+
+static const char * const vlp_vadsp_parents[] = {
+ "clk26m",
+ "osc_d20",
+ "osc_d10",
+ "osc_d2",
+ "ulposc",
+ "mainpll_d4_d2"
+};
+
+static const char * const vlp_scp_parents[] = {
+ "clk26m",
+ "univpll_d4",
+ "univpll_d3",
+ "mainpll_d3",
+ "univpll_d6",
+ "apll1",
+ "mainpll_d4",
+ "mainpll_d6",
+ "mainpll_d7",
+ "osc_d10"
+};
+
+static const char * const vlp_spmi_p_parents[] = {
+ "clk26m",
+ "f26m_d2",
+ "osc_d8",
+ "osc_d10",
+ "osc_d16",
+ "osc_d7",
+ "clk32k",
+ "mainpll_d7_d8",
+ "mainpll_d6_d8",
+ "mainpll_d5_d8"
+};
+
+static const char * const vlp_camtg_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d6_d8",
+ "univpll_192m_d4",
+ "osc_d16",
+ "osc_d20",
+ "osc_d10",
+ "univpll_d6_d16",
+ "tvdpll1_d16",
+ "f26m_d2",
+ "univpll_192m_d10",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const struct mtk_mux vlp_ck_muxes[] = {
+ /* VLP_CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, "vlp_scp_sel",
+ vlp_scp_parents, 0x008, 0x00c, 0x010,
+ 0, 4, 7, 0x04, 0),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, "vlp_pwrap_ulposc_sel",
+ vlp_pwrap_ulposc_parents, 0x008, 0x00c, 0x010,
+ 8, 3, 0x04, 1),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, "vlp_spmi_p_sel",
+ vlp_spmi_p_parents, 0x008, 0x00c, 0x010,
+ 16, 4, 0x04, 2),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, "vlp_dvfsrc_sel",
+ vlp_26m_oscd10_parents, 0x008, 0x00c, 0x010,
+ 24, 1, 0x04, 3),
+ /* VLP_CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, "vlp_pwm_vlp_sel",
+ vlp_pwm_vlp_parents, 0x014, 0x018, 0x01c,
+ 0, 3, 0x04, 4),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, "vlp_axi_vlp_sel",
+ vlp_axi_kp_parents, 0x014, 0x018, 0x01c,
+ 8, 3, 0x04, 5),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, "vlp_timer_26m_sel",
+ vlp_26m_oscd10_parents, 0x014, 0x018, 0x01c,
+ 16, 1, 0x04, 6),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, "vlp_sspm_sel",
+ vlp_sspm_parents, 0x014, 0x018, 0x01c,
+ 24, 3, 0x04, 7),
+ /* VLP_CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_F26M_SEL, "vlp_sspm_f26m_sel",
+ vlp_26m_oscd10_parents, 0x020, 0x024, 0x028,
+ 0, 1, 0x04, 8),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, "vlp_srck_sel",
+ vlp_26m_oscd10_parents, 0x020, 0x024, 0x028,
+ 8, 1, 0x04, 9),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, "vlp_scp_spi_sel",
+ vlp_scp_iic_spi_parents, 0x020, 0x024, 0x028,
+ 16, 2, 0x04, 10),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, "vlp_scp_iic_sel",
+ vlp_scp_iic_spi_parents, 0x020, 0x024, 0x028,
+ 24, 2, 0x04, 11),
+ /* VLP_CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL,
+ "vlp_scp_spi_hs_sel",
+ vlp_scp_iic_spi_parents, 0x02c, 0x030, 0x034,
+ 0, 2, 0x04, 12),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL,
+ "vlp_scp_iic_hs_sel",
+ vlp_scp_iic_spi_parents, 0x02c, 0x030, 0x034,
+ 8, 2, 0x04, 13),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, "vlp_sspm_ulposc_sel",
+ vlp_sspm_ulposc_parents, 0x02c, 0x030, 0x034,
+ 16, 2, 0x04, 14),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_SEL, "vlp_apxgpt_26m_sel",
+ vlp_26m_oscd10_parents, 0x02c, 0x030, 0x034,
+ 24, 1, 0x04, 15),
+ /* VLP_CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_SEL, "vlp_vadsp_sel",
+ vlp_vadsp_parents, 0x038, 0x03c, 0x040,
+ 0, 3, 7, 0x04, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_VOWPLL_SEL,
+ "vlp_vadsp_vowpll_sel",
+ vlp_vadsp_vowpll_parents, 0x038, 0x03c, 0x040,
+ 8, 1, 15, 0x04, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL,
+ "vlp_vadsp_uarthub_b_sel",
+ vlp_vadsp_uarthub_b_parents,
+ 0x038, 0x03c, 0x040, 16, 2, 23, 0x04, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG0_SEL, "vlp_camtg0_sel",
+ vlp_camtg_parents, 0x038, 0x03c, 0x040,
+ 24, 4, 31, 0x04, 19),
+ /* VLP_CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG1_SEL, "vlp_camtg1_sel",
+ vlp_camtg_parents, 0x044, 0x048, 0x04c,
+ 0, 4, 7, 0x04, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG2_SEL, "vlp_camtg2_sel",
+ vlp_camtg_parents, 0x044, 0x048, 0x04c,
+ 8, 4, 15, 0x04, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_AUD_ADC_SEL, "vlp_aud_adc_sel",
+ vlp_aud_adc_parents, 0x044, 0x048, 0x04c,
+ 16, 2, 23, 0x04, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, "vlp_kp_irq_sel",
+ vlp_axi_kp_parents, 0x044, 0x048, 0x04c,
+ 24, 3, 31, 0x04, 23),
+};
+
+static const struct mtk_gate_regs vlp_ck_cg_regs = {
+ .set_ofs = 0x1f4,
+ .clr_ofs = 0x1f8,
+ .sta_ofs = 0x1f0,
+};
+
+#define GATE_VLP_CK_FLAGS(_id, _name, _parent, _shift, _flag) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vlp_ck_cg_regs, \
+ .shift = _shift, \
+ .flags = _flag, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VLP_CK(_id, _name, _parent, _shift) \
+ GATE_VLP_CK_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate vlp_ck_clks[] = {
+ GATE_VLP_CK(CLK_VLP_CK_VADSYS_VLP_26M_EN, "vlp_vadsys_vlp_26m", "clk26m", 1),
+ GATE_VLP_CK_FLAGS(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, "vlp_fmipi_csi_up26m",
+ "fmipi_csi_up26m", 11, CLK_IS_CRITICAL),
+};
+
+static const struct mtk_clk_desc vlpck_desc = {
+ .mux_clks = vlp_ck_muxes,
+ .num_mux_clks = ARRAY_SIZE(vlp_ck_muxes),
+ .clks = vlp_ck_clks,
+ .num_clks = ARRAY_SIZE(vlp_ck_clks),
+ .clk_lock = &mt8189_vlpclk_lock,
+};
+
+static const struct of_device_id of_match_clk_mt8189_vlpck[] = {
+ { .compatible = "mediatek,mt8189-vlpckgen", .data = &vlpck_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8189_vlpck_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-vlpck",
+ .of_match_table = of_match_clk_mt8189_vlpck,
+ },
+};
+module_platform_driver(clk_mt8189_vlpck_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 vlpckgen clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 09/15] clk: mediatek: Add MT8189 vlpcfg clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (7 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 08/15] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 10/15] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
` (5 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 vlpcfg clock controller,
which provides clock gate control for vlp domain IPs.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Makefile | 2 +-
drivers/clk/mediatek/clk-mt8189-vlpcfg.c | 115 +++++++++++++++++++++++++++++++
2 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 3b25df9e7b50..d9279b237b7b 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -124,7 +124,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \
- clk-mt8189-vlpckgen.o
+ clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-vlpcfg.c b/drivers/clk/mediatek/clk-mt8189-vlpcfg.c
new file mode 100644
index 000000000000..81e2d44bd320
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-vlpcfg.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs vlpcfg_ao_reg_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_VLPCFG_AO_REG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &vlpcfg_ao_reg_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr)
+
+static const struct mtk_gate vlpcfg_ao_reg_clks[] = {
+ GATE_VLPCFG_AO_REG(CLK_VLPCFG_AO_APEINT_RX, "vlpcfg_ao_apeint_rx", "clk26m", 8),
+};
+
+static const struct mtk_clk_desc vlpcfg_ao_reg_mcd = {
+ .clks = vlpcfg_ao_reg_clks,
+ .num_clks = ARRAY_SIZE(vlpcfg_ao_reg_clks),
+};
+
+static const struct mtk_gate_regs vlpcfg_reg_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_VLPCFG_REG_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &vlpcfg_reg_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv, _flags)
+
+#define GATE_VLPCFG_REG(_id, _name, _parent, _shift) \
+ GATE_VLPCFG_REG_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate vlpcfg_reg_clks[] = {
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SCP, "vlpcfg_scp",
+ "vlp_scp_sel", 28, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_RG_R_APXGPT_26M, "vlpcfg_r_apxgpt_26m",
+ "clk26m", 24, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DPMSRCK_TEST, "vlpcfg_dpmsrck_test",
+ "clk26m", 23, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, "vlpcfg_dpmsrrtc_test",
+ "clk32k", 22, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DPMSRULP_TEST, "vlpcfg_dpmsrulp_test",
+ "osc_d10", 21, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SPMI_P_MST, "vlpcfg_spmi_p",
+ "vlp_spmi_p_sel", 20, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SPMI_P_MST_32K, "vlpcfg_spmi_p_32k",
+ "clk32k", 18, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, "vlpcfg_pmif_spmi_p_sys",
+ "vlp_pwrap_ulposc_sel", 13, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PMIF_SPMI_P_TMR, "vlpcfg_pmif_spmi_p_tmr",
+ "vlp_pwrap_ulposc_sel", 12, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG(CLK_VLPCFG_REG_PMIF_SPMI_M_SYS, "vlpcfg_pmif_spmi_m_sys",
+ "vlp_pwrap_ulposc_sel", 11),
+ GATE_VLPCFG_REG(CLK_VLPCFG_REG_PMIF_SPMI_M_TMR, "vlpcfg_pmif_spmi_m_tmr",
+ "vlp_pwrap_ulposc_sel", 10),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_DVFSRC, "vlpcfg_dvfsrc",
+ "vlp_dvfsrc_sel", 9, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_PWM_VLP, "vlpcfg_pwm_vlp",
+ "vlp_pwm_vlp_sel", 8, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SRCK, "vlpcfg_srck",
+ "vlp_srck_sel", 7, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_F26M, "vlpcfg_sspm_f26m",
+ "vlp_sspm_f26m_sel", 4, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_F32K, "vlpcfg_sspm_f32k",
+ "clk32k", 3, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_SSPM_ULPOSC, "vlpcfg_sspm_ulposc",
+ "vlp_sspm_ulposc_sel", 2, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_VLP_32K_COM, "vlpcfg_vlp_32k_com",
+ "clk32k", 1, CLK_IS_CRITICAL),
+ GATE_VLPCFG_REG_FLAGS(CLK_VLPCFG_REG_VLP_26M_COM, "vlpcfg_vlp_26m_com",
+ "clk26m", 0, CLK_IS_CRITICAL),
+};
+
+static const struct mtk_clk_desc vlpcfg_reg_mcd = {
+ .clks = vlpcfg_reg_clks,
+ .num_clks = ARRAY_SIZE(vlpcfg_reg_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_vlpcfg[] = {
+ { .compatible = "mediatek,mt8189-vlpcfg", .data = &vlpcfg_reg_mcd },
+ { .compatible = "mediatek,mt8189-vlpcfg-ao", .data = &vlpcfg_ao_reg_mcd },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8189_vlpcfg_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-vlpcfg",
+ .of_match_table = of_match_clk_mt8189_vlpcfg,
+ },
+};
+module_platform_driver(clk_mt8189_vlpcfg_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 vlpcfg clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 10/15] clk: mediatek: Add MT8189 bus clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (8 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 09/15] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 11/15] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
` (4 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 bus clock controller,
which provides clock gate control for infra/peri IPs
(such as spi, uart, msdc, flashif ...).
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 11 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-bus.c | 200 ++++++++++++++++++++++++++++++++++
3 files changed, 212 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index f67dfb6cd019..8eba45f05968 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -828,6 +828,17 @@ config COMMON_CLK_MT8189
with the MediaTek MT8189 hardware capabilities, providing efficient management of
clock speeds and power consumption.
+config COMMON_CLK_MT8189_BUS
+ tristate "Clock driver for MediaTek MT8189 bus"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this configuration option to support the clock framework for
+ MediaTek MT8189 SoC bus clocks. It includes the necessary clock
+ management for bus-related peripherals and interconnects within the
+ MT8189 chipset, ensuring that all bus-related components receive the
+ correct clock signals for optimal performance.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index d9279b237b7b..aabfb42cb1b2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -125,6 +125,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \
clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o
+obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-bus.c b/drivers/clk/mediatek/clk-mt8189-bus.c
new file mode 100644
index 000000000000..494f25e85d11
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-bus.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs ifrao0_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs ifrao1_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs ifrao2_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+#define GATE_IFRAO0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ifrao0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_IFRAO1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ifrao1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_IFRAO2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ifrao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ifrao_clks[] = {
+ /* IFRAO0 */
+ GATE_IFRAO0(CLK_IFRAO_CQ_DMA_FPC, "ifrao_dma", "ap2con", 28),
+ /* IFRAO1 */
+ GATE_IFRAO1(CLK_IFRAO_DEBUGSYS, "ifrao_debugsys", "axi_sel", 24),
+ GATE_IFRAO1(CLK_IFRAO_DBG_TRACE, "ifrao_dbg_trace", "axi_sel", 29),
+ /* IFRAO2 */
+ GATE_IFRAO2(CLK_IFRAO_CQ_DMA, "ifrao_cq_dma", "axi_sel", 27),
+};
+
+static const struct mtk_clk_desc ifrao_mcd = {
+ .clks = ifrao_clks,
+ .num_clks = ARRAY_SIZE(ifrao_clks),
+};
+
+static const struct mtk_gate_regs perao0_cg_regs = {
+ .set_ofs = 0x24,
+ .clr_ofs = 0x28,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs perao1_cg_regs = {
+ .set_ofs = 0x2c,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs perao2_cg_regs = {
+ .set_ofs = 0x34,
+ .clr_ofs = 0x38,
+ .sta_ofs = 0x18,
+};
+
+#define GATE_PERAO0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &perao0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_PERAO1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &perao1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_PERAO2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &perao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate perao_clks[] = {
+ /* PERAO0 */
+ GATE_PERAO0(CLK_PERAO_UART0, "perao_uart0", "uart_sel", 0),
+ GATE_PERAO0(CLK_PERAO_UART1, "perao_uart1", "uart_sel", 1),
+ GATE_PERAO0(CLK_PERAO_UART2, "perao_uart2", "uart_sel", 2),
+ GATE_PERAO0(CLK_PERAO_UART3, "perao_uart3", "uart_sel", 3),
+ GATE_PERAO0(CLK_PERAO_PWM_H, "perao_pwm_h", "axi_peri_sel", 4),
+ GATE_PERAO0(CLK_PERAO_PWM_B, "perao_pwm_b", "pwm_sel", 5),
+ GATE_PERAO0(CLK_PERAO_PWM_FB1, "perao_pwm_fb1", "pwm_sel", 6),
+ GATE_PERAO0(CLK_PERAO_PWM_FB2, "perao_pwm_fb2", "pwm_sel", 7),
+ GATE_PERAO0(CLK_PERAO_PWM_FB3, "perao_pwm_fb3", "pwm_sel", 8),
+ GATE_PERAO0(CLK_PERAO_PWM_FB4, "perao_pwm_fb4", "pwm_sel", 9),
+ GATE_PERAO0(CLK_PERAO_DISP_PWM0, "perao_disp_pwm0", "disp_pwm_sel", 10),
+ GATE_PERAO0(CLK_PERAO_DISP_PWM1, "perao_disp_pwm1", "disp_pwm_sel", 11),
+ GATE_PERAO0(CLK_PERAO_SPI0_B, "perao_spi0_b", "spi0_sel", 12),
+ GATE_PERAO0(CLK_PERAO_SPI1_B, "perao_spi1_b", "spi1_sel", 13),
+ GATE_PERAO0(CLK_PERAO_SPI2_B, "perao_spi2_b", "spi2_sel", 14),
+ GATE_PERAO0(CLK_PERAO_SPI3_B, "perao_spi3_b", "spi3_sel", 15),
+ GATE_PERAO0(CLK_PERAO_SPI4_B, "perao_spi4_b", "spi4_sel", 16),
+ GATE_PERAO0(CLK_PERAO_SPI5_B, "perao_spi5_b", "spi5_sel", 17),
+ GATE_PERAO0(CLK_PERAO_SPI0_H, "perao_spi0_h", "axi_peri_sel", 18),
+ GATE_PERAO0(CLK_PERAO_SPI1_H, "perao_spi1_h", "axi_peri_sel", 19),
+ GATE_PERAO0(CLK_PERAO_SPI2_H, "perao_spi2_h", "axi_peri_sel", 20),
+ GATE_PERAO0(CLK_PERAO_SPI3_H, "perao_spi3_h", "axi_peri_sel", 21),
+ GATE_PERAO0(CLK_PERAO_SPI4_H, "perao_spi4_h", "axi_peri_sel", 22),
+ GATE_PERAO0(CLK_PERAO_SPI5_H, "perao_spi5_h", "axi_peri_sel", 23),
+ GATE_PERAO0(CLK_PERAO_AXI, "perao_axi", "mem_sub_peri_sel", 24),
+ GATE_PERAO0(CLK_PERAO_AHB_APB, "perao_ahb_apb", "axi_peri_sel", 25),
+ GATE_PERAO0(CLK_PERAO_TL, "perao_tl", "pcie_mac_tl_sel", 26),
+ GATE_PERAO0(CLK_PERAO_REF, "perao_ref", "pcie_f26m", 27),
+ GATE_PERAO0(CLK_PERAO_I2C, "perao_i2c", "axi_peri_sel", 28),
+ GATE_PERAO0(CLK_PERAO_DMA_B, "perao_dma_b", "axi_peri_sel", 29),
+ /* PERAO1 */
+ GATE_PERAO1(CLK_PERAO_SSUSB0_REF, "perao_ssusb0_ref", "usb2_26m_p0_en", 1),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_FRMCNT, "perao_ssusb0_frmcnt", "fmcnt_p0_en", 2),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_SYS, "perao_ssusb0_sys", "usb_p0_sel", 4),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_XHCI, "perao_ssusb0_xhci", "ssusb_xhci_p0_sel", 5),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_F, "perao_ssusb0_f", "axi_peri_sel", 6),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_H, "perao_ssusb0_h", "axi_peri_sel", 7),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_REF, "perao_ssusb1_ref", "usb2_26m_p1_en", 8),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_FRMCNT, "perao_ssusb1_frmcnt", "fmcnt_p1_en", 9),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_SYS, "perao_ssusb1_sys", "usb_p1_sel", 11),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_XHCI, "perao_ssusb1_xhci", "ssusb_xhci_p1_sel", 12),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_F, "perao_ssusb1_f", "axi_peri_sel", 13),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_H, "perao_ssusb1_h", "axi_peri_sel", 14),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_REF, "perao_ssusb2_ref", "usb2_26m_p2_en", 15),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_FRMCNT, "perao_ssusb2_frmcnt", "fmcnt_p2_en", 16),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_SYS, "perao_ssusb2_sys", "usb_p2_sel", 18),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_XHCI, "perao_ssusb2_xhci", "ssusb_xhci_p2_sel", 19),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_F, "perao_ssusb2_f", "axi_peri_sel", 20),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_H, "perao_ssusb2_h", "axi_peri_sel", 21),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_REF, "perao_ssusb3_ref", "usb2_26m_p3_en", 23),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_FRMCNT, "perao_ssusb3_frmcnt", "fmcnt_p3_en", 24),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_SYS, "perao_ssusb3_sys", "usb_p3_sel", 26),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_XHCI, "perao_ssusb3_xhci", "ssusb_xhci_p3_sel", 27),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_F, "perao_ssusb3_f", "axi_peri_sel", 28),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_H, "perao_ssusb3_h", "axi_peri_sel", 29),
+ /* PERAO2 */
+ GATE_PERAO2(CLK_PERAO_SSUSB4_REF, "perao_ssusb4_ref", "usb2_26m_p4_en", 0),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_FRMCNT, "perao_ssusb4_frmcnt", "fmcnt_p4_en", 1),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_SYS, "perao_ssusb4_sys", "usb_p4_sel", 3),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_XHCI, "perao_ssusb4_xhci", "ssusb_xhci_p4_sel", 4),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_F, "perao_ssusb4_f", "axi_peri_sel", 5),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_H, "perao_ssusb4_h", "axi_peri_sel", 6),
+ GATE_PERAO2(CLK_PERAO_MSDC0, "perao_msdc0", "msdc50_0_sel", 7),
+ GATE_PERAO2(CLK_PERAO_MSDC0_H, "perao_msdc0_h", "msdc5hclk_sel", 8),
+ GATE_PERAO2(CLK_PERAO_MSDC0_FAES, "perao_msdc0_faes", "aes_msdcfde_sel", 9),
+ GATE_PERAO2(CLK_PERAO_MSDC0_MST_F, "perao_msdc0_mst_f", "axi_peri_sel", 10),
+ GATE_PERAO2(CLK_PERAO_MSDC0_SLV_H, "perao_msdc0_slv_h", "axi_peri_sel", 11),
+ GATE_PERAO2(CLK_PERAO_MSDC1, "perao_msdc1", "msdc30_1_sel", 12),
+ GATE_PERAO2(CLK_PERAO_MSDC1_H, "perao_msdc1_h", "msdc30_1_h_sel", 13),
+ GATE_PERAO2(CLK_PERAO_MSDC1_MST_F, "perao_msdc1_mst_f", "axi_peri_sel", 14),
+ GATE_PERAO2(CLK_PERAO_MSDC1_SLV_H, "perao_msdc1_slv_h", "axi_peri_sel", 15),
+ GATE_PERAO2(CLK_PERAO_MSDC2, "perao_msdc2", "msdc30_2_sel", 16),
+ GATE_PERAO2(CLK_PERAO_MSDC2_H, "perao_msdc2_h", "msdc30_2_h_sel", 17),
+ GATE_PERAO2(CLK_PERAO_MSDC2_MST_F, "perao_msdc2_mst_f", "axi_peri_sel", 18),
+ GATE_PERAO2(CLK_PERAO_MSDC2_SLV_H, "perao_msdc2_slv_h", "axi_peri_sel", 19),
+ GATE_PERAO2(CLK_PERAO_SFLASH, "perao_sflash", "sflash_sel", 20),
+ GATE_PERAO2(CLK_PERAO_SFLASH_F, "perao_sflash_f", "axi_peri_sel", 21),
+ GATE_PERAO2(CLK_PERAO_SFLASH_H, "perao_sflash_h", "axi_peri_sel", 22),
+ GATE_PERAO2(CLK_PERAO_SFLASH_P, "perao_sflash_p", "axi_peri_sel", 23),
+ GATE_PERAO2(CLK_PERAO_AUDIO0, "perao_audio0", "axi_peri_sel", 24),
+ GATE_PERAO2(CLK_PERAO_AUDIO1, "perao_audio1", "axi_peri_sel", 25),
+ GATE_PERAO2(CLK_PERAO_AUDIO2, "perao_audio2", "aud_intbus_sel", 26),
+ GATE_PERAO2(CLK_PERAO_AUXADC_26M, "perao_auxadc_26m", "clk26m", 27),
+};
+
+static const struct mtk_clk_desc perao_mcd = {
+ .clks = perao_clks,
+ .num_clks = ARRAY_SIZE(perao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_bus[] = {
+ { .compatible = "mediatek,mt8189-infra-ao", .data = &ifrao_mcd },
+ { .compatible = "mediatek,mt8189-peri-ao", .data = &perao_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_bus);
+
+static struct platform_driver clk_mt8189_bus_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-bus",
+ .of_match_table = of_match_clk_mt8189_bus,
+ },
+};
+module_platform_driver(clk_mt8189_bus_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 bus/peripheral clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 11/15] clk: mediatek: Add MT8189 dbgao clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (9 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 10/15] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 12/15] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
` (3 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 dbgao clock controller,
which provides clock gate control for debug-system.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 10 ++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-dbgao.c | 98 +++++++++++++++++++++++++++++++++
3 files changed, 109 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 8eba45f05968..635b0109ec07 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -839,6 +839,16 @@ config COMMON_CLK_MT8189_BUS
MT8189 chipset, ensuring that all bus-related components receive the
correct clock signals for optimal performance.
+config COMMON_CLK_MT8189_DBGAO
+ tristate "Clock driver for MediaTek MT8189 debug ao"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock management for the debug function
+ on MediaTek MT8189 SoCs. This includes enabling and disabling
+ vcore debug system clocks. If you want to control its clocks, say Y or M
+ to include this driver in your kernel build.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index aabfb42cb1b2..6ab6df7ebf2a 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -126,6 +126,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \
clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o
obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
+obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-dbgao.c b/drivers/clk/mediatek/clk-mt8189-dbgao.c
new file mode 100644
index 000000000000..40307bdc93eb
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-dbgao.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs dbgao_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+#define GATE_DBGAO(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dbgao_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate dbgao_clks[] = {
+ GATE_DBGAO(CLK_DBGAO_ATB_EN, "dbgao_atb_en", "atb_sel", 0),
+};
+
+static const struct mtk_clk_desc dbgao_mcd = {
+ .clks = dbgao_clks,
+ .num_clks = ARRAY_SIZE(dbgao_clks),
+};
+
+static const struct mtk_gate_regs dem0_cg_regs = {
+ .set_ofs = 0x2c,
+ .clr_ofs = 0x2c,
+ .sta_ofs = 0x2c,
+};
+
+static const struct mtk_gate_regs dem1_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate_regs dem2_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+#define GATE_DEM0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dem0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_DEM1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dem1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_DEM2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dem2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate dem_clks[] = {
+ /* DEM0 */
+ GATE_DEM0(CLK_DEM_BUSCLK_EN, "dem_busclk_en", "axi_sel", 0),
+ /* DEM1 */
+ GATE_DEM1(CLK_DEM_SYSCLK_EN, "dem_sysclk_en", "axi_sel", 0),
+ /* DEM2 */
+ GATE_DEM2(CLK_DEM_ATB_EN, "dem_atb_en", "atb_sel", 0),
+};
+
+static const struct mtk_clk_desc dem_mcd = {
+ .clks = dem_clks,
+ .num_clks = ARRAY_SIZE(dem_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_dbgao[] = {
+ { .compatible = "mediatek,mt8189-dbg-ao", .data = &dbgao_mcd },
+ { .compatible = "mediatek,mt8189-dem", .data = &dem_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dbgao);
+
+static struct platform_driver clk_mt8189_dbgao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-dbgao",
+ .of_match_table = of_match_clk_mt8189_dbgao,
+ },
+};
+module_platform_driver(clk_mt8189_dbgao_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 dbgao system clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 12/15] clk: mediatek: Add MT8189 dvfsrc clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (10 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 11/15] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 13/15] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
` (2 subsequent siblings)
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 dvfsrc clock controller,
which provides clock gate control for dram dvfs.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 10 ++++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 58 ++++++++++++++++++++++++++++++++
3 files changed, 69 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 635b0109ec07..245d3b83b5d3 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -849,6 +849,16 @@ config COMMON_CLK_MT8189_DBGAO
vcore debug system clocks. If you want to control its clocks, say Y or M
to include this driver in your kernel build.
+config COMMON_CLK_MT8189_DVFSRC
+ tristate "Clock driver for MediaTek MT8189 dvfsrc"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock management for the dvfsrc
+ on MediaTek MT8189 SoCs. This includes enabling and disabling
+ vcore dvfs clocks. If you want to control its clocks, say Y or M
+ to include this driver in your kernel build.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6ab6df7ebf2a..4dbfc9ac83ba 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -127,6 +127,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o
clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o
obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
+obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-dvfsrc.c b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c
new file mode 100644
index 000000000000..37b81dc0b882
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs dvfsrc_top_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_DVFSRC_TOP_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &dvfsrc_top_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv, _flags)
+
+static const struct mtk_gate dvfsrc_top_clks[] = {
+ GATE_DVFSRC_TOP_FLAGS(CLK_DVFSRC_TOP_DVFSRC_EN, "dvfsrc_dvfsrc_en",
+ "clk26m", 0, CLK_IS_CRITICAL),
+};
+
+static const struct mtk_clk_desc dvfsrc_top_mcd = {
+ .clks = dvfsrc_top_clks,
+ .num_clks = ARRAY_SIZE(dvfsrc_top_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_dvfsrc[] = {
+ { .compatible = "mediatek,mt8189-dvfsrc-top", .data = &dvfsrc_top_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dvfsrc);
+
+static struct platform_driver clk_mt8189_dvfsrc_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-dvfsrc",
+ .of_match_table = of_match_clk_mt8189_dvfsrc,
+ },
+};
+module_platform_driver(clk_mt8189_dvfsrc_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 dvfsrc clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 13/15] clk: mediatek: Add MT8189 i2c clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (11 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 12/15] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 14/15] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 15/15] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 i2c clock controller,
which provides clock gate control for i2c.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 13 ++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-iic.c | 122 ++++++++++++++++++++++++++++++++++
3 files changed, 136 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 245d3b83b5d3..bba631138b07 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -859,6 +859,19 @@ config COMMON_CLK_MT8189_DVFSRC
vcore dvfs clocks. If you want to control its clocks, say Y or M
to include this driver in your kernel build.
+config COMMON_CLK_MT8189_IIC
+ tristate "Clock driver for MediaTek MT8189 iic"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this option to support the clock framework for MediaTek MT8189
+ integrated circuits (iic). This driver is responsible for managing
+ clock sources, dividers, and gates specifically designed for MT8189
+ SoCs. Enabling this driver ensures that the system can correctly
+ manage clock frequencies and power for various components within
+ the MT8189 chipset, improving the overall performance and power
+ efficiency of the device.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 4dbfc9ac83ba..bfc075023d9b 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -128,6 +128,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
+obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-iic.c b/drivers/clk/mediatek/clk-mt8189-iic.c
new file mode 100644
index 000000000000..80a01706791a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-iic.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs impe_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPE(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &impe_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate impe_clks[] = {
+ GATE_IMPE(CLK_IMPE_I2C0, "impe_i2c0", "i2c_sel", 0),
+ GATE_IMPE(CLK_IMPE_I2C1, "impe_i2c1", "i2c_sel", 1),
+};
+
+static const struct mtk_clk_desc impe_mcd = {
+ .clks = impe_clks,
+ .num_clks = ARRAY_SIZE(impe_clks),
+};
+
+static const struct mtk_gate_regs impen_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPEN(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &impen_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate impen_clks[] = {
+ GATE_IMPEN(CLK_IMPEN_I2C7, "impen_i2c7", "i2c_sel", 0),
+ GATE_IMPEN(CLK_IMPEN_I2C8, "impen_i2c8", "i2c_sel", 1),
+};
+
+static const struct mtk_clk_desc impen_mcd = {
+ .clks = impen_clks,
+ .num_clks = ARRAY_SIZE(impen_clks),
+};
+
+static const struct mtk_gate_regs imps_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPS(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &imps_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate imps_clks[] = {
+ GATE_IMPS(CLK_IMPS_I2C3, "imps_i2c3", "i2c_sel", 0),
+ GATE_IMPS(CLK_IMPS_I2C4, "imps_i2c4", "i2c_sel", 1),
+ GATE_IMPS(CLK_IMPS_I2C5, "imps_i2c5", "i2c_sel", 2),
+ GATE_IMPS(CLK_IMPS_I2C6, "imps_i2c6", "i2c_sel", 3),
+};
+
+static const struct mtk_clk_desc imps_mcd = {
+ .clks = imps_clks,
+ .num_clks = ARRAY_SIZE(imps_clks),
+};
+
+static const struct mtk_gate_regs impws_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPWS(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &impws_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate impws_clks[] = {
+ GATE_IMPWS(CLK_IMPWS_I2C2, "impws_i2c2", "i2c_sel", 0),
+};
+
+static const struct mtk_clk_desc impws_mcd = {
+ .clks = impws_clks,
+ .num_clks = ARRAY_SIZE(impws_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_iic[] = {
+ { .compatible = "mediatek,mt8189-iic-wrap-e", .data = &impe_mcd },
+ { .compatible = "mediatek,mt8189-iic-wrap-en", .data = &impen_mcd },
+ { .compatible = "mediatek,mt8189-iic-wrap-s", .data = &imps_mcd },
+ { .compatible = "mediatek,mt8189-iic-wrap-ws", .data = &impws_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_iic);
+
+static struct platform_driver clk_mt8189_iic_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-iic",
+ .of_match_table = of_match_clk_mt8189_iic,
+ },
+};
+module_platform_driver(clk_mt8189_iic_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 iic clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 14/15] clk: mediatek: Add MT8189 scp clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (12 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 13/15] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 15/15] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 scp clock controller,
which provides clock gate control for System Control Processor.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 10 +++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-scp.c | 77 +++++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index bba631138b07..919a916f1f4f 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -872,6 +872,16 @@ config COMMON_CLK_MT8189_IIC
the MT8189 chipset, improving the overall performance and power
efficiency of the device.
+config COMMON_CLK_MT8189_SCP
+ tristate "Clock driver for MediaTek MT8189 scp"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock framework for the System Control
+ Processor (SCP) in the MediaTek MT8189 SoC. This includes clock
+ management for SCP-related features, ensuring proper clock
+ distribution and gating for power efficiency and functionality.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index bfc075023d9b..a3a93a16b369 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -129,6 +129,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o
+obj-$(CONFIG_COMMON_CLK_MT8189_SCP) += clk-mt8189-scp.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-scp.c b/drivers/clk/mediatek/clk-mt8189-scp.c
new file mode 100644
index 000000000000..75197cd98b52
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-scp.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs scp_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_SCP(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &scp_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate scp_clks[] = {
+ GATE_SCP(CLK_SCP_SET_SPI0, "scp_set_spi0", "clk26m", 0),
+ GATE_SCP(CLK_SCP_SET_SPI1, "scp_set_spi1", "clk26m", 1),
+};
+
+static const struct mtk_clk_desc scp_mcd = {
+ .clks = scp_clks,
+ .num_clks = ARRAY_SIZE(scp_clks),
+};
+
+static const struct mtk_gate_regs scp_iic_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_SCP_IIC(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &scp_iic_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate scp_iic_clks[] = {
+ GATE_SCP_IIC(CLK_SCP_IIC_I2C0_W1S, "scp_iic_i2c0_w1s", "vlp_scp_iic_sel", 0),
+ GATE_SCP_IIC(CLK_SCP_IIC_I2C1_W1S, "scp_iic_i2c1_w1s", "vlp_scp_iic_sel", 1),
+};
+
+static const struct mtk_clk_desc scp_iic_mcd = {
+ .clks = scp_iic_clks,
+ .num_clks = ARRAY_SIZE(scp_iic_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_scp[] = {
+ { .compatible = "mediatek,mt8189-scp-clk", .data = &scp_mcd },
+ { .compatible = "mediatek,mt8189-scp-i2c-clk", .data = &scp_iic_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_scp);
+
+static struct platform_driver clk_mt8189_scp_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-scp",
+ .of_match_table = of_match_clk_mt8189_scp,
+ },
+};
+module_platform_driver(clk_mt8189_scp_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 scp clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 15/15] clk: mediatek: Add MT8189 ufs clock support
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
` (13 preceding siblings ...)
2026-07-01 13:11 ` [PATCH 14/15] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
@ 2026-07-01 13:11 ` Louis-Alexis Eyraud
14 siblings, 0 replies; 18+ messages in thread
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
Add support for the MT8189 ufs clock controller,
which provides clock gate control for Universal Flash Storage.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 12 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-ufs.c | 133 ++++++++++++++++++++++++++++++++++
3 files changed, 146 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 919a916f1f4f..34a270a377cc 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -882,6 +882,18 @@ config COMMON_CLK_MT8189_SCP
management for SCP-related features, ensuring proper clock
distribution and gating for power efficiency and functionality.
+config COMMON_CLK_MT8189_UFS
+ tristate "Clock driver for MediaTek MT8189 ufs"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock management for the Universal Flash
+ Storage (UFS) interface on MediaTek MT8189 SoCs. This includes
+ clock sources, dividers, and gates that are specific to the UFS
+ feature of the MT8189 platform. It is recommended to enable this
+ option if the system includes a UFS device that relies on the MT8189
+ SoC for clock management.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a3a93a16b369..1aa9f4265225 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -130,6 +130,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o
obj-$(CONFIG_COMMON_CLK_MT8189_SCP) += clk-mt8189-scp.o
+obj-$(CONFIG_COMMON_CLK_MT8189_UFS) += clk-mt8189-ufs.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-ufs.c b/drivers/clk/mediatek/clk-mt8189-ufs.c
new file mode 100644
index 000000000000..85afab04420f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-ufs.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+#include <dt-bindings/reset/mediatek,mt8189-resets.h>
+
+#define MT8189_UFSCFG_AO_RST0_SET_OFFSET 0x48
+#define MT8189_UFSCFG_PDN_RST0_SET_OFFSET 0x48
+
+static const struct mtk_gate_regs ufscfg_ao_reg_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_UFSCFG_AO_REG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ufscfg_ao_reg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ufscfg_ao_reg_clks[] = {
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM,
+ "ufscfg_ao_unipro_tx_sym", "clk26m", 1),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0,
+ "ufscfg_ao_unipro_rx_sym0", "clk26m", 2),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1,
+ "ufscfg_ao_unipro_rx_sym1", "clk26m", 3),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_SYS,
+ "ufscfg_ao_unipro_sys", "ufs_sel", 4),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_SAP_CFG,
+ "ufscfg_ao_u_sap_cfg", "clk26m", 5),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS,
+ "ufscfg_ao_u_phy_ahb_s_bus", "axi_u_sel", 6),
+};
+
+static u16 ufscfg_ao_rst_ofs[] = {
+ MT8189_UFSCFG_AO_RST0_SET_OFFSET,
+};
+
+static u16 ufscfg_ao_rst_idx_map[] = {
+ [MT8189_UFSAO_RST_UFS_MPHY] = 8,
+};
+
+static const struct mtk_clk_rst_desc ufscfg_ao_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_ofs = ufscfg_ao_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(ufscfg_ao_rst_ofs),
+ .rst_idx_map = ufscfg_ao_rst_idx_map,
+ .rst_idx_map_nr = ARRAY_SIZE(ufscfg_ao_rst_idx_map),
+};
+
+static const struct mtk_clk_desc ufscfg_ao_reg_mcd = {
+ .clks = ufscfg_ao_reg_clks,
+ .num_clks = ARRAY_SIZE(ufscfg_ao_reg_clks),
+ .rst_desc = &ufscfg_ao_rst_desc,
+};
+
+static const struct mtk_gate_regs ufscfg_pdn_reg_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_UFSCFG_PDN_REG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ufscfg_pdn_reg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ufscfg_pdn_reg_clks[] = {
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_UFS,
+ "ufscfg_ufshci_ufs", "ufs_sel", 0),
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_AES,
+ "ufscfg_ufshci_aes", "aes_ufsfde_sel", 1),
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AHB,
+ "ufscfg_ufshci_u_ahb", "axi_u_sel", 3),
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AXI,
+ "ufscfg_ufshci_u_axi", "mem_sub_u_sel", 5),
+};
+
+static u16 ufscfg_pdn_rst_ofs[] = {
+ MT8189_UFSCFG_PDN_RST0_SET_OFFSET,
+};
+
+static u16 ufscfg_pdn_rst_idx_map[] = {
+ [MT8189_UFSPDN_RST_UFS_UNIPRO] = 0,
+ [MT8189_UFSPDN_RST_UFS_CRYPTO] = 1,
+ [MT8189_UFSPDN_RST_UFS_HCI] = 2,
+};
+
+static const struct mtk_clk_rst_desc ufscfg_pdn_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_ofs = ufscfg_pdn_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(ufscfg_pdn_rst_ofs),
+ .rst_idx_map = ufscfg_pdn_rst_idx_map,
+ .rst_idx_map_nr = ARRAY_SIZE(ufscfg_pdn_rst_idx_map),
+};
+
+static const struct mtk_clk_desc ufscfg_pdn_reg_mcd = {
+ .clks = ufscfg_pdn_reg_clks,
+ .num_clks = ARRAY_SIZE(ufscfg_pdn_reg_clks),
+ .rst_desc = &ufscfg_pdn_rst_desc,
+};
+
+static const struct of_device_id of_match_clk_mt8189_ufs[] = {
+ { .compatible = "mediatek,mt8189-ufscfg-ao", .data = &ufscfg_ao_reg_mcd },
+ { .compatible = "mediatek,mt8189-ufscfg-pdn", .data = &ufscfg_pdn_reg_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_ufs);
+
+static struct platform_driver clk_mt8189_ufs_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-ufs",
+ .of_match_table = of_match_clk_mt8189_ufs,
+ },
+};
+module_platform_driver(clk_mt8189_ufs_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 ufs clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186
2026-07-01 13:11 ` [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
@ 2026-07-01 16:24 ` Rob Herring (Arm)
2026-07-01 19:33 ` Rob Herring
1 sibling, 0 replies; 18+ messages in thread
From: Rob Herring (Arm) @ 2026-07-01 16:24 UTC (permalink / raw)
To: Louis-Alexis Eyraud
Cc: linux-kernel, Richard Cochran, Chun-Jie Chen, netdev,
AngeloGioacchino Del Regno, Brian Masney, Philipp Zabel,
devicetree, linux-arm-kernel, Stephen Boyd, linux-mediatek,
Krzysztof Kozlowski, kernel, Michael Turquette, Edward-JW Yang,
Matthias Brugger, Conor Dooley, linux-clk
On Wed, 01 Jul 2026 15:11:07 +0200, Louis-Alexis Eyraud wrote:
> Regroup the MT8188 clock and system clock dt-bindings into MT8186 ones
> to ease maintainability and have common files for several currently
> supported SoC or new future ones, that have the same kind of clock
> controller design.
>
> Note:
> The `#clock-cells` property is a required property for all compatibles
> declared in MT8188 clock and system clock dt-bindings but not in MT8186
> ones.
> To avoid ABI breakage, conditional blocks to check this requirement
> for MT8188 compatibles are added, rather than enforcing it for MT8186
> compatibles.
>
> Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
> ---
> .../bindings/clock/mediatek,mt8186-clock.yaml | 82 ++++++++++++++++++-
> .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 20 ++++-
> .../bindings/clock/mediatek,mt8188-clock.yaml | 93 ----------------------
> .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 --------------
> 4 files changed, 100 insertions(+), 153 deletions(-)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml:62:1: [warning] too many blank lines (2 > 1) (empty-lines)
dtschema/dtc warnings/errors:
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701-mt8189-clocks-system-base-v1-2-2b048feea50a@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186
2026-07-01 13:11 ` [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-07-01 16:24 ` Rob Herring (Arm)
@ 2026-07-01 19:33 ` Rob Herring
1 sibling, 0 replies; 18+ messages in thread
From: Rob Herring @ 2026-07-01 19:33 UTC (permalink / raw)
To: Louis-Alexis Eyraud
Cc: Michael Turquette, Stephen Boyd, Brian Masney,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran, kernel, linux-clk, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, netdev
On Wed, Jul 01, 2026 at 03:11:07PM +0200, Louis-Alexis Eyraud wrote:
> Regroup the MT8188 clock and system clock dt-bindings into MT8186 ones
> to ease maintainability and have common files for several currently
> supported SoC or new future ones, that have the same kind of clock
> controller design.
>
> Note:
> The `#clock-cells` property is a required property for all compatibles
> declared in MT8188 clock and system clock dt-bindings but not in MT8186
> ones.
> To avoid ABI breakage, conditional blocks to check this requirement
> for MT8188 compatibles are added, rather than enforcing it for MT8186
> compatibles.
If the existing DTs are just wrong, then I would just make #clock-cells
required. But please update the .dts files so the warnings don't grow.
The grouping I would do here is:
- clock controller only
- reset controller only
- both clock and reset controller
That should avoid any if/then schemas.
Rob
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2026-07-01 19:58 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-07-01 13:11 [PATCH 00/15] MT8189: Add support for system and base clock controllers Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 01/15] dt-bindings: clock: mediatek: reorder MT8186 compatibles Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 Louis-Alexis Eyraud
2026-07-01 16:24 ` Rob Herring (Arm)
2026-07-01 19:33 ` Rob Herring
2026-07-01 13:11 ` [PATCH 03/15] dt-bindings: clock: mediatek: regroup MT8192 " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 04/15] dt-bindings: clock: mediatek: regroup MT8195 " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 05/15] dt-bindings: clock: mediatek: Add MT8189 clocks Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 06/15] clk: mediatek: Add MT8189 apmixedsys clock support Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 07/15] clk: mediatek: Add MT8189 topckgen " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 08/15] clk: mediatek: Add MT8189 vlpckgen " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 09/15] clk: mediatek: Add MT8189 vlpcfg " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 10/15] clk: mediatek: Add MT8189 bus " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 11/15] clk: mediatek: Add MT8189 dbgao " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 12/15] clk: mediatek: Add MT8189 dvfsrc " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 13/15] clk: mediatek: Add MT8189 i2c " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 14/15] clk: mediatek: Add MT8189 scp " Louis-Alexis Eyraud
2026-07-01 13:11 ` [PATCH 15/15] clk: mediatek: Add MT8189 ufs " Louis-Alexis Eyraud
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