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From: Jason Gunthorpe <jgg@nvidia.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: iommu@lists.linux.dev, "Joerg Roedel (AMD)" <joro@8bytes.org>,
	Jean-Philippe Brucker <jpb@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	Robin Murphy <robin.murphy@arm.com>,
	Will Deacon <will@kernel.org>,
	David Matlack <dmatlack@google.com>,
	Pasha Tatashin <pasha.tatashin@soleen.com>,
	patches@lists.linux.dev, Pranjal Shrivastava <praan@google.com>,
	Samiullah Khawaja <skhawaja@google.com>,
	Mostafa Saleh <smostafa@google.com>
Subject: Re: [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation
Date: Wed, 8 Jul 2026 15:27:10 -0300	[thread overview]
Message-ID: <20260708182710.GC422027@nvidia.com> (raw)
In-Reply-To: <ak2qw/dFEixxY/Uj@Asurada-Nvidia>

On Tue, Jul 07, 2026 at 06:41:23PM -0700, Nicolin Chen wrote:
> On Mon, Jul 06, 2026 at 01:26:44PM -0300, Jason Gunthorpe wrote:
> > @@ -2331,8 +2331,8 @@ static struct arm_smmu_cmd arm_smmu_atc_inv_to_cmd(u32 sid, int ssid,
> >  	 * This has the unpleasant side-effect of invalidating all PASID-tagged
> >  	 * ATC entries within the address range.
> >  	 */
> > -	page_start = tlbi->iova >> inval_grain_shift;
> > -	page_end = (tlbi->iova + tlbi->size - 1) >> inval_grain_shift;
> > +	page_start = tlbi->start >> inval_grain_shift;
> > +	page_end = tlbi->last >> inval_grain_shift;
> 
> arm_smmu_domain_inv() in the header passes in start=last=0, but
> it's supposed to flush the entire ATC, right?

Yeah, that's a mistake! The invalidate all needs to set last=ULONG_MAX

        /* Prefilled for invalidate all */
        struct arm_smmu_tlbi tlbi = {
+               .start = 0,
+               .last = ULONG_MAX,

> >  static void arm_smmu_iotlb_sync(struct iommu_domain *domain,
> >  				struct iommu_iotlb_gather *gather)
> >  {
> > +	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
> > +	unsigned int tg = smmu_domain->tgsz_lg2;
> >  	struct arm_smmu_tlbi tlbi = {
> > -		.smmu_domain = to_smmu_domain(domain),
> > -		.iova = gather->start,
> > -		.size = gather->end - gather->start + 1,
> > -		.iopte_granule = gather->pgsize,
> > -		.leaf_only = true,
> > +		.smmu_domain = smmu_domain,
> > +		.start = gather->start,
> > +		.last = gather->end,
> > +		.leaf_levels_bitmap =
> [...]
> > +			BIT((ilog2(gather->pgsize) - tg) / (tg - 3)),
> >  	};
> >  
> >  	if (!gather->pgsize)
> 
> pgsize=0 is checked after ilog2(0).

Yes, but gather->pgsize = 0 also can't happen.. But lets do better:

@@ -4096,13 +4096,13 @@ static void arm_smmu_iotlb_sync(struct iommu_domain *domain,
                .tgsz_lg2 = smmu_domain->tgsz_lg2,
                .start = gather->start,
                .last = gather->end,
-               .leaf_levels_bitmap =
-                       BIT((ilog2(gather->pgsize) - tg) / (tg - 3)),
        };
 
-       if (!gather->pgsize)
+       if (WARN_ON(gather->pgsize < BIT(tg)))
                return;
 
+       tlbi.leaf_levels_bitmap = BIT((ilog2(gather->pgsize) - tg) / (tg - 3));
+
        arm_smmu_domain_tlbi(&tlbi, smmu_domain);
 }


Jason


  reply	other threads:[~2026-07-08 18:27 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-06 16:26 [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 1/8] iommu/arm-smmu-v3: Pass the parameters for the invalidation in a struct Jason Gunthorpe
2026-07-07  3:04   ` Nicolin Chen
2026-07-07 11:18   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 2/8] iommu/arm-smmu-v3: Move pgsize out of arm_smmu_inv Jason Gunthorpe
2026-07-07  3:57   ` Nicolin Chen
2026-07-07 16:15     ` Jason Gunthorpe
2026-07-07 17:21       ` Nicolin Chen
2026-07-08 18:43         ` Jason Gunthorpe
2026-07-07 11:24   ` Mostafa Saleh
2026-07-07 18:08     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 3/8] iommu/arm-smmu-v3: Optimize range invalidation for latency Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 19:13     ` Jason Gunthorpe
2026-07-07 21:07       ` Nicolin Chen
2026-07-07 11:45   ` Mostafa Saleh
2026-07-08  0:10     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 4/8] iommu/arm-smmu-v3: Keep track in the arm_smmu_invs if RIL is used Jason Gunthorpe
2026-07-07  7:27   ` Nicolin Chen
2026-07-07 11:46   ` Mostafa Saleh
2026-07-06 16:26 ` [PATCH v2 5/8] iommu/arm-smmu-v3: Precompute the invalidation commands Jason Gunthorpe
2026-07-07 11:52   ` Mostafa Saleh
2026-07-07 14:58     ` Jason Gunthorpe
2026-07-08  9:00       ` Mostafa Saleh
2026-07-08 13:15         ` Jason Gunthorpe
2026-07-07 20:31   ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 6/8] iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain Jason Gunthorpe
2026-07-07 11:57   ` Mostafa Saleh
2026-07-08 18:09     ` Jason Gunthorpe
2026-07-07 21:51   ` Nicolin Chen
2026-07-08 18:40     ` Jason Gunthorpe
2026-07-06 16:26 ` [PATCH v2 7/8] iommu/arm-smmu-v3: Change how the tlbi describes the invalidation Jason Gunthorpe
2026-07-06 18:00   ` Robin Murphy
2026-07-06 19:45     ` Jason Gunthorpe
2026-07-08  1:41   ` Nicolin Chen
2026-07-08 18:27     ` Jason Gunthorpe [this message]
2026-07-08  5:29   ` Nicolin Chen
2026-07-06 16:26 ` [PATCH v2 8/8] iommu/arm-smmu-v3: Support the DS expansion of RIL's SCALE Jason Gunthorpe
2026-07-07 23:20   ` Nicolin Chen
2026-07-08  0:02     ` Jason Gunthorpe
2026-07-08  2:10       ` Nicolin Chen
2026-07-08 13:05         ` Jason Gunthorpe
2026-07-07 12:25 ` [PATCH v2 0/8] Organize the SMMUv3 invalidation flow so iommupt can use it Mostafa Saleh
2026-07-07 15:00   ` Jason Gunthorpe

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