From: Jiaxing Hu <gahing@gahingwoo.com>
To: heiko@sntech.de
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
andrew@lunn.ch, devicetree@vger.kernel.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 0/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO
Date: Fri, 17 Jul 2026 10:51:43 +1200 [thread overview]
Message-ID: <20260716225143.2544913-1-gahing@gahingwoo.com> (raw)
In-Reply-To: <40552860.10thIPus4b@phil>
> As Rob said in the v2 bindings, please slow down.
> Additionally that is the 2nd "v3" today?
Sorry, both for the pace and for the double v3. The second v3 was not
intentional: my mail provider accepted the first one with SMTP 250 but
then held it without delivering, so when nothing appeared on the list I
resent it. The provider released both copies hours later, so two v3
threads showed up. I have moved off that provider.
I will stop respinning and collect review first. The next version will
wait, will fold in Andrew's rgmii-id feedback after a board re-test, and
will be marked and explained in the cover letter.
Sorry for the noise,
Jiaxing
next prev parent reply other threads:[~2026-07-16 23:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-16 9:50 [PATCH v3 0/2] arm64: dts: rockchip: Add ArmSoM CM5 and CM5-IO Jiaxing Hu
2026-07-16 9:51 ` [PATCH v3 1/2] dt-bindings: arm: " Jiaxing Hu
2026-07-16 9:51 ` [PATCH v3 2/2] arm64: dts: " Jiaxing Hu
2026-07-16 18:42 ` Andrew Lunn
2026-07-16 22:51 ` Jiaxing Hu
2026-07-16 18:35 ` [PATCH v3 0/2] " Heiko Stuebner
2026-07-16 22:51 ` Jiaxing Hu [this message]
-- strict thread matches above, loose matches on Subject: below --
2026-07-16 8:17 Jiaxing Hu
2026-07-16 8:17 ` [PATCH v3 1/2] dt-bindings: arm: " Jiaxing Hu
2026-07-16 8:17 ` [PATCH v3 2/2] arm64: dts: " Jiaxing Hu
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