[PATCH v16 0/7] spi: pxa2xx: Fix PM and interrupt issues on Intel LPSS SPI

[PATCH v16 0/7] spi: pxa2xx: Fix PM and interrupt issues on Intel LPSS SPI

[Shih-Yuan Lee]

This 7-patch series addresses long-standing power management (PM), runtime autosuspend,
and interrupt synchronization regressions in the spi-pxa2xx host controller driver,
specifically targeting Intel Low Power Subsystem (LPSS) SPI controllers and platforms
such as the Apple MacBook8,1.

Specifically, this series:
  - Prevents system hangs and PCIe Completion Timeouts during S3 suspend/resume by
    restoring Intel LPSS private register context (resets and control registers).
  - Resolves race conditions in the shared interrupt handler (ssp_int()) during PM power
    state transitions (RPM_SUSPENDING) by tracking suspend states and guaranteeing
    active hardware clocks prior to MMIO register access.
  - Locks out runtime PM autosuspend for Intel LPSS SPI controllers in PIO mode to avoid
    unclocked MMIO accesses on subsequent transfers.
  - Applies a PCI glue DMI quirk to force PIO mode for Apple MacBook8,1 to work around
    persistent hardware DMA timeouts.
  - Cleanly refactors clock helper functions, PM callback state alignments, and local
    variable conventions across the driver.

Changes in v16:
  - Addressed feedback from Sashiko review on the v15 patchset:
  - Fixed 'bool suspended' field location in spi-pxa2xx.h (moved from Patch 1 to Patch 2).
  - Updated pxa2xx_spi_clk_disable() to set drv_data->clk_enabled = false BEFORE
    calling clk_disable_unprepare(), eliminating an IRQ handler race window on
    multi-core systems.
  - Updated pxa2xx_spi_suspend() and pxa2xx_spi_runtime_suspend() to explicitly
    set drv_data->suspended = true.
  - Fixed pm_runtime_put_sync() in pxa2xx_spi_remove(), moving the PM reference drop
    to before hardware teardown and using pm_runtime_put_noidle() to prevent
    runtime_suspend calls on unclocked hardware.
  - Fixed PM runtime state alignment in pxa2xx_spi_resume() error path using
    pm_runtime_set_suspended().
  - Resolved merge conflicts and renamed remaining 'status' variables to 'ret'
    in suspend/resume handlers.

Changes in v15:
  - Split the large PIO mode PM and interrupt patch (v14 Patch 2) into 4 distinct,
    single-purpose commits (clock helpers, suspended flag, teardown overhaul,
    and autosuspend lockout).
  - Reordered the commits so that PIO PM and interrupt bug fixes are applied
    before disabling DMA on MacBook8,1, satisfying kernel bisection safety.
  - Replaced raw pxa_ssp_disable() calls in PM suspend/remove with
    pxa2xx_spi_off() to respect the MMP2 platform's SSE-disable quirk.
  - Renamed return variables from 'status' to 'ret' in clock helper functions,
    and added a cleanup commit to rename 'status' to 'ret' in the PM and probe
    callbacks to conform to standard coding conventions.

Changes in v14:
  - Addressed feedback from Sashiko review on the v13 patchset for Patch 2:
  - Updated commit message text for Patch 2 to accurately reflect that ssp_int()
    uses drv_data->suspended and drv_data->clk_enabled instead of pm_runtime_get_if_active().
  - Clarified in commit message that active SPI transfers hold a PM reference via
    spi_controller.auto_runtime_pm (pm_runtime_get_sync()), preventing autosuspend
    from racing while an IRQ handler is reading/writing FIFO registers.
  - Clarified teardown ordering: pxa_ssp_disable() disables hardware interrupt generation
    first, followed by setting drv_data->suspended = true and calling synchronize_irq(),
    ensuring in-flight IRQ handlers drain completely before clock gating.

Changes in v13:
  - Addressed feedback from Sashiko review on the v12 patchset for Patch 2:
  - Removed pm_runtime_get_if_active() check from ssp_int(). During PM state
    transitions (such as RPM_SUSPENDING or RPM_RESUMING), pm_runtime_get_if_active()
    returns 0 because the state is not RPM_ACTIVE. Returning IRQ_NONE during transition
    without clearing a level-triggered interrupt would cause the interrupt controller
    to endlessly re-invoke the handler in a loop.
  - Rely on drv_data->suspended and drv_data->clk_enabled in ssp_int() instead.
    If the clock is enabled (drv_data->clk_enabled == true), MMIO reads are 100% safe
    and will not cause PCIe Completion Timeouts. If the clock is disabled or the device
    is suspended, ssp_int() immediately returns IRQ_NONE to prevent unclocked access.

Changes in v12:
  - Addressed feedback from Sashiko review on the v11 patchset for Patch 2:
  - Preserved the if (!pm_runtime_suspended(dev)) check prior to enabling/disabling
    the clock in pxa2xx_spi_suspend() and pxa2xx_spi_resume(). On non-LPSS platforms,
    if a device was runtime suspended prior to system sleep, unconditionally enabling
    its hardware clock during system resume forced the clock ON while the PM core
    retained RPM_SUSPENDED. Restoring this check prevents PM state desynchronization,
    avoiding power leaks on non-LPSS platforms.

Changes in v11:
  - Addressed feedback from Sashiko review on the v10 patchset for Patch 2:
  - Replaced pm_runtime_put_noidle() with pm_runtime_put_sync() in pxa2xx_spi_remove().
    Using pm_runtime_put_noidle() dropped usage count without executing the runtime_suspend
    callback or updating the device runtime status, leaving it stuck in RPM_ACTIVE. This
    permanently leaked an active child count on the parent LPSS power domain, preventing
    the parent from entering low-power runtime suspend. Switching to pm_runtime_put_sync()
    ensures the runtime PM state machine properly transitions to RPM_SUSPENDED upon driver
    unbind.

Changes in v10:
  - Addressed feedback from Sashiko review on the v9 patchset:
  - Fixed ssp_int() by explicitly returning IRQ_NONE when pm_runtime_get_if_active()
    returns 0 (device inactive or suspending). This prevents reading SSSR and MMIO
    registers when the hardware is powered down or in power transition.
  - Resolved PM usage counter leak and double-increment for PIO mode devices. Removed
    the redundant/unconditional pm_runtime_get_noresume() in pxa2xx_spi_probe() and
    moved the single pm_runtime_get_noresume() call to occur strictly after
    spi_register_controller() succeeds.

Changes in v9:
  - Separated the original "disable DMA and fix runtime PM" patch into two distinct commits:
    1. spi: pxa2xx: disable DMA for Apple MacBook8,1 (PCI glue DMI quirk)
    2. spi: pxa2xx: fix runtime PM and interrupt handling in PIO mode (core driver PM/IRQ fixes)
  - Condensed commit messages for Patches 2 and 3 for clarity and brevity.
  - Fixed checkpatch.pl warning regarding unnecessary braces in pxa2xx_spi_remove().
  - Addressed feedback from Sashiko review on the v8 patchset:
  - Scoped pm_runtime_get_noresume() in pxa2xx_spi_probe() and pm_runtime_put_noidle()
    in remove/error paths using is_lpss_ssp(drv_data). This locks out autosuspend
    for LPSS controllers operating in PIO mode without causing power regressions on
    non-LPSS platforms (e.g. PXA25x, Intel Quark, CE4100) operating in PIO mode.
  - Guarded MMIO accesses in pxa2xx_spi_runtime_suspend() with a drv_data->clk_enabled
    check. If the clock has already been turned off (e.g. in pxa2xx_spi_remove() or
    resume error path), runtime suspend skips hardware writes, avoiding unclocked
    MMIO accesses and PCIe Completion Timeouts if runtime PM triggers after teardown.
  - Cleaned up pxa2xx_spi_pci_can_dma() signature in spi-pxa2xx-pci.c by removing the
    redundant `bool verbose` parameter.

Changes in v8:
  - Addressed feedback from Sashiko review on the v7 patchset:
  - Fixed runtime PM resume interrupt storm in ssp_int() by checking drv_data->clk_enabled
    instead of pm_runtime_get_if_active() == 0.
  - Fixed PM disabled configuration (CONFIG_PM=n) support in ssp_int() by avoiding
    active <= 0 early returns.
  - Reordered suspend and remove sequences to invoke pxa_ssp_disable() before setting
    drv_data->suspended = true and synchronizing the IRQ, closing a race window
    where level-triggered interrupts could cause a storm.
  - Masked hardware interrupt generation in pxa2xx_spi_runtime_suspend() via
    pxa_ssp_disable() to prevent unexpected interrupts during clock enable.
  - Avoided PCIe Completion Timeout system hangs on newer LPSS platforms (SPT, BXT, CNL)
    by introducing pxa2xx_spi_need_lpss_restore() to restrict MMIO save/restore
    loops to LPT, BYT, and BSW platforms (which lack an MFD parent).
  - Fixed compiler error in pxa2xx_spi_probe() due to unused label.

Changes in v7:
  - Addressed feedback from Sashiko review on the v6 patchset:
  - Fixed a race condition during probe by moving the request_irq() call after
    the clock is enabled and the suspended flag is cleared. This prevents an early
    shared interrupt from asserting and triggering an interrupt storm before the clock
    is active to allow clearing it.
  - Rectified the teardown sequence in pxa2xx_spi_remove(): first set drv_data->suspended
    to true and disable SSP hardware-level interrupt generation (pxa_ssp_disable()), then call
    synchronize_irq() to wait for in-flight interrupt handlers to complete, free the
    IRQ, and only then disable the clocks. This eliminates both post-clock-disable MMIO
    accesses and unhandled shared hardware interrupt storms.
  - Clarified that the unconditional MMIO register access in pxa2xx_spi_suspend()
    is safe because pm_runtime_resume_and_get() is invoked at the very beginning of the
    suspend callback, guaranteeing the LPSS device is active and clocked during register
    disabling/saving.
  - Added spi_controller_resume() recovery to the error path of spi_controller_suspend()
    in pxa2xx_spi_suspend() to prevent the controller from remaining permanently disabled
    in the event system suspend is aborted.

Changes in v6:
  - Addressed feedback from Sashiko review on the v5 patchset:
  - Added a synchronize_irq() call to the spi_controller_resume() error path in
    pxa2xx_spi_resume(). This ensures any concurrent shared interrupt handlers
    (which might execute because drv_data->suspended = false was set earlier)
    finish executing before we disable the clock, preventing PCIe timeouts.
  - Checked and confirmed that active == 0 is the correct check in ssp_int(). If
    Runtime PM is disabled, pm_runtime_get_if_active() returns a negative error
    code (like -EINVAL). Changing this check to active <= 0 would cause a
    regression on non-PM configurations because the handler would always return
    IRQ_NONE. Under disabled Runtime PM, the hardware clock is kept constantly
    active, so it is safe to proceed and read registers when active < 0.

Changes in v5:
  - Reverted runtime PM configuration in spi-pxa2xx-pci.c to be unconditional.
    This prevents the usage count from leaking by +1 on unbind for PIO mode,
    while letting pxa2xx_spi_probe()'s pm_runtime_get_noresume() and
    pxa2xx_spi_remove()'s pm_runtime_put_noidle() handle the permanent
    autosuspend lockout for PIO devices symmetrically.
  - Removed the pm_runtime_forbid() call from pxa2xx_spi_remove(). This resolves
    reference leaks for non-PCI platform devices where pm_runtime_allow() was
    never called during probe.
  - Delayed clearing the drv_data->suspended flag on resume until after LPSS reset
    deassertion and private register restoration are complete. This prevents a
    shared interrupt from firing during resume and attempting to read the SSSR
    register while the LPSS block is still held in reset.
  - Set drv_data->suspended = true on spi_controller_resume() failure path in
    pxa2xx_spi_resume(). This ensures that subsequent shared interrupts do not
    attempt register access once the clock is disabled.

Changes in v4:
  - Track clock state using drv_data->clk_enabled via pxa2xx_spi_clk_enable() and
    pxa2xx_spi_clk_disable() helper functions. This guarantees clock enable/disable
    symmetry, preventing clock disable count underflows and framework warnings on S3
    resume or runtime autosuspend error paths.
  - Introduce drv_data->suspended flag to protect MMIO access in ssp_int() during
    system suspend and runtime suspend transition windows.
  - Initialize drv_data->suspended = true early in probe(), clearing it only after
    the clock is successfully enabled. This completely prevents shared interrupt
    handler races during device probe when the clock is still off.
  - Call synchronize_irq() after setting drv_data->suspended = true in suspend and
    runtime_suspend. This ensures any running shared interrupt handlers finish
    executing before the clock is physically turned off.

Changes in v3:
  - Avoid PM reference leaks on probe bind/unbind cycle by keeping probe PM
    configuration symmetric.
  - Prevent userspace (PowerTOP, udev) from overriding runtime PM settings when
    DMA is disabled by holding a PM reference via pm_runtime_get_noresume()
    in pxa2xx_spi_probe() and dropping it in remove/error paths.
  - Check device status in the shared interrupt handler ssp_int() using
    pm_runtime_get_if_active() instead of pm_runtime_suspended(). If the device is
    suspending (RPM_SUSPENDING) or suspended, ssp_int() immediately returns
    IRQ_NONE to avoid reading unclocked MMIO registers during power transition.
  - Adjust the driver teardown order in pxa2xx_spi_remove() and probe error paths:
    always call free_irq() to unregister the handler before calling
    clk_disable_unprepare() to turn off the clock, preventing concurrent
    interrupts from reading registers while the clock is disabled.
  - Avoid duplicate can-DMA pci_info() logging by checking the pre-computed
    enable_dma status in probe and passing a verbose flag to can_dma().

Changes in v2:
  - Addressed feedback from Mark Brown on the original v1 series.
  - Used drv_data->lpss_base together with relative offsets rather than
    hardcoding absolute MMIO offsets that vary between LPSS IP revisions.
  - Moved the register save block in suspend to after the controller is quiesced
    (after spi_controller_suspend() and pxa_ssp_disable()).
  - Store the context array lpss_priv_ctx[6] inside struct driver_data instead of
    struct pxa2xx_spi_controller. This keeps the changes entirely local to the
    core driver, preventing symbol version mismatches (disagrees about version
    of symbol) for other subsystem components (e.g., spi-pxa2xx-platform.ko).
  - Restrict the save/restore loop to the first 6 LPSS private registers
    (offsets 0x00 to 0x14). Offsets beyond 0x14 (except CS control at 0x18, which is
    re-initialised by lpss_ssp_setup()) are reserved/unimplemented on LPT
    platforms (such as MacBook8,1), and writing to them triggers a PCIe
    Completion Timeout causing a system freeze.
  - Added named constants for LPSS_PRIV_RESETS and the de-assert value.
  - Wrapped S3 suspend/resume with pm_runtime_resume_and_get() and
    pm_runtime_put_autosuspend() respectively.

Shih-Yuan Lee (7):
  spi: pxa2xx: introduce clock enable and disable helper functions
  spi: pxa2xx: introduce suspended flag for interrupt synchronization
  spi: pxa2xx: overhaul teardown and suspend sequence using
    pxa2xx_spi_off
  spi: pxa2xx: lock out runtime autosuspend for Intel LPSS SPI in PIO
    mode
  spi: pxa2xx: disable DMA for Apple MacBook8,1
  spi: pxa2xx: restore LPSS private register state on S3 resume
  spi: pxa2xx: rename local status variable to ret

 drivers/spi/spi-pxa2xx-pci.c |  35 ++++-
 drivers/spi/spi-pxa2xx.c     | 256 ++++++++++++++++++++++++++++-------
 drivers/spi/spi-pxa2xx.h     |   4 +
 3 files changed, 246 insertions(+), 49 deletions(-)

-- 
2.39.5

[PATCH v16 1/7] spi: pxa2xx: introduce clock enable and disable helper functions

[Shih-Yuan Lee]

The driver disables the clock during PM runtime suspend, PM system
suspend, and device unbinding (remove). It also disables the clock
on various error unwinding paths in pxa2xx_spi_probe().

However, if the clock is already disabled (for example, if the device is
already runtime-suspended during driver unbinding), calling the common
clock framework's clk_disable_unprepare() again leads to clock prepare/enable
count underflows, generating kernel warnings.

Introduce pxa2xx_spi_clk_enable() and pxa2xx_spi_clk_disable() helper
functions that track the clock enable state using a new 'clk_enabled'
boolean flag in struct driver_data.

This ensures clk_disable_unprepare() is called only when the clock is
active, preventing clock underflows during suspend transitions and unbind.
It also allows the probe function to safely unwind resource allocations
without triggering clock underflows.

Signed-off-by: Shih-Yuan Lee <fourdollars@debian.org>
---
 drivers/spi/spi-pxa2xx.c | 37 +++++++++++++++++++++++++++++--------
 drivers/spi/spi-pxa2xx.h |  2 ++
 2 files changed, 31 insertions(+), 8 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 6291d7c2e06f..d50152aad348 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -713,6 +713,28 @@ static void handle_bad_msg(struct driver_data *drv_data)
 	dev_err(drv_data->ssp->dev, "bad message state in interrupt handler\n");
 }
 
+static int pxa2xx_spi_clk_enable(struct driver_data *drv_data)
+{
+	int ret;
+
+	if (drv_data->clk_enabled)
+		return 0;
+
+	ret = clk_prepare_enable(drv_data->ssp->clk);
+	if (ret == 0)
+		drv_data->clk_enabled = true;
+
+	return ret;
+}
+
+static void pxa2xx_spi_clk_disable(struct driver_data *drv_data)
+{
+	if (drv_data->clk_enabled) {
+		clk_disable_unprepare(drv_data->ssp->clk);
+		drv_data->clk_enabled = false;
+	}
+}
+
 static irqreturn_t ssp_int(int irq, void *dev_id)
 {
 	struct driver_data *drv_data = dev_id;
@@ -1352,7 +1374,7 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 	}
 
 	/* Enable SOC clock */
-	status = clk_prepare_enable(ssp->clk);
+	status = pxa2xx_spi_clk_enable(drv_data);
 	if (status)
 		goto out_error_dma_irq_alloc;
 
@@ -1449,7 +1471,7 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 	return status;
 
 out_error_clock_enabled:
-	clk_disable_unprepare(ssp->clk);
+	pxa2xx_spi_clk_disable(drv_data);
 
 out_error_dma_irq_alloc:
 	pxa2xx_spi_dma_release(drv_data);
@@ -1468,7 +1490,7 @@ void pxa2xx_spi_remove(struct device *dev)
 
 	/* Disable the SSP at the peripheral and SOC level */
 	pxa_ssp_disable(ssp);
-	clk_disable_unprepare(ssp->clk);
+	pxa2xx_spi_clk_disable(drv_data);
 
 	/* Release DMA */
 	if (drv_data->controller_info->enable_dma)
@@ -1492,7 +1514,7 @@ static int pxa2xx_spi_suspend(struct device *dev)
 	pxa_ssp_disable(ssp);
 
 	if (!pm_runtime_suspended(dev))
-		clk_disable_unprepare(ssp->clk);
+		pxa2xx_spi_clk_disable(drv_data);
 
 	return 0;
 }
@@ -1500,12 +1522,11 @@ static int pxa2xx_spi_suspend(struct device *dev)
 static int pxa2xx_spi_resume(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
-	struct ssp_device *ssp = drv_data->ssp;
 	int status;
 
 	/* Enable the SSP clock */
 	if (!pm_runtime_suspended(dev)) {
-		status = clk_prepare_enable(ssp->clk);
+		status = pxa2xx_spi_clk_enable(drv_data);
 		if (status)
 			return status;
 	}
@@ -1518,7 +1539,7 @@ static int pxa2xx_spi_runtime_suspend(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
 
-	clk_disable_unprepare(drv_data->ssp->clk);
+	pxa2xx_spi_clk_disable(drv_data);
 	return 0;
 }
 
@@ -1526,7 +1547,7 @@ static int pxa2xx_spi_runtime_resume(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
 
-	return clk_prepare_enable(drv_data->ssp->clk);
+	return pxa2xx_spi_clk_enable(drv_data);
 }
 
 EXPORT_NS_GPL_DEV_PM_OPS(pxa2xx_spi_pm_ops, SPI_PXA2xx) = {
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 447be0369384..820e573a3c60 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -72,6 +72,8 @@ struct driver_data {
 
 	void __iomem *lpss_base;
 
+	bool clk_enabled;
+
 	/* Optional slave FIFO ready signal */
 	struct gpio_desc *gpiod_ready;
 };
-- 
2.39.5

[PATCH v16 2/7] spi: pxa2xx: introduce suspended flag for interrupt synchronization

[Shih-Yuan Lee]

When a shared interrupt line is used, the interrupt handler ssp_int()
can be triggered by other devices sharing the line. The handler must
ensure it does not access the SSP controller registers via MMIO when
the device is powered down or when its clock is gated; otherwise, it
will cause PCIe Completion Timeouts and system hangs.

Currently, ssp_int() guards MMIO access using:
    if (pm_runtime_suspended(drv_data->ssp->dev)) return IRQ_NONE;

However, during PM transitions (such as system suspend or runtime PM
autosuspend), device callbacks execute to disable the hardware and gate the
clock, but the PM state machine does not mark the device as RPM_SUSPENDED
until after the suspend callback returns. During this transitional state
(RPM_SUSPENDING), pm_runtime_suspended() returns false. If a shared
interrupt fires after the clock has been gated but before the PM state has
transitioned, ssp_int() will execute, attempt MMIO reads on the unclocked
register space, and hang the system.

Formal verification using Spin/PROMELA confirms that a scheduling window
exists where the interrupt thread accesses MMIO when clk_enabled is false,
violating safety properties.

Introduce a custom 'suspended' boolean flag in struct driver_data to
track the device's suspended state across all PM transitions. Check
both 'drv_data->suspended' and '!drv_data->clk_enabled' in ssp_int()
to return IRQ_NONE immediately before any MMIO access is attempted.

This closes the state transition race condition and mathematically guarantees
deadlock-free, safe shared interrupt handling during power transitions.

Signed-off-by: Shih-Yuan Lee <fourdollars@debian.org>
---
 drivers/spi/spi-pxa2xx.c | 51 ++++++++++++++++++++++++++--------------
 drivers/spi/spi-pxa2xx.h |  1 +
 2 files changed, 35 insertions(+), 17 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index d50152aad348..c44349ab2b52 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -730,8 +730,8 @@ static int pxa2xx_spi_clk_enable(struct driver_data *drv_data)
 static void pxa2xx_spi_clk_disable(struct driver_data *drv_data)
 {
 	if (drv_data->clk_enabled) {
-		clk_disable_unprepare(drv_data->ssp->clk);
 		drv_data->clk_enabled = false;
+		clk_disable_unprepare(drv_data->ssp->clk);
 	}
 }
 
@@ -743,12 +743,12 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
 	u32 status;
 
 	/*
-	 * The IRQ might be shared with other peripherals so we must first
-	 * check that are we RPM suspended or not. If we are we assume that
-	 * the IRQ was not for us (we shouldn't be RPM suspended when the
-	 * interrupt is enabled).
+	 * The IRQ might be shared with other peripherals or trigger during
+	 * power state transitions. First check if device is suspended or if
+	 * clock is disabled; if so, return IRQ_NONE immediately to avoid
+	 * unclocked MMIO reads.
 	 */
-	if (pm_runtime_suspended(drv_data->ssp->dev))
+	if (drv_data->suspended || !drv_data->clk_enabled)
 		return IRQ_NONE;
 
 	/*
@@ -1310,6 +1310,7 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 	drv_data->controller = controller;
 	drv_data->controller_info = platform_info;
 	drv_data->ssp = ssp;
+	drv_data->suspended = true;
 
 	/* The spi->mode bits understood by this driver: */
 	controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
@@ -1352,11 +1353,6 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 						| SSSR_ROR | SSSR_TUR;
 	}
 
-	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
-			drv_data);
-	if (status < 0)
-		return dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq);
-
 	/* Setup DMA if requested */
 	if (platform_info->enable_dma) {
 		status = pxa2xx_spi_dma_setup(drv_data);
@@ -1376,7 +1372,16 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 	/* Enable SOC clock */
 	status = pxa2xx_spi_clk_enable(drv_data);
 	if (status)
-		goto out_error_dma_irq_alloc;
+		goto out_error_dma_alloc;
+
+	drv_data->suspended = false;
+
+	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
+			drv_data);
+	if (status < 0) {
+		status = dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq);
+		goto out_error_clock_enabled;
+	}
 
 	controller->max_speed_hz = clk_get_rate(ssp->clk);
 	/*
@@ -1456,7 +1461,7 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 						"ready", GPIOD_OUT_LOW);
 		if (IS_ERR(drv_data->gpiod_ready)) {
 			status = PTR_ERR(drv_data->gpiod_ready);
-			goto out_error_clock_enabled;
+			goto out_error_irq_alloc;
 		}
 	}
 
@@ -1465,17 +1470,19 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 	status = spi_register_controller(controller);
 	if (status) {
 		dev_err_probe(dev, status, "problem registering SPI controller\n");
-		goto out_error_clock_enabled;
+		goto out_error_irq_alloc;
 	}
 
 	return status;
 
+out_error_irq_alloc:
+	free_irq(ssp->irq, drv_data);
+
 out_error_clock_enabled:
 	pxa2xx_spi_clk_disable(drv_data);
 
-out_error_dma_irq_alloc:
+out_error_dma_alloc:
 	pxa2xx_spi_dma_release(drv_data);
-	free_irq(ssp->irq, drv_data);
 
 	return status;
 }
@@ -1511,6 +1518,7 @@ static int pxa2xx_spi_suspend(struct device *dev)
 	if (status)
 		return status;
 
+	drv_data->suspended = true;
 	pxa_ssp_disable(ssp);
 
 	if (!pm_runtime_suspended(dev))
@@ -1531,6 +1539,8 @@ static int pxa2xx_spi_resume(struct device *dev)
 			return status;
 	}
 
+	drv_data->suspended = false;
+
 	/* Start the queue running */
 	return spi_controller_resume(drv_data->controller);
 }
@@ -1539,6 +1549,7 @@ static int pxa2xx_spi_runtime_suspend(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
 
+	drv_data->suspended = true;
 	pxa2xx_spi_clk_disable(drv_data);
 	return 0;
 }
@@ -1546,8 +1557,14 @@ static int pxa2xx_spi_runtime_suspend(struct device *dev)
 static int pxa2xx_spi_runtime_resume(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
+	int ret;
 
-	return pxa2xx_spi_clk_enable(drv_data);
+	ret = pxa2xx_spi_clk_enable(drv_data);
+	if (ret)
+		return ret;
+
+	drv_data->suspended = false;
+	return 0;
 }
 
 EXPORT_NS_GPL_DEV_PM_OPS(pxa2xx_spi_pm_ops, SPI_PXA2xx) = {
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 820e573a3c60..44f37bf9c519 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -72,6 +72,7 @@ struct driver_data {
 
 	void __iomem *lpss_base;
 
+	bool suspended;
 	bool clk_enabled;
 
 	/* Optional slave FIFO ready signal */
-- 
2.39.5

[PATCH v16 3/7] spi: pxa2xx: overhaul teardown and suspend sequence using pxa2xx_spi_off

[Shih-Yuan Lee]

When removing the driver or suspending the device, the clock must not
be disabled while shared interrupts are still active. Gating the clock
before waiting for in-flight interrupt handlers to complete results
in race conditions where the handler performs unclocked MMIO accesses,
causing PCIe Completion Timeouts.

Overhaul the remove, suspend, and runtime_suspend paths to use a strict
synchronized teardown order:
1. Disable hardware interrupt generation at the controller level.
2. Mark the device state as suspended (suspended = true) to prevent
   subsequent interrupt handlers from attempting MMIO reads.
3. Call synchronize_irq() to wait for any active interrupt handlers
   to drain completely.
4. Gate the clock via pxa2xx_spi_clk_disable().

Additionally, commit 29d7e05c5f75 ("spi: pxa2xx: Avoid touching
SSCR0_SSE on MMP2") documented that disabling the hardware block via SSE on
MMP2 SoC platforms corrupts the RX/TX FIFO. Instead of calling
pxa_ssp_disable() directly, use the helper function pxa2xx_spi_off(),
which respects the MMP2 platform quirk by bypassing SSE register writes.

Signed-off-by: Shih-Yuan Lee <fourdollars@debian.org>
---
 drivers/spi/spi-pxa2xx.c | 45 ++++++++++++++++++++++++++++------------
 1 file changed, 32 insertions(+), 13 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index c44349ab2b52..6bfd3382acc3 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1495,16 +1495,24 @@ void pxa2xx_spi_remove(struct device *dev)
 
 	spi_unregister_controller(drv_data->controller);
 
-	/* Disable the SSP at the peripheral and SOC level */
-	pxa_ssp_disable(ssp);
+	/* Disable SSP interrupt generation on hardware level while clock is active */
+	pxa2xx_spi_off(drv_data);
+
+	/* Mark as suspended to prevent further IRQ handling */
+	drv_data->suspended = true;
+
+	/* Wait for any pending interrupt handlers to complete */
+	synchronize_irq(ssp->irq);
+
+	/* Release IRQ */
+	free_irq(ssp->irq, drv_data);
+
+	/* Safe to disable the SSP clock now */
 	pxa2xx_spi_clk_disable(drv_data);
 
 	/* Release DMA */
 	if (drv_data->controller_info->enable_dma)
 		pxa2xx_spi_dma_release(drv_data);
-
-	/* Release IRQ */
-	free_irq(ssp->irq, drv_data);
 }
 EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_remove, "SPI_PXA2xx");
 
@@ -1519,10 +1527,10 @@ static int pxa2xx_spi_suspend(struct device *dev)
 		return status;
 
 	drv_data->suspended = true;
-	pxa_ssp_disable(ssp);
+	pxa2xx_spi_off(drv_data);
+	synchronize_irq(ssp->irq);
 
-	if (!pm_runtime_suspended(dev))
-		pxa2xx_spi_clk_disable(drv_data);
+	pxa2xx_spi_clk_disable(drv_data);
 
 	return 0;
 }
@@ -1530,6 +1538,7 @@ static int pxa2xx_spi_suspend(struct device *dev)
 static int pxa2xx_spi_resume(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
+	struct ssp_device *ssp = drv_data->ssp;
 	int status;
 
 	/* Enable the SSP clock */
@@ -1542,7 +1551,15 @@ static int pxa2xx_spi_resume(struct device *dev)
 	drv_data->suspended = false;
 
 	/* Start the queue running */
-	return spi_controller_resume(drv_data->controller);
+	status = spi_controller_resume(drv_data->controller);
+	if (status) {
+		drv_data->suspended = true;
+		synchronize_irq(ssp->irq);
+		pxa2xx_spi_clk_disable(drv_data);
+		return status;
+	}
+
+	return 0;
 }
 
 static int pxa2xx_spi_runtime_suspend(struct device *dev)
@@ -1550,6 +1567,8 @@ static int pxa2xx_spi_runtime_suspend(struct device *dev)
 	struct driver_data *drv_data = dev_get_drvdata(dev);
 
 	drv_data->suspended = true;
+	pxa2xx_spi_off(drv_data);
+	synchronize_irq(drv_data->ssp->irq);
 	pxa2xx_spi_clk_disable(drv_data);
 	return 0;
 }
@@ -1557,11 +1576,11 @@ static int pxa2xx_spi_runtime_suspend(struct device *dev)
 static int pxa2xx_spi_runtime_resume(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
-	int ret;
+	int status;
 
-	ret = pxa2xx_spi_clk_enable(drv_data);
-	if (ret)
-		return ret;
+	status = pxa2xx_spi_clk_enable(drv_data);
+	if (status)
+		return status;
 
 	drv_data->suspended = false;
 	return 0;
-- 
2.39.5

[PATCH v16 4/7] spi: pxa2xx: lock out runtime autosuspend for Intel LPSS SPI in PIO mode

[Shih-Yuan Lee]

When operating in PIO mode on Intel LPSS SPI controllers, runtime PM
autosuspend clock-gates the hardware block when idle. On subsequent
transfers, MMIO accesses to trigger resume are performed before the runtime
PM state machine can wake the controller, causing PCIe Completion Timeouts.
This issue does not affect DMA mode, where the DMA engine holds the required
resources, nor does it affect non-LPSS controllers.

Lock out runtime PM autosuspend for LPSS SPI controllers specifically
when operating in PIO mode.

Acquire a runtime PM reference via pm_runtime_get_noresume() in
pxa2xx_spi_probe() after registration, and release it via
pm_runtime_put_noidle() in pxa2xx_spi_remove() before hardware teardown to
ensure the runtime PM reference held in probe is released without invoking
runtime_suspend on already-unclocked hardware.

Signed-off-by: Shih-Yuan Lee <fourdollars@debian.org>
---
 drivers/spi/spi-pxa2xx.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 6bfd3382acc3..34241a6742eb 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1473,6 +1473,9 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 		goto out_error_irq_alloc;
 	}
 
+	if (is_lpss_ssp(drv_data) && !platform_info->enable_dma)
+		pm_runtime_get_noresume(dev);
+
 	return status;
 
 out_error_irq_alloc:
@@ -1495,6 +1498,13 @@ void pxa2xx_spi_remove(struct device *dev)
 
 	spi_unregister_controller(drv_data->controller);
 
+	/* Release the PM reference held in probe for LPSS PIO mode before
+	 * hardware teardown so the PM core does not invoke runtime_suspend
+	 * on already-unclocked hardware.
+	 */
+	if (is_lpss_ssp(drv_data) && !drv_data->controller_info->enable_dma)
+		pm_runtime_put_noidle(dev);
+
 	/* Disable SSP interrupt generation on hardware level while clock is active */
 	pxa2xx_spi_off(drv_data);
 
-- 
2.39.5

[PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Shih-Yuan Lee]

On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at
00:15.4 suffers from hardware DMA handshake failures and interrupt
routing bugs, causing keyboard/touchpad transactions to fail when
DMA is enabled.

Move the forced PIO mode DMI quirk to spi-pxa2xx-pci.c (the LPSS host
controller PCI glue driver) to avoid layering violations in client
drivers (such as applespi).

Add an explicit DMI match table for MacBook8,1 and a module parameter
spi_pxa2xx_force_pio to allow forcing PIO mode on demand.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=108331
Signed-off-by: Shih-Yuan Lee <fourdollars@debian.org>
---
 drivers/spi/spi-pxa2xx-pci.c | 35 +++++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index cae77ac18520..31bdaa096d9e 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -18,9 +18,14 @@
 
 #include <linux/dmaengine.h>
 #include <linux/platform_data/dma-dw.h>
+#include <linux/dmi.h>
 
 #include "spi-pxa2xx.h"
 
+static bool spi_pxa2xx_force_pio;
+module_param_named(force_pio, spi_pxa2xx_force_pio, bool, 0444);
+MODULE_PARM_DESC(force_pio, "Force PIO mode (disables DMA) for SPI transfers. ([0] = disabled, 1 = enabled)");
+
 #define PCI_DEVICE_ID_INTEL_QUARK_X1000		0x0935
 #define PCI_DEVICE_ID_INTEL_BYT			0x0f0e
 #define PCI_DEVICE_ID_INTEL_MRFLD		0x1194
@@ -93,6 +98,32 @@ static void lpss_dma_put_device(void *dma_dev)
 	pci_dev_put(dma_dev);
 }
 
+static const struct dmi_system_id pxa2xx_spi_pci_dmi_table[] = {
+	{
+		.ident = "Apple MacBook8,1",
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
+			DMI_MATCH(DMI_PRODUCT_NAME, "MacBook8,1"),
+		},
+	},
+	{ }
+};
+
+static bool pxa2xx_spi_pci_can_dma(struct pci_dev *dev)
+{
+	if (spi_pxa2xx_force_pio) {
+		pci_info(dev, "Forcing PIO mode (disabling DMA)\n");
+		return false;
+	}
+
+	if (dmi_check_system(pxa2xx_spi_pci_dmi_table)) {
+		pci_info(dev, "MacBook8,1 detected: disabling DMA to force PIO mode\n");
+		return false;
+	}
+
+	return true;
+}
+
 static int lpss_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controller *c)
 {
 	struct ssp_device *ssp = &c->ssp;
@@ -166,7 +197,7 @@ static int lpss_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controller *c)
 
 	c->dma_filter = lpss_dma_filter;
 	c->dma_burst_size = 1;
-	c->enable_dma = 1;
+	c->enable_dma = pxa2xx_spi_pci_can_dma(dev);
 	return 0;
 }
 
@@ -238,7 +269,7 @@ static int mrfld_spi_setup(struct pci_dev *dev, struct pxa2xx_spi_controller *c)
 
 	c->dma_filter = lpss_dma_filter;
 	c->dma_burst_size = 8;
-	c->enable_dma = 1;
+	c->enable_dma = pxa2xx_spi_pci_can_dma(dev);
 	return 0;
 }
 
-- 
2.39.5

[PATCH v16 6/7] spi: pxa2xx: restore LPSS private register state on S3 resume

[Shih-Yuan Lee]

Intel LPSS SPI controllers lose all private register state across S3
suspend because the LPSS power domain is fully removed. On resume the
driver only re-enables the SSP clock, leaving the LPSS private registers
in their power-on-reset state, which causes two problems:

1. LPSS_PRIV_RESETS (offset 0x04 within the LPSS private space) stays
   zero, keeping the functional block in reset. Any MMIO access while
   the block is held in reset causes a PCIe Completion Timeout and a
   watchdog-triggered system reset. LPSS_PRIV_RESETS_FUNC and
   LPSS_PRIV_RESETS_IDMA must be de-asserted before any other register
   access on resume.

2. The LPSS software chip-select control register must not be blindly
   restored from its suspend-time snapshot: if CS was asserted at the
   moment of suspend, restoring that state corrupts the first
   post-resume SPI transaction. Instead, call lpss_ssp_setup() which
   unconditionally writes SW_MODE | CS_HIGH (idle/deasserted), matching
   the state established at probe time.

To resolve these issues safely:
- Wrap S3 suspend/resume with pm_runtime_resume_and_get() and
  pm_runtime_put_noidle() to guarantee active clocks during MMIO
  access and preserve PM reference counting.
- Restrict LPSS private register save/restore to LPT, BYT, and BSW
  platforms via pxa2xx_spi_need_lpss_restore() (newer platforms are
  handled by intel-lpss.c).
- Save only the first 6 LPSS private registers (offsets 0x00..0x14) in
  drv_data during suspend, avoiding reserved offsets beyond 0x14.
- On resume, de-assert resets first, restore saved registers, call
  lpss_ssp_setup(), and clear drv_data->suspended to prevent unclocked
  IRQ access.
- Add error recovery paths for spi_controller_suspend/resume failures.
- On the resume error path, call pm_runtime_set_suspended() before
  pm_runtime_put_noidle() to align the PM runtime state with the
  already-disabled hardware clock, preventing pxa2xx_spi_runtime_suspend()
  from attempting unclocked MMIO via pxa2xx_spi_off().

Link: https://bugzilla.kernel.org/show_bug.cgi?id=108331
Signed-off-by: Shih-Yuan Lee <fourdollars@debian.org>
---
 drivers/spi/spi-pxa2xx.c | 105 +++++++++++++++++++++++++++++++++++++--
 drivers/spi/spi-pxa2xx.h |   1 +
 2 files changed, 102 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 34241a6742eb..851626ead25e 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -72,6 +72,11 @@ struct chip_data {
 #define LPSS_CAPS_CS_EN_SHIFT			9
 #define LPSS_CAPS_CS_EN_MASK			(0xf << LPSS_CAPS_CS_EN_SHIFT)
 
+/* Offsets from drv_data->lpss_base */
+#define LPSS_PRIV_RESETS			0x04
+#define LPSS_PRIV_RESETS_IDMA			BIT(2)
+#define LPSS_PRIV_RESETS_FUNC			0x3
+
 #define LPSS_PRIV_CLOCK_GATE 0x38
 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK	0x3
 #define LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON	0x3
@@ -189,6 +194,18 @@ static bool is_lpss_ssp(const struct driver_data *drv_data)
 	}
 }
 
+static bool pxa2xx_spi_need_lpss_restore(const struct driver_data *drv_data)
+{
+	switch (drv_data->ssp_type) {
+	case LPSS_LPT_SSP:
+	case LPSS_BYT_SSP:
+	case LPSS_BSW_SSP:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
 {
 	return drv_data->ssp_type == QUARK_X1000_SSP;
@@ -1532,17 +1549,44 @@ static int pxa2xx_spi_suspend(struct device *dev)
 	struct ssp_device *ssp = drv_data->ssp;
 	int status;
 
+	status = pm_runtime_resume_and_get(dev);
+	if (status < 0)
+		return status;
+
+
 	status = spi_controller_suspend(drv_data->controller);
 	if (status)
-		return status;
+		goto out_put;
 
+	/* Disable SSP interrupt generation on hardware level while clock is active */
 	drv_data->suspended = true;
 	pxa2xx_spi_off(drv_data);
 	synchronize_irq(ssp->irq);
 
+	if (pxa2xx_spi_need_lpss_restore(drv_data)) {
+		unsigned int i;
+
+		/*
+		 * Save the first 6 LPSS private registers (offsets 0x00 to 0x14)
+		 * while the clock is still enabled.  They are lost when the LPSS
+		 * power domain is removed across S3 and must be restored on resume.
+		 * Use drv_data->lpss_base so the correct per-platform offset
+		 * is applied regardless of LPSS IP revision.
+		 * Registers beyond 0x14 (except CS control at 0x18) are reserved
+		 * or unimplemented on LPT, and accessing them triggers a PCIe
+		 * Completion Timeout causing a system halt.
+		 */
+		for (i = 0; i < 6; i++)
+			drv_data->lpss_priv_ctx[i] = readl(drv_data->lpss_base + i * 4);
+	}
+
 	pxa2xx_spi_clk_disable(drv_data);
 
 	return 0;
+
+out_put:
+	pm_runtime_put_noidle(dev);
+	return status;
 }
 
 static int pxa2xx_spi_resume(struct device *dev)
@@ -1555,9 +1599,47 @@ static int pxa2xx_spi_resume(struct device *dev)
 	if (!pm_runtime_suspended(dev)) {
 		status = pxa2xx_spi_clk_enable(drv_data);
 		if (status)
-			return status;
+			goto out_put;
 	}
 
+	if (pxa2xx_spi_need_lpss_restore(drv_data)) {
+		unsigned int i;
+
+		/*
+		 * The LPSS power domain is removed across S3, taking
+		 * all private registers with it.  De-assert the
+		 * functional block and IDMA resets first; any MMIO
+		 * access while the block is held in reset causes a
+		 * PCIe Completion Timeout and a watchdog-triggered
+		 * system reset.
+		 */
+		writel(LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA,
+		       drv_data->lpss_base + LPSS_PRIV_RESETS);
+
+		/* Restore the other 5 saved private registers */
+		for (i = 0; i < 6; i++) {
+			if (i == LPSS_PRIV_RESETS / 4)
+				continue;
+			writel(drv_data->lpss_priv_ctx[i],
+			       drv_data->lpss_base + i * 4);
+		}
+	}
+
+	if (is_lpss_ssp(drv_data)) {
+		/*
+		 * Re-initialise the SW chip-select control register so
+		 * CS starts deasserted (SW_MODE | CS_HIGH), regardless
+		 * of the state it was in at suspend time.  A stale
+		 * asserted CS on the first post-resume transaction
+		 * corrupts the write-status response from the device.
+		 */
+		lpss_ssp_setup(drv_data);
+	}
+
+	/*
+	 * Now that resets are de-asserted and registers are restored,
+	 * it is safe to handle interrupts.
+	 */
 	drv_data->suspended = false;
 
 	/* Start the queue running */
@@ -1566,10 +1648,25 @@ static int pxa2xx_spi_resume(struct device *dev)
 		drv_data->suspended = true;
 		synchronize_irq(ssp->irq);
 		pxa2xx_spi_clk_disable(drv_data);
-		return status;
+		goto out_put;
 	}
 
-	return 0;
+out_put:
+	if (!pm_runtime_suspended(dev)) {
+		if (status)
+			/*
+			 * Clock is already disabled on the error path; align
+			 * the PM runtime state with hardware reality before
+			 * releasing the reference so the PM core does not
+			 * later invoke pxa2xx_spi_runtime_suspend() and attempt
+			 * unclocked MMIO via pxa2xx_spi_off().
+			 */
+			pm_runtime_set_suspended(dev);
+		pm_runtime_put_noidle(dev);
+	}
+
+	return status;
+
 }
 
 static int pxa2xx_spi_runtime_suspend(struct device *dev)
diff --git a/drivers/spi/spi-pxa2xx.h b/drivers/spi/spi-pxa2xx.h
index 44f37bf9c519..48169494f74e 100644
--- a/drivers/spi/spi-pxa2xx.h
+++ b/drivers/spi/spi-pxa2xx.h
@@ -71,6 +71,7 @@ struct driver_data {
 	irqreturn_t (*transfer_handler)(struct driver_data *drv_data);
 
 	void __iomem *lpss_base;
+	u32 lpss_priv_ctx[6];
 
 	bool suspended;
 	bool clk_enabled;
-- 
2.39.5

[PATCH v16 7/7] spi: pxa2xx: rename local status variable to ret

[Shih-Yuan Lee]

Rename the return value variable name from 'status' to 'ret' in the
pxa2xx_spi_probe(), pxa2xx_spi_suspend(), pxa2xx_spi_resume(), and
pxa2xx_spi_runtime_resume() functions to conform to standard Linux kernel
coding conventions.

Signed-off-by: Shih-Yuan Lee <fourdollars@debian.org>
---
 drivers/spi/spi-pxa2xx.c | 66 +++++++++++++++++++---------------------
 1 file changed, 32 insertions(+), 34 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 851626ead25e..9379aac82c7a 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -1313,7 +1313,7 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 	struct spi_controller *controller;
 	struct driver_data *drv_data;
 	const struct lpss_config *config;
-	int status;
+	int ret;
 	u32 tmp;
 
 	if (platform_info->is_target)
@@ -1372,8 +1372,8 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 
 	/* Setup DMA if requested */
 	if (platform_info->enable_dma) {
-		status = pxa2xx_spi_dma_setup(drv_data);
-		if (status) {
+		ret = pxa2xx_spi_dma_setup(drv_data);
+		if (ret) {
 			dev_warn(dev, "no DMA channels available, using PIO\n");
 			platform_info->enable_dma = false;
 		} else {
@@ -1387,16 +1387,16 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 	}
 
 	/* Enable SOC clock */
-	status = pxa2xx_spi_clk_enable(drv_data);
-	if (status)
+	ret = pxa2xx_spi_clk_enable(drv_data);
+	if (ret)
 		goto out_error_dma_alloc;
 
 	drv_data->suspended = false;
 
-	status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
+	ret = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
 			drv_data);
-	if (status < 0) {
-		status = dev_err_probe(dev, status, "cannot get IRQ %d\n", ssp->irq);
+	if (ret < 0) {
+		ret = dev_err_probe(dev, ret, "cannot get IRQ %d\n", ssp->irq);
 		goto out_error_clock_enabled;
 	}
 
@@ -1477,23 +1477,23 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 		drv_data->gpiod_ready = devm_gpiod_get_optional(dev,
 						"ready", GPIOD_OUT_LOW);
 		if (IS_ERR(drv_data->gpiod_ready)) {
-			status = PTR_ERR(drv_data->gpiod_ready);
+			ret = PTR_ERR(drv_data->gpiod_ready);
 			goto out_error_irq_alloc;
 		}
 	}
 
 	/* Register with the SPI framework */
 	dev_set_drvdata(dev, drv_data);
-	status = spi_register_controller(controller);
-	if (status) {
-		dev_err_probe(dev, status, "problem registering SPI controller\n");
+	ret = spi_register_controller(controller);
+	if (ret) {
+		dev_err_probe(dev, ret, "problem registering SPI controller\n");
 		goto out_error_irq_alloc;
 	}
 
 	if (is_lpss_ssp(drv_data) && !platform_info->enable_dma)
 		pm_runtime_get_noresume(dev);
 
-	return status;
+	return ret;
 
 out_error_irq_alloc:
 	free_irq(ssp->irq, drv_data);
@@ -1504,7 +1504,7 @@ int pxa2xx_spi_probe(struct device *dev, struct ssp_device *ssp,
 out_error_dma_alloc:
 	pxa2xx_spi_dma_release(drv_data);
 
-	return status;
+	return ret;
 }
 EXPORT_SYMBOL_NS_GPL(pxa2xx_spi_probe, "SPI_PXA2xx");
 
@@ -1547,15 +1547,14 @@ static int pxa2xx_spi_suspend(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
 	struct ssp_device *ssp = drv_data->ssp;
-	int status;
-
-	status = pm_runtime_resume_and_get(dev);
-	if (status < 0)
-		return status;
+	int ret;
 
+	ret = pm_runtime_resume_and_get(dev);
+	if (ret < 0)
+		return ret;
 
-	status = spi_controller_suspend(drv_data->controller);
-	if (status)
+	ret = spi_controller_suspend(drv_data->controller);
+	if (ret)
 		goto out_put;
 
 	/* Disable SSP interrupt generation on hardware level while clock is active */
@@ -1586,19 +1585,19 @@ static int pxa2xx_spi_suspend(struct device *dev)
 
 out_put:
 	pm_runtime_put_noidle(dev);
-	return status;
+	return ret;
 }
 
 static int pxa2xx_spi_resume(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
 	struct ssp_device *ssp = drv_data->ssp;
-	int status;
+	int ret;
 
 	/* Enable the SSP clock */
 	if (!pm_runtime_suspended(dev)) {
-		status = pxa2xx_spi_clk_enable(drv_data);
-		if (status)
+		ret = pxa2xx_spi_clk_enable(drv_data);
+		if (ret)
 			goto out_put;
 	}
 
@@ -1643,8 +1642,8 @@ static int pxa2xx_spi_resume(struct device *dev)
 	drv_data->suspended = false;
 
 	/* Start the queue running */
-	status = spi_controller_resume(drv_data->controller);
-	if (status) {
+	ret = spi_controller_resume(drv_data->controller);
+	if (ret) {
 		drv_data->suspended = true;
 		synchronize_irq(ssp->irq);
 		pxa2xx_spi_clk_disable(drv_data);
@@ -1653,7 +1652,7 @@ static int pxa2xx_spi_resume(struct device *dev)
 
 out_put:
 	if (!pm_runtime_suspended(dev)) {
-		if (status)
+		if (ret)
 			/*
 			 * Clock is already disabled on the error path; align
 			 * the PM runtime state with hardware reality before
@@ -1665,8 +1664,7 @@ static int pxa2xx_spi_resume(struct device *dev)
 		pm_runtime_put_noidle(dev);
 	}
 
-	return status;
-
+	return ret;
 }
 
 static int pxa2xx_spi_runtime_suspend(struct device *dev)
@@ -1683,11 +1681,11 @@ static int pxa2xx_spi_runtime_suspend(struct device *dev)
 static int pxa2xx_spi_runtime_resume(struct device *dev)
 {
 	struct driver_data *drv_data = dev_get_drvdata(dev);
-	int status;
+	int ret;
 
-	status = pxa2xx_spi_clk_enable(drv_data);
-	if (status)
-		return status;
+	ret = pxa2xx_spi_clk_enable(drv_data);
+	if (ret)
+		return ret;
 
 	drv_data->suspended = false;
 	return 0;
-- 
2.39.5

Re: [PATCH v16 2/7] spi: pxa2xx: introduce suspended flag for interrupt synchronization

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 2423 bytes --]

On Tue, Jul 21, 2026 at 12:21:11AM +0800, Shih-Yuan Lee wrote:
> When a shared interrupt line is used, the interrupt handler ssp_int()
> can be triggered by other devices sharing the line. The handler must
> ensure it does not access the SSP controller registers via MMIO when
> the device is powered down or when its clock is gated; otherwise, it
> will cause PCIe Completion Timeouts and system hangs.

> Currently, ssp_int() guards MMIO access using:
>     if (pm_runtime_suspended(drv_data->ssp->dev)) return IRQ_NONE;

...

> Introduce a custom 'suspended' boolean flag in struct driver_data to
> track the device's suspended state across all PM transitions. Check
> both 'drv_data->suspended' and '!drv_data->clk_enabled' in ssp_int()
> to return IRQ_NONE immediately before any MMIO access is attempted.

>  static void pxa2xx_spi_clk_disable(struct driver_data *drv_data)
>  {
>  	if (drv_data->clk_enabled) {
> -		clk_disable_unprepare(drv_data->ssp->clk);
>  		drv_data->clk_enabled = false;
> +		clk_disable_unprepare(drv_data->ssp->clk);
>  	}
>  }

It's probably better to avoid extra changes like this, it makes the
patch bigger and a bit harder to review.

> @@ -743,12 +743,12 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
>  	u32 status;
>  
>  	/*
> -	 * The IRQ might be shared with other peripherals so we must first
> -	 * check that are we RPM suspended or not. If we are we assume that
> -	 * the IRQ was not for us (we shouldn't be RPM suspended when the
> -	 * interrupt is enabled).
> +	 * The IRQ might be shared with other peripherals or trigger during
> +	 * power state transitions. First check if device is suspended or if
> +	 * clock is disabled; if so, return IRQ_NONE immediately to avoid
> +	 * unclocked MMIO reads.
>  	 */
> -	if (pm_runtime_suspended(drv_data->ssp->dev))
> +	if (drv_data->suspended || !drv_data->clk_enabled)
>  		return IRQ_NONE;
>  
>  	/*

The local flags *must* be racy - I'm not seeing any locking which
protects them, nor anything that stops something else dropping a runtime
PM reference and powering things down after we checked here.  There's a
helper in the power management code pm_runtime_get_if_active() which I
think is what you want here, it'll tell you if the device is runtime
suspended and if the device is active it'll ensure nothing else drops
the last reference while we're running.

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH v16 1/7] spi: pxa2xx: introduce clock enable and disable helper functions

[Andy Shevchenko]

On Tue, Jul 21, 2026 at 12:21:10AM +0800, Shih-Yuan Lee wrote:
> The driver disables the clock during PM runtime suspend, PM system
> suspend, and device unbinding (remove). It also disables the clock
> on various error unwinding paths in pxa2xx_spi_probe().
> 
> However, if the clock is already disabled (for example, if the device is
> already runtime-suspended during driver unbinding), calling the common
> clock framework's clk_disable_unprepare() again leads to clock prepare/enable
> count underflows, generating kernel warnings.

Any real life example here?

> Introduce pxa2xx_spi_clk_enable() and pxa2xx_spi_clk_disable() helper
> functions that track the clock enable state using a new 'clk_enabled'
> boolean flag in struct driver_data.
> 
> This ensures clk_disable_unprepare() is called only when the clock is
> active, preventing clock underflows during suspend transitions and unbind.
> It also allows the probe function to safely unwind resource allocations
> without triggering clock underflows.

...

Same issue, I have no cover letter in my mailbox. Please, slow down and check
your email setup. Something is wrong.

...

> +static int pxa2xx_spi_clk_enable(struct driver_data *drv_data)
> +{
> +	int ret;
> +
> +	if (drv_data->clk_enabled)
> +		return 0;
> +
> +	ret = clk_prepare_enable(drv_data->ssp->clk);

> +	if (ret == 0)
> +		drv_data->clk_enabled = true;
> +
> +	return ret;

Use usual pattern

	if (ret)
		return ret;

	...
	return 0;

> +}

> +static void pxa2xx_spi_clk_disable(struct driver_data *drv_data)
> +{
> +	if (drv_data->clk_enabled) {

	if (!drv_data->clk_enabled)
		return;

> +		clk_disable_unprepare(drv_data->ssp->clk);
> +		drv_data->clk_enabled = false;
> +	}
> +}

...

> struct driver_data {

>  	void __iomem *lpss_base;
>  
> +	bool clk_enabled;

How is this protected against simultaneously called enable/disable on different
CPUs?

>  	/* Optional slave FIFO ready signal */
>  	struct gpio_desc *gpiod_ready;
>  };

Whenever you add the field, check with `pahole` that the layout is optimal.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Andy Shevchenko]

On Tue, Jul 21, 2026 at 12:21:14AM +0800, Shih-Yuan Lee wrote:
> On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at
> 00:15.4 suffers from hardware DMA handshake failures and interrupt
> routing bugs, causing keyboard/touchpad transactions to fail when
> DMA is enabled.

Why? The thing like this I noticed on some other HW which required different
DMA settings. Have you tried to investigate the issue more?

> Move the forced PIO mode DMI quirk to spi-pxa2xx-pci.c (the LPSS host
> controller PCI glue driver) to avoid layering violations in client
> drivers (such as applespi).
> 
> Add an explicit DMI match table for MacBook8,1 and a module parameter
> spi_pxa2xx_force_pio to allow forcing PIO mode on demand.

This looks like a hack. Please, if you have a hardware, try to dump the errors,
collect the data corruption or timeouts and provide more information. DMA for
SPI on LPSS hardware never was a problem (unlike UART in some cases). I'm almost
100% sure the problem is in DMA configuration / setting bits.

...

>  #include <linux/dmaengine.h>
>  #include <linux/platform_data/dma-dw.h>
>   +#include <linux/dmi.h>

Keep list ordered.

>  #include "spi-pxa2xx.h"

...

> +static bool spi_pxa2xx_force_pio;
> +module_param_named(force_pio, spi_pxa2xx_force_pio, bool, 0444);
> +MODULE_PARM_DESC(force_pio, "Force PIO mode (disables DMA) for SPI transfers. ([0] = disabled, 1 = enabled)");

No. There is no room for module parameters like this.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v16 3/7] spi: pxa2xx: overhaul teardown and suspend sequence using pxa2xx_spi_off

[Andy Shevchenko]

On Tue, Jul 21, 2026 at 12:21:12AM +0800, Shih-Yuan Lee wrote:
> When removing the driver or suspending the device, the clock must not
> be disabled while shared interrupts are still active. Gating the clock
> before waiting for in-flight interrupt handlers to complete results
> in race conditions where the handler performs unclocked MMIO accesses,
> causing PCIe Completion Timeouts.
> 
> Overhaul the remove, suspend, and runtime_suspend paths to use a strict
> synchronized teardown order:
> 1. Disable hardware interrupt generation at the controller level.
> 2. Mark the device state as suspended (suspended = true) to prevent
>    subsequent interrupt handlers from attempting MMIO reads.
> 3. Call synchronize_irq() to wait for any active interrupt handlers
>    to drain completely.
> 4. Gate the clock via pxa2xx_spi_clk_disable().
> 
> Additionally, commit 29d7e05c5f75 ("spi: pxa2xx: Avoid touching
> SSCR0_SSE on MMP2") documented that disabling the hardware block via SSE on
> MMP2 SoC platforms corrupts the RX/TX FIFO. Instead of calling
> pxa_ssp_disable() directly, use the helper function pxa2xx_spi_off(),
> which respects the MMP2 platform quirk by bypassing SSE register writes.

...

> +	/* Wait for any pending interrupt handlers to complete */
> +	synchronize_irq(ssp->irq);

Unneeded. free_irq() implies that.

> +	/* Release IRQ */
> +	free_irq(ssp->irq, drv_data);

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v16 4/7] spi: pxa2xx: lock out runtime autosuspend for Intel LPSS SPI in PIO mode

[Andy Shevchenko]

On Tue, Jul 21, 2026 at 12:21:13AM +0800, Shih-Yuan Lee wrote:
> When operating in PIO mode on Intel LPSS SPI controllers, runtime PM
> autosuspend clock-gates the hardware block when idle. On subsequent
> transfers, MMIO accesses to trigger resume are performed before the runtime
> PM state machine can wake the controller, causing PCIe Completion Timeouts.
> This issue does not affect DMA mode, where the DMA engine holds the required
> resources, nor does it affect non-LPSS controllers.
> 
> Lock out runtime PM autosuspend for LPSS SPI controllers specifically
> when operating in PIO mode.
> 
> Acquire a runtime PM reference via pm_runtime_get_noresume() in
> pxa2xx_spi_probe() after registration, and release it via
> pm_runtime_put_noidle() in pxa2xx_spi_remove() before hardware teardown to
> ensure the runtime PM reference held in probe is released without invoking
> runtime_suspend on already-unclocked hardware.

.runtime_suspend()

// this is how we refer to the callbacks.


...

> +	/* Release the PM reference held in probe for LPSS PIO mode before
> +	 * hardware teardown so the PM core does not invoke runtime_suspend
> +	 * on already-unclocked hardware.
> +	 */

/*
 * Keep the comment style as per SPI and many other subsystems
 * and as in this example.
 */

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v16 7/7] spi: pxa2xx: rename local status variable to ret

[Andy Shevchenko]

On Tue, Jul 21, 2026 at 12:21:16AM +0800, Shih-Yuan Lee wrote:
> Rename the return value variable name from 'status' to 'ret' in the
> pxa2xx_spi_probe(), pxa2xx_spi_suspend(), pxa2xx_spi_resume(), and
> pxa2xx_spi_runtime_resume() functions to conform to standard Linux kernel
> coding conventions.

It makes a ping-pong style of changes: Previous patches add more status uses
and moves, and so on. Instead, this patch should go before all that.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v16 6/7] spi: pxa2xx: restore LPSS private register state on S3 resume

[Andy Shevchenko]

On Tue, Jul 21, 2026 at 12:21:15AM +0800, Shih-Yuan Lee wrote:

Is this series AI-assisted?

> Intel LPSS SPI controllers lose all private register state across S3
> suspend because the LPSS power domain is fully removed. On resume the
> driver only re-enables the SSP clock, leaving the LPSS private registers
> in their power-on-reset state, which causes two problems:
> 
> 1. LPSS_PRIV_RESETS (offset 0x04 within the LPSS private space) stays
>    zero, keeping the functional block in reset. Any MMIO access while
>    the block is held in reset causes a PCIe Completion Timeout and a
>    watchdog-triggered system reset. LPSS_PRIV_RESETS_FUNC and
>    LPSS_PRIV_RESETS_IDMA must be de-asserted before any other register
>    access on resume.
> 
> 2. The LPSS software chip-select control register must not be blindly
>    restored from its suspend-time snapshot: if CS was asserted at the
>    moment of suspend, restoring that state corrupts the first
>    post-resume SPI transaction. Instead, call lpss_ssp_setup() which
>    unconditionally writes SW_MODE | CS_HIGH (idle/deasserted), matching
>    the state established at probe time.
> 
> To resolve these issues safely:
> - Wrap S3 suspend/resume with pm_runtime_resume_and_get() and
>   pm_runtime_put_noidle() to guarantee active clocks during MMIO
>   access and preserve PM reference counting.
> - Restrict LPSS private register save/restore to LPT, BYT, and BSW

^^^^ (1)

>   platforms via pxa2xx_spi_need_lpss_restore() (newer platforms are
>   handled by intel-lpss.c).
> - Save only the first 6 LPSS private registers (offsets 0x00..0x14) in
>   drv_data during suspend, avoiding reserved offsets beyond 0x14.
> - On resume, de-assert resets first, restore saved registers, call
>   lpss_ssp_setup(), and clear drv_data->suspended to prevent unclocked
>   IRQ access.
> - Add error recovery paths for spi_controller_suspend/resume failures.
> - On the resume error path, call pm_runtime_set_suspended() before
>   pm_runtime_put_noidle() to align the PM runtime state with the
>   already-disabled hardware clock, preventing pxa2xx_spi_runtime_suspend()
>   from attempting unclocked MMIO via pxa2xx_spi_off().

This is an ugly hack.

Saving context is done in drivers/acpi/x86/lpss.c (see #1 why this file).
If something wrong in the flow it has to be fixed there, not here.

-- 
With Best Regards,
Andy Shevchenko

Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Lukas Wunner]

On Tue, Jul 21, 2026 at 12:21:14AM +0800, Shih-Yuan Lee wrote:
> On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at
> 00:15.4 suffers from hardware DMA handshake failures and interrupt
> routing bugs, causing keyboard/touchpad transactions to fail when
> DMA is enabled.
[...]
> Link: https://bugzilla.kernel.org/show_bug.cgi?id=108331

In the bugzilla comments, Leif Liddy writes:

   "I needed to modify drivers/dma/dw/pci.c to assign the DMA controller
    irq value to 21 (which is what is listed in the ACPI table) for it
    to work. The DMA controller was being assigned an irq value of 20
    for some reason."

It would seem better to fix up the incorrect interrupt number in a quirk,
rather than disabling DMA wholesale.

Thanks,

Lukas

Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Shih-Yuan Lee (FourDollars)]

On Tue, Jul 21, 2026 at 5:18 PM Lukas Wunner <lukas@wunner.de> wrote:
>
> On Tue, Jul 21, 2026 at 12:21:14AM +0800, Shih-Yuan Lee wrote:
> > On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at
> > 00:15.4 suffers from hardware DMA handshake failures and interrupt
> > routing bugs, causing keyboard/touchpad transactions to fail when
> > DMA is enabled.
> [...]
> > Link: https://bugzilla.kernel.org/show_bug.cgi?id=108331
>
> In the bugzilla comments, Leif Liddy writes:
>
>    "I needed to modify drivers/dma/dw/pci.c to assign the DMA controller
>     irq value to 21 (which is what is listed in the ACPI table) for it
>     to work. The DMA controller was being assigned an irq value of 20
>     for some reason."
>
> It would seem better to fix up the incorrect interrupt number in a quirk,
> rather than disabling DMA wholesale.

This is a very good catch!

I appreciate the comment. Based on the Bugzilla feedback regarding the
incorrect interrupt assignment, it seems fixing the IRQ value via a
quirk is indeed a better approach than disabling DMA wholesale. While
I am not certain this will resolve the issue entirely, it looks very
promising. I will investigate the IRQ mis-assignment problem further.

Shih-Yuan

Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Shih-Yuan Lee (FourDollars)]

On Tue, Jul 21, 2026 at 5:26 PM Shih-Yuan Lee (FourDollars)
<fourdollars@debian.org> wrote:
>
> On Tue, Jul 21, 2026 at 5:18 PM Lukas Wunner <lukas@wunner.de> wrote:
> >
> > On Tue, Jul 21, 2026 at 12:21:14AM +0800, Shih-Yuan Lee wrote:
> > > On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at
> > > 00:15.4 suffers from hardware DMA handshake failures and interrupt
> > > routing bugs, causing keyboard/touchpad transactions to fail when
> > > DMA is enabled.
> > [...]
> > > Link: https://bugzilla.kernel.org/show_bug.cgi?id=108331
> >
> > In the bugzilla comments, Leif Liddy writes:
> >
> >    "I needed to modify drivers/dma/dw/pci.c to assign the DMA controller
> >     irq value to 21 (which is what is listed in the ACPI table) for it
> >     to work. The DMA controller was being assigned an irq value of 20
> >     for some reason."
> >
> > It would seem better to fix up the incorrect interrupt number in a quirk,
> > rather than disabling DMA wholesale.
>
> This is a very good catch!
>
> I appreciate the comment. Based on the Bugzilla feedback regarding the
> incorrect interrupt assignment, it seems fixing the IRQ value via a
> quirk is indeed a better approach than disabling DMA wholesale. While
> I am not certain this will resolve the issue entirely, it looks very
> promising. I will investigate the IRQ mis-assignment problem further.

Hi Lukas,

Thank you for the suggestion. I have investigated this direction
thoroughly by implementing the DMI-based IRQ override quirk in
drivers/dma/dw/pci.c to assign both pdev->irq and chip->irq to 21 on
the physical MacBook8,1.

However, I found that fixing up the IRQ to 21 in software is not a
viable solution due to the following findings:

1. DMAR/IOMMU Validation Failure (Error -22)
On modern kernels with Interrupt Remapping (DMAR) enabled, overriding
pdev->irq to 21 causes the dw_dmac_pci driver probe to fail with
-EINVAL (-22) during request_irq(). This is because the
DMAR/IOMMU strictly validates the PCI Requester ID (source ID) against
the GSI mapping defined in the ACPI _PRT table. Forcing a device
mapped to GSI 20 (00:15.0) to register on GSI 21 triggers a
source ID mismatch check, which the kernel rejects.

2. The Mechanism Behind the Historical irqpoll Workaround
In Bugzilla ticket 108331, the reason Leif Liddy's workaround
functioned might be that they booted the system with irqpoll or
irqfixup. Under irqpoll, the kernel polls the DMA status register on
every clock tick/timer interrupt, which completely bypasses the broken
physical interrupt line at the cost of high CPU overhead and power
consumption. Without irqpoll, even if we register the handler
on IRQ 21, the driver never receives physical interrupts because the
hardware line on the motherboard is physically disconnected or masked.

3. Cross-OS Evidence (macOS and Windows 10)
  • macOS: Apple's native driver runs the SPI controller in pure PIO mode.
  • Windows 10 (Boot Camp): Interestingly, the Intel LPSS DMA
Controller (8086:9ce0) is left completely driverless (no driver
installed) by the official Boot Camp package, and does not register or
    use IRQ 20 at all. This forces the Windows SPI driver
(iaLPSS_SPI.sys) to fall back to pure PIO mode as well.

Since both macOS and Windows officially disable DMA to work around
this hardware routing defect, forcing PIO mode in spi-pxa2xx is the
most native, clean, and power-efficient way to support the
MacBook8,1 without introducing probe errors or relying on
high-overhead irqpoll workarounds.

Therefore, disabling DMA wholesale for this platform seems to be the
only correct solution. I will update the commit message of the next
revision to document these physical verification findings.

Thanks,

Shih-Yuan

Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Shih-Yuan Lee (FourDollars)]

On Tue, Jul 21, 2026 at 3:27 AM Andy Shevchenko
<andriy.shevchenko@intel.com> wrote:
>
> On Tue, Jul 21, 2026 at 12:21:14AM +0800, Shih-Yuan Lee wrote:
> > On MacBook8,1 (early 2015 12" MacBook), the LPSS SPI controller at
> > 00:15.4 suffers from hardware DMA handshake failures and interrupt
> > routing bugs, causing keyboard/touchpad transactions to fail when
> > DMA is enabled.
>
> Why? The thing like this I noticed on some other HW which required different
> DMA settings. Have you tried to investigate the issue more?
>
> > Move the forced PIO mode DMI quirk to spi-pxa2xx-pci.c (the LPSS host
> > controller PCI glue driver) to avoid layering violations in client
> > drivers (such as applespi).
> >
> > Add an explicit DMI match table for MacBook8,1 and a module parameter
> > spi_pxa2xx_force_pio to allow forcing PIO mode on demand.
>
> This looks like a hack. Please, if you have a hardware, try to dump the errors,
> collect the data corruption or timeouts and provide more information. DMA for
> SPI on LPSS hardware never was a problem (unlike UART in some cases). I'm almost
> 100% sure the problem is in DMA configuration / setting bits.
>
> ...
>
> >  #include <linux/dmaengine.h>
> >  #include <linux/platform_data/dma-dw.h>
> >   +#include <linux/dmi.h>
>
> Keep list ordered.
>
> >  #include "spi-pxa2xx.h"
>
> ...
>
> > +static bool spi_pxa2xx_force_pio;
> > +module_param_named(force_pio, spi_pxa2xx_force_pio, bool, 0444);
> > +MODULE_PARM_DESC(force_pio, "Force PIO mode (disables DMA) for SPI transfers. ([0] = disabled, 1 = enabled)");
>
> No. There is no room for module parameters like this.
Hi Andy,

Thank you for the review and feedback.

Regarding your question about why DMA fails on this hardware, I have
just sent a detailed reply to Lukas in this thread outlining our
physical verification findings. In short, I confirmed that the
DMA controller's physical interrupt line is not functioning on this
motherboard, and macOS and Windows 10 also completely bypass the DMA
controller. Please refer to that email for the DMAR/IOMMU and
cross-OS analysis details.

Regarding your other comments:

1. Header Sorting:
I will fix the alphabetical ordering of the include headers in the
next revision.

2. The force_pio Module Parameter:
The original spi-pxa2xx driver is designed to hardcode DMA usage if
DMA channels are available. I introduced the force_pio module
parameter for two reasons:
  • It serves as a diagnostic tool for users on similar hardware to
easily test and verify if their issues are related to DMA.
  • It allows developers to easily test and debug the PIO code path on
DMA-capable LPSS hardware to prevent regressions.

That being said, if module parameters of this type are strictly not
preferred, I am completely fine with removing force_pio and keeping
only the DMI-based quirk for the MacBook8,1. Please let me know your
preference.

Thanks,

Shih-Yuan

Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Mark Brown]

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On Tue, Jul 21, 2026 at 10:34:20PM +0800, Shih-Yuan Lee (FourDollars) wrote:
> On Tue, Jul 21, 2026 at 5:26 PM Shih-Yuan Lee (FourDollars)
> > On Tue, Jul 21, 2026 at 5:18 PM Lukas Wunner <lukas@wunner.de> wrote:

> > > It would seem better to fix up the incorrect interrupt number in a quirk,
> > > rather than disabling DMA wholesale.

> > I appreciate the comment. Based on the Bugzilla feedback regarding the
> > incorrect interrupt assignment, it seems fixing the IRQ value via a
> > quirk is indeed a better approach than disabling DMA wholesale. While
> > I am not certain this will resolve the issue entirely, it looks very
> > promising. I will investigate the IRQ mis-assignment problem further.

> 1. DMAR/IOMMU Validation Failure (Error -22)
> On modern kernels with Interrupt Remapping (DMAR) enabled, overriding
> pdev->irq to 21 causes the dw_dmac_pci driver probe to fail with
> -EINVAL (-22) during request_irq(). This is because the
> DMAR/IOMMU strictly validates the PCI Requester ID (source ID) against
> the GSI mapping defined in the ACPI _PRT table. Forcing a device
> mapped to GSI 20 (00:15.0) to register on GSI 21 triggers a
> source ID mismatch check, which the kernel rejects.

That really seems like something we ought to be able to do, though I
think the idiom here is to patch the ACPI tables so they are correct
rather than quirk things in C code.  ICBW about the preferred approach
there.

BTW, if you're using a LLM to assist with analysis please don't just
paste the output into mail.  Instead make sure you understand what the
LLM is saying and write up the salient bits.

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Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Shih-Yuan Lee (FourDollars)]

On Tue, Jul 21, 2026 at 11:05 PM Mark Brown <broonie@debian.org> wrote:
>
> On Tue, Jul 21, 2026 at 10:34:20PM +0800, Shih-Yuan Lee (FourDollars) wrote:
> > On Tue, Jul 21, 2026 at 5:26 PM Shih-Yuan Lee (FourDollars)
> > > On Tue, Jul 21, 2026 at 5:18 PM Lukas Wunner <lukas@wunner.de> wrote:
>
> > > > It would seem better to fix up the incorrect interrupt number in a quirk,
> > > > rather than disabling DMA wholesale.
>
> > > I appreciate the comment. Based on the Bugzilla feedback regarding the
> > > incorrect interrupt assignment, it seems fixing the IRQ value via a
> > > quirk is indeed a better approach than disabling DMA wholesale. While
> > > I am not certain this will resolve the issue entirely, it looks very
> > > promising. I will investigate the IRQ mis-assignment problem further.
>
> > 1. DMAR/IOMMU Validation Failure (Error -22)
> > On modern kernels with Interrupt Remapping (DMAR) enabled, overriding
> > pdev->irq to 21 causes the dw_dmac_pci driver probe to fail with
> > -EINVAL (-22) during request_irq(). This is because the
> > DMAR/IOMMU strictly validates the PCI Requester ID (source ID) against
> > the GSI mapping defined in the ACPI _PRT table. Forcing a device
> > mapped to GSI 20 (00:15.0) to register on GSI 21 triggers a
> > source ID mismatch check, which the kernel rejects.
>
> That really seems like something we ought to be able to do, though I
> think the idiom here is to patch the ACPI tables so they are correct
> rather than quirk things in C code.  ICBW about the preferred approach
> there.
>
> BTW, if you're using a LLM to assist with analysis please don't just
> paste the output into mail.  Instead make sure you understand what the
> LLM is saying and write up the salient bits.
Hi Mark,

You are absolutely correct. The standard idiom for correcting firmware
bugs in ACPI tables is indeed using the Initrd ACPI Table Override
mechanism (compiling a modified DSDT with corrected _PRT routing and
prepending it to the initramfs).

Actually, I was just following Lukas's suggestion to modify
drivers/dma/dw/pci.c to do a quick proof-of-concept test, and I used
an AI assistant to help me write and deploy the driver quirk code.

I have previous experience with the Initrd ACPI Table Override
mechanism, so I can definitely try that on my machine next to see if
we can get DMA working properly by aligning the PCI routing and DMAR
mapping correctly).

Also, I will keep your advice in mind regarding LLM usage, and will
make sure to write up the key points myself rather than pasting raw
output.

Thanks,

Shih-Yuan

Re: [PATCH v16 5/7] spi: pxa2xx: disable DMA for Apple MacBook8,1

[Shih-Yuan Lee (FourDollars)]

On Tue, Jul 21, 2026 at 11:26 PM Shih-Yuan Lee (FourDollars)
<fourdollars@debian.org> wrote:
>
> On Tue, Jul 21, 2026 at 11:05 PM Mark Brown <broonie@debian.org> wrote:
> >
> > On Tue, Jul 21, 2026 at 10:34:20PM +0800, Shih-Yuan Lee (FourDollars) wrote:
> > > On Tue, Jul 21, 2026 at 5:26 PM Shih-Yuan Lee (FourDollars)
> > > > On Tue, Jul 21, 2026 at 5:18 PM Lukas Wunner <lukas@wunner.de> wrote:
> >
> > > > > It would seem better to fix up the incorrect interrupt number in a quirk,
> > > > > rather than disabling DMA wholesale.
> >
> > > > I appreciate the comment. Based on the Bugzilla feedback regarding the
> > > > incorrect interrupt assignment, it seems fixing the IRQ value via a
> > > > quirk is indeed a better approach than disabling DMA wholesale. While
> > > > I am not certain this will resolve the issue entirely, it looks very
> > > > promising. I will investigate the IRQ mis-assignment problem further.
> >
> > > 1. DMAR/IOMMU Validation Failure (Error -22)
> > > On modern kernels with Interrupt Remapping (DMAR) enabled, overriding
> > > pdev->irq to 21 causes the dw_dmac_pci driver probe to fail with
> > > -EINVAL (-22) during request_irq(). This is because the
> > > DMAR/IOMMU strictly validates the PCI Requester ID (source ID) against
> > > the GSI mapping defined in the ACPI _PRT table. Forcing a device
> > > mapped to GSI 20 (00:15.0) to register on GSI 21 triggers a
> > > source ID mismatch check, which the kernel rejects.
> >
> > That really seems like something we ought to be able to do, though I
> > think the idiom here is to patch the ACPI tables so they are correct
> > rather than quirk things in C code.  ICBW about the preferred approach
> > there.
> >
> > BTW, if you're using a LLM to assist with analysis please don't just
> > paste the output into mail.  Instead make sure you understand what the
> > LLM is saying and write up the salient bits.
> Hi Mark,
>
> You are absolutely correct. The standard idiom for correcting firmware
> bugs in ACPI tables is indeed using the Initrd ACPI Table Override
> mechanism (compiling a modified DSDT with corrected _PRT routing and
> prepending it to the initramfs).
>
> Actually, I was just following Lukas's suggestion to modify
> drivers/dma/dw/pci.c to do a quick proof-of-concept test, and I used
> an AI assistant to help me write and deploy the driver quirk code.
>
> I have previous experience with the Initrd ACPI Table Override
> mechanism, so I can definitely try that on my machine next to see if
> we can get DMA working properly by aligning the PCI routing and DMAR
> mapping correctly).
>
> Also, I will keep your advice in mind regarding LLM usage, and will
> make sure to write up the key points myself rather than pasting raw
> output.

Hi Mark,

I just tested the Initrd ACPI Table Override on the machine. Here is
what I found.

I patched the _PRT table in the DSDT to remap device 00:15.0 (Pin 0
and Pin 1) from GSI 20 to GSI 21 to match the SPI controller's
interrupt line, bumped the OEM Revision from 0x00080001 to 0x00080002
so the kernel would accept the override, and prepended it to the
initramfs.

The override was successfully applied:

  ACPI: Table Upgrade: override [DSDT-APPLE - MacBook]
  ACPI: DSDT ... 007EB5 (v03 APPLE  MacBook  00080002 INTL 20251212)

After rebooting, the DMA controller loaded without errors and both
dw:dmac168 and the SPI controller 0000:00:15.4 now correctly share IRQ
21:

  21: 0  0  0  0  IR-IO-APIC  21-fasteoi  dw:dmac168, 0000:00:15.4

However, SPI transfers still timed out with -ETIMEDOUT (-110) and the
IRQ 21 counter remained at zero — no interrupts were actually received
from the DMA hardware, despite the corrected ACPI routing.

This confirms the root cause is not a software IRQ routing issue but
rather that the DMA controller's interrupt line is physically
non-functional on this motherboard. macOS also does not use DMA for
this device, which is consistent with that conclusion.

It is also worth noting that Apple may have intentionally mapped the
DMA controller to GSI 20 — an otherwise unused interrupt — precisely
because the interrupt line is not physically connected. On macOS and
Windows, no DMA driver is ever loaded for this device, so the bogus
GSI 20 entry is harmless. It effectively acts as a silent signal to
the OS that interrupt-driven DMA should not be used on this platform.
Since the DMA interrupt line is physically unconnected, no completion
interrupt ever fires, causing all SPI transfers to time out with
-ETIMEDOUT (-110) and ultimately deadlocking the applespi driver.

Therefore, forcing PIO mode via a DMI quirk in spi-pxa2xx-pci remains
the only viable out-of-the-box solution for this platform.

Thanks,

Shih-Yuan