From: Anshuman Khandual <anshuman.khandual@arm.com>
To: linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org
Cc: Anshuman Khandual <anshuman.khandual@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Ryan Roberts <ryan.roberts@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Lorenzo Stoakes <ljs@kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
David Hildenbrand <david@kernel.org>,
Mike Rapoport <rppt@kernel.org>,
Linu Cherian <linu.cherian@arm.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH 15/17] arm64/mm: Add an abstraction level for tlbi_op
Date: Wed, 29 Jul 2026 17:54:50 +0530 [thread overview]
Message-ID: <20260729122452.3797443-16-anshuman.khandual@arm.com> (raw)
In-Reply-To: <20260729122452.3797443-1-anshuman.khandual@arm.com>
From: Linu Cherian <linu.cherian@arm.com>
With FEAT_D128, a new instruction aka TLBIP is being introduced for the TLB
-by-range operations which has an argument size of 128 bit.
Add an abstraction level to void (*tlbi_op)(u64 arg) helpers to support the
D128 variations when applicable.
No functional changes are introduced with this patch.
Signed-off-by: Linu Cherian <linu.cherian@arm.com>
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/include/asm/tlbflush.h | 70 ++++++++++++++++---------------
1 file changed, 37 insertions(+), 33 deletions(-)
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index e0e84332f51b..c103380ec87e 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -130,49 +130,53 @@ static inline void sme_dvmsync_batch(void)
#define TLBI_TTL_UNKNOWN INT_MAX
-typedef void (*tlbi_op)(u64 arg);
+typedef u64 tlbi_arg_t;
+#define __tlbi_wrapper(op, arg) __tlbi(op, arg)
+#define __tlbi_user_wrapper(op, arg) __tlbi_user(op, arg)
-static __always_inline void vae1is(u64 arg)
+typedef void (*tlbi_op)(tlbi_arg_t arg);
+
+static __always_inline void vae1is(tlbi_arg_t arg)
{
- __tlbi(vae1is, arg);
- __tlbi_user(vae1is, arg);
+ __tlbi_wrapper(vae1is, arg);
+ __tlbi_user_wrapper(vae1is, arg);
}
-static __always_inline void vae2is(u64 arg)
+static __always_inline void vae2is(tlbi_arg_t arg)
{
- __tlbi(vae2is, arg);
+ __tlbi_wrapper(vae2is, arg);
}
-static __always_inline void vale1(u64 arg)
+static __always_inline void vale1(tlbi_arg_t arg)
{
- __tlbi(vale1, arg);
- __tlbi_user(vale1, arg);
+ __tlbi_wrapper(vale1, arg);
+ __tlbi_user_wrapper(vale1, arg);
}
-static __always_inline void vale1is(u64 arg)
+static __always_inline void vale1is(tlbi_arg_t arg)
{
- __tlbi(vale1is, arg);
- __tlbi_user(vale1is, arg);
+ __tlbi_wrapper(vale1is, arg);
+ __tlbi_user_wrapper(vale1is, arg);
}
-static __always_inline void vale2is(u64 arg)
+static __always_inline void vale2is(tlbi_arg_t arg)
{
- __tlbi(vale2is, arg);
+ __tlbi_wrapper(vale2is, arg);
}
-static __always_inline void vaale1is(u64 arg)
+static __always_inline void vaale1is(tlbi_arg_t arg)
{
- __tlbi(vaale1is, arg);
+ __tlbi_wrapper(vaale1is, arg);
}
-static __always_inline void ipas2e1(u64 arg)
+static __always_inline void ipas2e1(tlbi_arg_t arg)
{
- __tlbi(ipas2e1, arg);
+ __tlbi_wrapper(ipas2e1, arg);
}
-static __always_inline void ipas2e1is(u64 arg)
+static __always_inline void ipas2e1is(tlbi_arg_t arg)
{
- __tlbi(ipas2e1is, arg);
+ __tlbi_wrapper(ipas2e1is, arg);
}
static __always_inline void __tlbi_level_asid(tlbi_op op, u64 addr, u32 level,
@@ -443,32 +447,32 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
* operations can only span an even number of pages. We save this for last to
* ensure 64KB start alignment is maintained for the LPA2 case.
*/
-static __always_inline void rvae1is(u64 arg)
+static __always_inline void rvae1is(tlbi_arg_t arg)
{
- __tlbi(rvae1is, arg);
- __tlbi_user(rvae1is, arg);
+ __tlbi_wrapper(rvae1is, arg);
+ __tlbi_user_wrapper(rvae1is, arg);
}
-static __always_inline void rvale1(u64 arg)
+static __always_inline void rvale1(tlbi_arg_t arg)
{
- __tlbi(rvale1, arg);
- __tlbi_user(rvale1, arg);
+ __tlbi_wrapper(rvale1, arg);
+ __tlbi_user_wrapper(rvale1, arg);
}
-static __always_inline void rvale1is(u64 arg)
+static __always_inline void rvale1is(tlbi_arg_t arg)
{
- __tlbi(rvale1is, arg);
- __tlbi_user(rvale1is, arg);
+ __tlbi_wrapper(rvale1is, arg);
+ __tlbi_user_wrapper(rvale1is, arg);
}
-static __always_inline void rvaale1is(u64 arg)
+static __always_inline void rvaale1is(tlbi_arg_t arg)
{
- __tlbi(rvaale1is, arg);
+ __tlbi_wrapper(rvaale1is, arg);
}
-static __always_inline void ripas2e1is(u64 arg)
+static __always_inline void ripas2e1is(tlbi_arg_t arg)
{
- __tlbi(ripas2e1is, arg);
+ __tlbi_wrapper(ripas2e1is, arg);
}
static __always_inline void __tlbi_range(tlbi_op op, u64 addr,
--
2.43.0
next prev parent reply other threads:[~2026-07-29 14:08 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-29 12:24 [PATCH 00/17] arm64/mm: Enable 128 bit page table entries Anshuman Khandual
2026-07-29 12:24 ` [PATCH 01/17] mm: Add read-write accessors for vm_page_prot Anshuman Khandual
2026-07-29 12:24 ` [PATCH 02/17] arm64/mm: Convert READ_ONCE() as pmdp_get() while accessing PMD Anshuman Khandual
2026-07-29 12:24 ` [PATCH 03/17] arm64/mm: Convert READ_ONCE() as pudp_get() while accessing PUD Anshuman Khandual
2026-07-29 12:24 ` [PATCH 04/17] arm64/mm: Convert READ_ONCE() as p4dp_get() while accessing P4D Anshuman Khandual
2026-07-29 12:24 ` [PATCH 05/17] arm64/mm: Convert READ_ONCE() as pgdp_get() while accessing PGD Anshuman Khandual
2026-07-29 12:24 ` [PATCH 06/17] arm64/mm: Route all pgtable reads via ptval_get() Anshuman Khandual
2026-07-29 12:24 ` [PATCH 07/17] arm64/mm: Route all pgtable writes via ptval_set() Anshuman Khandual
2026-07-29 12:24 ` [PATCH 08/17] arm64/mm: Route all pgtable atomics to central helpers Anshuman Khandual
2026-07-29 12:24 ` [PATCH 09/17] arm64/mm: Override read-write accessors for vm_page_prot Anshuman Khandual
2026-07-29 12:24 ` [PATCH 10/17] arm64/mm: Standardize printing for pgtable entries Anshuman Khandual
2026-07-29 12:24 ` [PATCH 11/17] arm64/mm: Enable fixmap with 5 level page table Anshuman Khandual
2026-07-29 12:24 ` [PATCH 12/17] arm64/mm: Enable pgtable geometry for FEAT_D128 Anshuman Khandual
2026-07-29 12:24 ` [PATCH 13/17] arm64/mm: Enable pgtable descriptor " Anshuman Khandual
2026-07-29 12:24 ` [PATCH 14/17] arm64/mm: Enable 128 bit translation Anshuman Khandual
2026-07-29 12:24 ` Anshuman Khandual [this message]
2026-07-29 12:24 ` [PATCH 16/17] arm64/mm: Enable TLBIP instruction based TLB flush Anshuman Khandual
2026-07-29 12:24 ` [PATCH 17/17] arm64/mm: Make ARM64_D128 selectable Anshuman Khandual
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