[PATCH 3/3] arm64: dts: ti: k3-am62p5: add standby cpu idle state

[Kendall Willis <k-willis@ti.com>]

Allow the A53 cores to enter standby mode on the AM62PX SoC.
The standby idle state enables the CPU cores to enter WFI through the
CPUIdle framework.

Signed-off-by: Kendall Willis <k-willis@ti.com>
---
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
index 8982a7b9f1a6a1d1a0eebe9342fdfa5d46245159..74a588e94e22a9addb44b2df495d5a8ed75967d4 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
@@ -50,6 +50,7 @@ cpu0: cpu@0 {
 			operating-points-v2 = <&a53_opp_table>;
 			clocks = <&k3_clks 135 0>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_STANDBY>;
 		};
 
 		cpu1: cpu@1 {
@@ -67,6 +68,7 @@ cpu1: cpu@1 {
 			operating-points-v2 = <&a53_opp_table>;
 			clocks = <&k3_clks 136 0>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_STANDBY>;
 		};
 
 		cpu2: cpu@2 {
@@ -84,6 +86,7 @@ cpu2: cpu@2 {
 			operating-points-v2 = <&a53_opp_table>;
 			clocks = <&k3_clks 137 0>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_STANDBY>;
 		};
 
 		cpu3: cpu@3 {
@@ -101,6 +104,20 @@ cpu3: cpu@3 {
 			operating-points-v2 = <&a53_opp_table>;
 			clocks = <&k3_clks 138 0>;
 			#cooling-cells = <2>;
+			cpu-idle-states = <&CPU_STANDBY>;
+		};
+
+		cpu_idle_states: idle-states {
+			entry-method = "psci";
+
+			CPU_STANDBY: cpu-standby {
+				compatible = "arm,idle-state";
+				entry-latency-us = <100>;
+				exit-latency-us = <50>;
+				idle-state-name = "standby";
+				min-residency-us = <500>;
+				arm,psci-suspend-param = <0x00000001>;
+			};
 		};
 	};
 

-- 
2.34.1