From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: nd <nd@arm.com>, "maz@kernel.org" <maz@kernel.org>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
Timothy Hayes <Timothy.Hayes@arm.com>,
"fuad.tabba@linux.dev" <fuad.tabba@linux.dev>
Subject: [PATCH v6 34/49] KVM: arm64: gic-v5: Add VGICv5 IST save/restore UAPI
Date: Fri, 4 Sep 2026 11:51:33 +0000 [thread overview]
Message-ID: <20260904113404.4051341-35-sascha.bischoff@arm.com> (raw)
In-Reply-To: <20260904113404.4051341-1-sascha.bischoff@arm.com>
Introduce KVM_DEV_ARM_VGIC_GRP_IST as the VGICv5 device attribute
group used to transfer SPI and LPI IST state between KVM and userspace
during migration.
The group uses struct kvm_vgic_v5_ist as a descriptor for the
userspace-owned SPI and LPI IST buffers. Each buffer contains the
architected 32-bit ISTE state for the corresponding interrupt number
space, while the host IST layout remains private to KVM.
The descriptor is architecture-specific, as it is only the payload of
an ARM VGIC device attribute.
Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
---
arch/arm64/include/uapi/asm/kvm.h | 9 +++++++++
tools/arch/arm64/include/uapi/asm/kvm.h | 9 +++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 8a023ab54bff9..65ee09bd14636 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -424,6 +424,15 @@ enum {
#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
#define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9
#define KVM_DEV_ARM_VGIC_GRP_IRS_REGS 10
+#define KVM_DEV_ARM_VGIC_GRP_IST 11
+
+struct kvm_vgic_v5_ist {
+ __u64 spi_ist_addr;
+ __u64 spi_ist_size;
+ __u64 lpi_ist_addr;
+ __u64 lpi_ist_size;
+};
+
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
diff --git a/tools/arch/arm64/include/uapi/asm/kvm.h b/tools/arch/arm64/include/uapi/asm/kvm.h
index 710a0d267347d..9998252ea8ec8 100644
--- a/tools/arch/arm64/include/uapi/asm/kvm.h
+++ b/tools/arch/arm64/include/uapi/asm/kvm.h
@@ -423,6 +423,15 @@ enum {
#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
#define KVM_DEV_ARM_VGIC_GRP_MAINT_IRQ 9
#define KVM_DEV_ARM_VGIC_GRP_IRS_REGS 10
+#define KVM_DEV_ARM_VGIC_GRP_IST 11
+
+struct kvm_vgic_v5_ist {
+ __u64 spi_ist_addr;
+ __u64 spi_ist_size;
+ __u64 lpi_ist_addr;
+ __u64 lpi_ist_size;
+};
+
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
--
2.34.1
next prev parent reply other threads:[~2026-09-04 11:52 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-04 11:34 [PATCH v6 00/49] KVM: arm64: Add GICv5 IRS support Sascha Bischoff
2026-09-04 11:34 ` [PATCH v6 01/49] irqchip/gic-v5: Allow KVM setup without a maintenance IRQ Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 02/49] irqchip/gic-v5: Provide OF IRS config frame attrs to KVM Sascha Bischoff
2026-09-04 11:35 ` [PATCH v6 03/49] irqchip/gic-v5: Set up gic_kvm_info on ACPI hosts Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 04/49] KVM: arm64: gic-v5: Define remaining IRS MMIO registers Sascha Bischoff
2026-09-04 11:36 ` [PATCH v6 05/49] arm64/sysreg: Add GICv5 GIC VDPEND encoding Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 06/49] arm64/sysreg: Update ICC_CR0_EL1 with LINK and LINK_IDLE fields Sascha Bischoff
2026-09-04 11:37 ` [PATCH v6 07/49] KVM: arm64: gic-v5: Cache host IRS ID registers Sascha Bischoff
2026-09-04 11:38 ` [PATCH v6 08/49] KVM: arm64: gic-v5: Add VPE doorbell domain Sascha Bischoff
2026-09-04 11:38 ` [PATCH v6 09/49] KVM: arm64: gic-v5: Create and manage VM and VPE tables Sascha Bischoff
2026-09-04 11:39 ` [PATCH v6 10/49] KVM: arm64: gic-v5: Introduce guest IST alloc and management Sascha Bischoff
2026-09-04 11:39 ` [PATCH v6 11/49] KVM: arm64: gic-v5: Implement VMT/vIST IRS MMIO Ops Sascha Bischoff
2026-09-04 11:40 ` [PATCH v6 12/49] KVM: arm64: vgic: Enforce model-specific vCPU limits Sascha Bischoff
2026-09-04 11:40 ` [PATCH v6 13/49] KVM: arm64: gic-v5: Implement VPE IRS MMIO Ops Sascha Bischoff
2026-09-04 11:41 ` [PATCH v6 14/49] KVM: arm64: gic-v5: Set up VMTEs and VPE doorbells Sascha Bischoff
2026-09-04 11:41 ` [PATCH v6 15/49] KVM: arm64: gic-v5: Add resident/non-resident hyp calls Sascha Bischoff
2026-09-04 11:42 ` [PATCH v6 16/49] KVM: arm64: gic-v5: Request doorbells when VPEs enter WFI Sascha Bischoff
2026-09-04 11:42 ` [PATCH v6 17/49] KVM: arm64: gic-v5: Introduce struct vgic_v5_irs and IRS base address Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 18/49] KVM: arm64: gic-v5: Add IRS IODEV support to MMIO handlers Sascha Bischoff
2026-09-04 11:43 ` [PATCH v6 19/49] KVM: arm64: gic-v5: Add KVM_VGIC_V5_ADDR_TYPE_IRS to UAPI Sascha Bischoff
2026-09-04 11:44 ` [PATCH v6 20/49] KVM: arm64: gic-v5: Add GICv5 IRS IODEV and MMIO emulation Sascha Bischoff
2026-09-04 11:44 ` [PATCH v6 21/49] KVM: arm64: gic-v5: Initialise per-VM IRS state Sascha Bischoff
2026-09-04 11:45 ` [PATCH v6 22/49] KVM: arm64: gic-v5: Register the IRS IODEV Sascha Bischoff
2026-09-04 11:45 ` [PATCH v6 23/49] KVM: arm64: gic-v5: Set IRICHPPIDIS based on IRS enable state Sascha Bischoff
2026-09-04 11:46 ` [PATCH v6 24/49] KVM: arm64: selftests: Update vGICv5 selftest to set IRS address Sascha Bischoff
2026-09-04 11:46 ` [PATCH v6 25/49] KVM: arm64: gic-v5: Add GIC VDPEND hyp call Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 26/49] KVM: arm64: gic: Introduce set_pending_state() to irq_ops Sascha Bischoff
2026-09-04 11:47 ` [PATCH v6 27/49] KVM: arm64: gic-v5: Support SPI injection Sascha Bischoff
2026-09-04 11:48 ` [PATCH v6 28/49] Documentation: KVM: Extend VGICv5 device attribute docs Sascha Bischoff
2026-09-04 11:49 ` [PATCH v6 29/49] KVM: arm64: gic-v5: Add GICv5 SPI injection to irqfd Sascha Bischoff
2026-09-04 11:49 ` [PATCH v6 30/49] KVM: arm64: gic-v5: Mask per-vCPU PPI state in vgic_v5_finalize_ppi_state() Sascha Bischoff
2026-09-04 11:50 ` [PATCH v6 31/49] KVM: arm64: gic-v5: Add GICv5 EL1 sysreg userspace accessors Sascha Bischoff
2026-09-04 11:50 ` [PATCH v6 32/49] KVM: arm64: gic-v5: Handle userspace accesses to IRS MMIO region Sascha Bischoff
2026-09-04 11:51 ` [PATCH v6 33/49] KVM: arm64: gic-v5: Add CoreSight MMIO regs to IRS Sascha Bischoff
2026-09-04 11:51 ` Sascha Bischoff [this message]
2026-09-04 11:52 ` [PATCH v6 35/49] KVM: arm64: gic-v5: Implement save/restore mechanisms for ISTs Sascha Bischoff
2026-09-04 11:52 ` [PATCH v6 36/49] Documentation: KVM: Document KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS for VGICv5 Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 37/49] Documentation: KVM: Add KVM_DEV_ARM_VGIC_GRP_IRS_REGS to VGICv5 docs Sascha Bischoff
2026-09-04 11:53 ` [PATCH v6 38/49] Documentation: KVM: Add docs for KVM_DEV_ARM_VGIC_GRP_IST Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 39/49] Documentation: KVM: Add the VGICv5 IRS save/restore sequences Sascha Bischoff
2026-09-04 11:54 ` [PATCH v6 40/49] KVM: selftests: Add VGICv5 IRS address attribute tests Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 41/49] KVM: selftests: Add VGICv5 NR_IRQS " Sascha Bischoff
2026-09-04 11:55 ` [PATCH v6 42/49] KVM: selftests: Add VGICv5 IRS_REGS " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 43/49] KVM: selftests: Add VGICv5 IST " Sascha Bischoff
2026-09-04 11:56 ` [PATCH v6 44/49] KVM: selftests: Add VGICv5 USERSPACE_PPIS tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 45/49] KVM: selftests: Add VGICv5 CPU sysreg attribute tests Sascha Bischoff
2026-09-04 11:57 ` [PATCH v6 46/49] KVM: selftests: Add VGICv5 SPI injection tests Sascha Bischoff
2026-09-04 11:58 ` [PATCH v6 47/49] KVM: selftests: Add VGICv5 LPI delivery tests Sascha Bischoff
2026-09-04 11:58 ` [PATCH v6 48/49] KVM: selftests: Add VGICv5 IST save/restore coverage Sascha Bischoff
2026-09-04 11:59 ` [PATCH v6 49/49] KVM: selftests: Add VGICv5 sparse vCPU IDs test Sascha Bischoff
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