* [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase
@ 2026-09-30 6:10 Colin Huang
2026-09-30 6:10 ` [PATCH v9 01/15] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it Colin Huang
` (14 more replies)
0 siblings, 15 replies; 16+ messages in thread
From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Ryan Chen, Billy Tsai
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
colin.huang2, Colin Huang, Carl Lee, Rex Fu, Andy Chung,
Peter Shen
This series refactors the Anacapa BMC devicetree layout to better support
development-phase hardware revisions (EVT1/EVT2/DVT) while keeping a platform
entrypoint.
Signed-off-by: Colin Huang <u8813345@gmail.com>
---
Changes in v9:
- Add four new DTS updates for Anacapa platform:
* Add E1.S FRU EEPROM definitions.
* Add NCT7363 fan controller nodes.
* Remove conflicting LTC4287 power monitor nodes.
* Update EDSFF power status signal names from PG to FLT.
- Link to v8: https://lore.kernel.org/r/20260902-anacapa-devlop-phase-devicetree-v8-0-69c8eb2a7cda@gmail.com
Changes in v8:
- Fix [Critical] The board compatible string was silently changed from "facebook,anacapa-bmc" to "facebook,anacapa"
, breaking dt-bindings and backward compatibility.
- Fix [Low] The /dts-v1/ directive is improperly placed inside a .dtsi include file instead of the top-level .dts file.
Move "/dts-v1/" into aspeed-bmc-facebook-anacapa.dts
- Link to v7: https://lore.kernel.org/r/20260901-anacapa-devlop-phase-devicetree-v7-0-0bd71d2e0105@gmail.com
Changes in v7:
- Fix [Critical] Devicetree ABI breakage due to removal of generic compatible string
keep to use compatible string "facebook,anacapa-bmc".
- Fix [Low] Redundant redefinition of inherited properties in the `evt2.dts` file.
- Fix [Low] Included devicetrees use `.dts` extension instead of `.dtsi`
aspeed-bmc-facebook-anacapa-evt1.dts -> aspeed-bmc-facebook-anacapa-evt1.dtsi
aspeed-bmc-facebook-anacapa-evt2.dts -> aspeed-bmc-facebook-anacapa-evt2.dtsi
aspeed-bmc-facebook-anacapa-dvt.dts -> aspeed-bmc-facebook-anacapa-dvt.dtsi
- Link to v6: https://lore.kernel.org/r/20260825-anacapa-devlop-phase-devicetree-v6-0-9059a2a279ce@gmail.com
Changes in v6:
- Fold the following fixes into this series:
- Remove redundant vhub pinctrl-names
- Use default SPI2 memory mapping
- Fix dt-check-style strict violations
- Move p3v3_bmc_aux node from evt1.dts to evt2.dts for dt-check-style
- Fix the patch author information
- Link to v5: https://lore.kernel.org/r/20260813-anacapa-devlop-phase-devicetree-v5-0-c7058f63dc67@gmail.com
Changes in v5:
- Remove redundant vhub pinctrl-names
- Use default SPI2 memory mapping
- Fix dt-check-style strict violations
- Add Acked-by from Conor Dooley
- Sort compatible strings in alphabetical order
- More commit message for ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it.
- Update commit message to describe both LPDB and RPDB GPIO expanders
- Link to v4: https://lore.kernel.org/r/20260805-anacapa-devlop-phase-devicetree-v4-0-5d67e0efa6c5@gmail.com
Changes in v4:
- Capitalize the first word of the short description.
- Rework the Anacapa development-phase devicetree hierarchy.
- Ensure that anacapa-evt1 generates an identical devicetree to the existing aspeed-bmc-facebook-anacapa.dts.
- Add SPI flash VCC supply.
- Simplify leakage GPIO line names.
- Add LPDB fuse monitor GPIO expander.
- Link to v3: https://lore.kernel.org/r/20260602-anacapa-devlop-phase-devicetree-v3-0-7c93c5df8d9b@gmail.com
Changes in v3:
- Restructure the EVT2 devicetree to inherit from the EVT1 devicetree, making it incremental rather than standalone.
- Add the DVT devicetree, inheriting from the EVT2 devicetree.
- Enable MCTP and FRU support for the NIC.
- Align PDB fan GPIO numbering.
- Add an EEPROM device node for the NFC adaptor board.
- Add an additional EEPROM device node for the SCM.
- Add shunt resistor values for HSC monitors
- Link to v2: https://lore.kernel.org/r/20260409-anacapa-devlop-phase-devicetree-v2-0-68f328671653@gmail.com
Changes in v2:
- Fix dtbs_check fail.
Validated by following command:
make dt_binding_check DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa.dtb
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt1.dtb
make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt2.dtb
- Link to v1: https://lore.kernel.org/r/20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@gmail.com
---
Andy Chung (1):
ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC
Carl Lee (3):
ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board
ARM: dts: aspeed: anacapa: Add NCT7363 fan controllers
ARM: dts: aspeed: anacapa: Remove LTC4287 power monitors
Colin Huang (5):
ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it
ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1
ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2
ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM
ARM: dts: aspeed: anacapa: Add E1.S FRU EEPROMs
Peter Shen (1):
ARM: dts: aspeed: anacapa: evt2: Add shunt resistor values for HSC monitors
Rex Fu (5):
ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering
ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander
ARM: dts: aspeed: anacapa: Simplify leakage GPIO line names
ARM: dts: aspeed: anacapa: Add SPI flash VCC supply
ARM: dts: aspeed: anacapa: Update EDSFF power status signals
.../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 259 +++++
.../aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 1165 ++++++++++++++++++++
.../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 467 ++++++++
.../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1077 +-----------------
4 files changed, 1892 insertions(+), 1076 deletions(-)
---
base-commit: cd7d1ef7d74ed5f5a1790a40389bc38382924556
change-id: 20260407-anacapa-devlop-phase-devicetree-4101d3f312c0
Best regards,
--
Colin Huang <u8813345@gmail.com>
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v9 01/15] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 02/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Colin Huang ` (13 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang This commit introduces an EVT1 development-phase devicetree for the Facebook Anacapa BMC. It updates the top-level wrapper DTS to include the EVT1 hardware revision file. A dedicated EVT1 DTS is added as the base revision for subsequent board variants. The EVT1 devicetree is derived from the original Anacapa devicetree and incorporates several cleanups and fixes: - Remove redundant vhub pinctrl-names - Use default SPI2 memory mapping - Fix dt-check-style strict violations Remove p3v3_bmc_aux lable to fix '[unused-lable]' warning. The top-level aspeed-bmc-facebook-anacapa.dts now includes the EVT1 devicetree, allowing EVT2 and DVT revisions to inherit from a common baseline while preserving a single build target for Anacapa. Signed-off-by: Colin Huang <u8813345@gmail.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 1127 ++++++++++++++++++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 1077 +------------------ 2 files changed, 1128 insertions(+), 1076 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi new file mode 100644 index 000000000000..5f9cfeec39cb --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi @@ -0,0 +1,1127 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "aspeed-g6.dtsi" +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/i2c/i2c.h> + +/ { + compatible = "facebook,anacapa-bmc", "aspeed,ast2600"; + model = "Facebook Anacapa BMC"; + + aliases { + i2c16 = &i2c0mux0ch0; + i2c17 = &i2c0mux0ch1; + i2c18 = &i2c0mux0ch2; + i2c19 = &i2c0mux0ch3; + i2c20 = &i2c1mux0ch0; + i2c21 = &i2c1mux0ch1; + i2c22 = &i2c1mux0ch2; + i2c23 = &i2c1mux0ch3; + i2c24 = &i2c4mux0ch0; + i2c25 = &i2c4mux0ch1; + i2c26 = &i2c4mux0ch2; + i2c27 = &i2c4mux0ch3; + i2c28 = &i2c4mux0ch4; + i2c29 = &i2c4mux0ch5; + i2c30 = &i2c4mux0ch6; + i2c31 = &i2c4mux0ch7; + i2c32 = &i2c8mux0ch0; + i2c33 = &i2c8mux0ch1; + i2c34 = &i2c8mux0ch2; + i2c35 = &i2c8mux0ch3; + i2c36 = &i2c10mux0ch0; + i2c37 = &i2c10mux0ch1; + i2c38 = &i2c10mux0ch2; + i2c39 = &i2c10mux0ch3; + i2c40 = &i2c10mux0ch4; + i2c41 = &i2c10mux0ch5; + i2c42 = &i2c10mux0ch6; + i2c43 = &i2c10mux0ch7; + i2c44 = &i2c11mux0ch0; + i2c45 = &i2c11mux0ch1; + i2c46 = &i2c11mux0ch2; + i2c47 = &i2c11mux0ch3; + i2c48 = &i2c11mux0ch4; + i2c49 = &i2c11mux0ch5; + i2c50 = &i2c11mux0ch6; + i2c51 = &i2c11mux0ch7; + i2c52 = &i2c13mux0ch0; + i2c53 = &i2c13mux0ch1; + i2c54 = &i2c13mux0ch2; + i2c55 = &i2c13mux0ch3; + i2c56 = &i2c13mux0ch4; + i2c57 = &i2c13mux0ch5; + i2c58 = &i2c13mux0ch6; + i2c59 = &i2c13mux0ch7; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + }; + + chosen { + stdout-path = "serial4:57600n8"; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 2>; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; + label = "bmc_heartbeat_amber"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + default-state = "off"; + gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; + label = "fp_id_amber"; + }; + }; + + memory@80000000 { + reg = <0x80000000 0x80000000>; + device_type = "memory"; + }; + + regulator-p3v3-bmc-aux { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "p3v3_bmc_aux"; + }; + + reserved-memory { + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gfx_memory: framebuffer { + compatible = "shared-dma-pool"; + alignment = <0x01000000>; + reusable; + size = <0x01000000>; + }; + + video_engine_memory: video { + compatible = "shared-dma-pool"; + alignment = <0x00100000>; + reusable; + size = <0x02c00000>; + }; + }; + + spi { + compatible = "spi-gpio"; + #address-cells = <1>; + cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; + + miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; + mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; + num-chipselects = <1>; + sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; + #size-cells = <0>; + + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <33000000>; + }; + }; +}; + +&adc0 { + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; + pinctrl-names = "default"; + aspeed,int-vref-microvolt = <2500000>; + + status = "okay"; +}; + +&adc1 { + pinctrl-0 = <&pinctrl_adc10_default>; + pinctrl-names = "default"; + aspeed,int-vref-microvolt = <2500000>; + + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&fmc { + status = "okay"; + + flash@0 { + label = "bmc"; + spi-max-frequency = <50000000>; + m25p,fast-read; + + status = "okay"; +#include "openbmc-flash-layout-128.dtsi" + }; + + flash@1 { + label = "alt-bmc"; + spi-max-frequency = <50000000>; + m25p,fast-read; + + status = "okay"; + }; +}; + +&gfx { + memory-region = <&gfx_memory>; + + status = "okay"; +}; + +&gpio0 { + gpio-line-names = + + /*A0-A7*/ + "","","","","","","","", + + /*B0-B7*/ + "BATTERY_DETECT", "", "", "BMC_READY", + "", "FM_ID_LED", "", "", + + /*C0-C7*/ + "","","","","","","","", + + /*D0-D7*/ + "","","","","","","","", + + /*E0-E7*/ + "","","","","","","","", + + /*F0-F7*/ + "","","","","","","","", + + /*G0-G7*/ + "FM_MUX1_SEL", "", "", "", + "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", + + /*H0-H7*/ + "","","","","","","","", + + /*I0-I7*/ + "", "", "", "", + "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", + + /*J0-J7*/ + "","","","","","","","", + + /*K0-K7*/ + "","","","","","","","", + + /*L0-L7*/ + "","","","","","","","", + + /*M0-M7*/ + "", "BMC_FRU_WP", "", "", + "", "", "", "", + + /*N0-N7*/ + "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", + "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", + + /*O0-O7*/ + "","","","","","","","", + + /*P0-P7*/ + "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", + "PWR_LED", "", "", "BMC_HEARTBEAT_N", + + /*Q0-Q7*/ + "","","","","","","","", + + /*R0-R7*/ + "","","","","","","","", + + /*S0-S7*/ + "", "", "SYS_BMC_PWRBTN_N", "", + "", "", "", "RUN_POWER_FAULT", + + /*T0-T7*/ + "","","","","","","","", + + /*U0-U7*/ + "","","","","","","","", + + /*V0-V7*/ + "","","","","","","","", + + /*W0-W7*/ + "","","","","","","","", + + /*X0-X7*/ + "","","","","","","","", + + /*Y0-Y7*/ + "","","","","","","","", + + /*Z0-Z7*/ + "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", + "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; +}; + +&gpio1 { + gpio-line-names = + /*18A0-18A7*/ + "","","","","","","","", + + /*18B0-18B7*/ + "","","","", + "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", + "FM_BOARD_BMC_REV_ID2", "", + + /*18C0-18C7*/ + "","","","","","","","", + + /*18D0-18D7*/ + "","","","","","","","", + + /*18E0-18E3*/ + "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; +}; + +// L Bridge Board +&i2c0 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c2048"; + reg = <0x50>; + pagesize = <128>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + i2c-mux-idle-disconnect; + #size-cells = <0>; + + i2c0mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c0mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c0mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c0mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// R Bridge Board +&i2c1 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c2048"; + reg = <0x50>; + pagesize = <128>; + }; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + i2c-mux-idle-disconnect; + #size-cells = <0>; + + i2c1mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// MB - E1.S +&i2c4 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + i2c-mux-idle-disconnect; + #size-cells = <0>; + + i2c4mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c4mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// AMC +&i2c5 { + status = "okay"; +}; + +// MB +&i2c6 { + status = "okay"; + + // HPM FRU + eeprom@50 { + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + +// SCM +&i2c7 { + status = "okay"; +}; + +// MB - PDB +&i2c8 { + status = "okay"; + + i2c-mux@72 { + compatible = "nxp,pca9546"; + reg = <0x72>; + #address-cells = <1>; + i2c-mux-idle-disconnect; + #size-cells = <0>; + + i2c8mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "", + "", "", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", + "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + interrupt-parent = <&sgpiom0>; + + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", + "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", + "", "RPDB_FAN1_PRSNT_N_R", + "", "RPDB_FAN2_PRSNT_N_R", + "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", + "", ""; + interrupt-parent = <&sgpiom0>; + + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + + // R-PDB FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + + i2c8mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N","", + "","", + "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R",""; + interrupt-parent = <&sgpiom0>; + + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + + gpio@24 { + compatible = "nxp,pca9555"; + reg = <0x24>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", + "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", + "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", + "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", + "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", + "","", + "","", + "",""; + interrupt-parent = <&sgpiom0>; + + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + + // L-PDB FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + + i2c8mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c8mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// SCM +&i2c9 { + status = "okay"; + + // SCM FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + + // BSM FRU + eeprom@56 { + compatible = "atmel,24c64"; + reg = <0x56>; + }; +}; + +// R Bridge Board +&i2c10 { + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + i2c-mux-idle-disconnect; + #size-cells = <0>; + + i2c10mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "","", + "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", + "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", + "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", + "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", + "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", + "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", + "",""; + }; + + // R Bridge Board FRU + eeprom@52 { + compatible = "atmel,24c256"; + reg = <0x52>; + }; + }; + + i2c10mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c10mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// L Bridge Board +&i2c11 { + status = "okay"; + + i2c-mux@71 { + compatible = "nxp,pca9548"; + reg = <0x71>; + #address-cells = <1>; + i2c-mux-idle-disconnect; + #size-cells = <0>; + + i2c11mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + + gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "","", + "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", + "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", + "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", + "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", + "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", + "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", + "",""; + }; + + // L Bridge Board FRU + eeprom@52 { + compatible = "atmel,24c256"; + reg = <0x52>; + }; + }; + + i2c11mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c11mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +// Debug Card +&i2c12 { + status = "okay"; +}; + +// MB +&i2c13 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + i2c-mux-idle-disconnect; + #size-cells = <0>; + + i2c13mux0ch0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux0ch1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux0ch2: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux0ch3: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + adc@1f { + compatible = "ti,adc128d818"; + reg = <0x1f>; + ti,mode = /bits/ 8 <1>; + }; + }; + + i2c13mux0ch4: i2c@4 { + reg = <4>; + #address-cells = <1>; + #size-cells = <0>; + + // HPM BRD ID FRU + eeprom@51 { + compatible = "atmel,24c256"; + reg = <0x51>; + }; + }; + + i2c13mux0ch5: i2c@5 { + reg = <5>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux0ch6: i2c@6 { + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c13mux0ch7: i2c@7 { + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + + nfc@28 { + compatible = "nxp,nxp-nci-i2c"; + reg = <0x28>; + + enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&sgpiom0>; + + interrupts = <156 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + }; +}; + +// SCM +&i2c14 { + status = "okay"; +}; + +&i2c15 { + status = "okay"; +}; + +&kcs2 { + aspeed,lpc-io-reg = <0xca8>; + + status = "okay"; +}; + +&kcs3 { + aspeed,lpc-io-reg = <0xca2>; + + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&mac2 { + pinctrl-0 = <&pinctrl_ncsi3_default>; + pinctrl-names = "default"; + use-ncsi; + + status = "okay"; +}; + +&sgpiom0 { + bus-frequency = <2000000>; + gpio-line-names = + /*in - out - in - out */ + /* A0-A7 line 0-15 */ + "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", + "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", + "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", + "", "", "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "", + "Channel5_leakage_EAM1", "", + "Channel6_leakage_CPU_DIMM", "", + "Channel7_leakage_EAM2", "", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "", "", "", + "", "", "", "", + "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", + "", "", "", "", + + /* D0-D7 line 48-63 */ + "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", + "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", + "AMC_BRD_PRSNT_CPLD_L", "", "", "", + "", "", "", "", + + /* E0-E7 line 64-79 */ + "AMC_PDB_EAMHSC0_CPLD_EN_R", "", + "AMC_PDB_EAMHSC1_CPLD_EN_R", "", + "AMC_PDB_EAMHSC2_CPLD_EN_R", "", + "AMC_PDB_EAMHSC3_CPLD_EN_R", "", + "", "", "", "", + "", "", "", "", + + /* F0-F7 line 80-95 */ + "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", + "PWRGD_PVDDCR_CPU0_P0", "", + "", "", "", "", + "", "", "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "PWRGD_CHEH_CPU0_FPGA", "", + "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", + "", "", + + /* H0-H7 line 112-127 */ + "PWRGD_P3V3", "", + "P12V_DDR_IP_PWRGD_R", "", + "P12V_DDR_AH_PWRGD_R", "", + "PWRGD_P12V_VRM1_CPLD_PG_R", "", + "PWRGD_P12V_VRM0_CPLD_PG_R", "", + "PWRGD_PDB_HSC4_CPLD_PG_R", "", + "PWRGD_PVDD18_S5_P0_PG", "", + "PWRGD_PVDD33_S5_P0_PG", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "EAM0_CPU_MOD_PWR_GD_R", "", + "EAM1_CPU_MOD_PWR_GD_R", "", + "PRSNT_EDSFF_BOOT_N", "", + "EAM3_CPU_MOD_PWR_GD_R", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BIRDGE_R", "", + "PRSNT_R_BIRDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "", "", "", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", + "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", + "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "", "", "", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "", + "FM_PWRGD_CPU0_PWROK", "", + "wS5_PWR_Ready", "", + "wS0_ON_N", "PWRGD_P1V0_AUX"; + + ngpios = <128>; + + status = "okay"; +}; + +// BIOS Flash +&spi2 { + pinctrl-0 = <&pinctrl_spi2_default>; + + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + label = "pnor"; + spi-max-frequency = <12000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + + status = "okay"; + }; +}; + +// HOST BIOS Debug +&uart1 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +// BMC Debug Console +&uart5 { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&vhub { + status = "okay"; +}; + +&video { + memory-region = <&video_engine_memory>; + + status = "okay"; +}; + +&wdt1 { + pinctrl-0 = <&pinctrl_wdtrst1_default>; + pinctrl-names = "default"; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; + aspeed,ext-push-pull; + aspeed,external-signal; + aspeed,reset-type = "soc"; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 1fddf3a5d138..5e76076bdcd4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,1079 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include "aspeed-g6.dtsi" -#include <dt-bindings/gpio/aspeed-gpio.h> -#include <dt-bindings/i2c/i2c.h> - -/ { - model = "Facebook Anacapa BMC"; - compatible = "facebook,anacapa-bmc", "aspeed,ast2600"; - - aliases { - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - serial3 = &uart4; - serial4 = &uart5; - i2c16 = &i2c0mux0ch0; - i2c17 = &i2c0mux0ch1; - i2c18 = &i2c0mux0ch2; - i2c19 = &i2c0mux0ch3; - i2c20 = &i2c1mux0ch0; - i2c21 = &i2c1mux0ch1; - i2c22 = &i2c1mux0ch2; - i2c23 = &i2c1mux0ch3; - i2c24 = &i2c4mux0ch0; - i2c25 = &i2c4mux0ch1; - i2c26 = &i2c4mux0ch2; - i2c27 = &i2c4mux0ch3; - i2c28 = &i2c4mux0ch4; - i2c29 = &i2c4mux0ch5; - i2c30 = &i2c4mux0ch6; - i2c31 = &i2c4mux0ch7; - i2c32 = &i2c8mux0ch0; - i2c33 = &i2c8mux0ch1; - i2c34 = &i2c8mux0ch2; - i2c35 = &i2c8mux0ch3; - i2c36 = &i2c10mux0ch0; - i2c37 = &i2c10mux0ch1; - i2c38 = &i2c10mux0ch2; - i2c39 = &i2c10mux0ch3; - i2c40 = &i2c10mux0ch4; - i2c41 = &i2c10mux0ch5; - i2c42 = &i2c10mux0ch6; - i2c43 = &i2c10mux0ch7; - i2c44 = &i2c11mux0ch0; - i2c45 = &i2c11mux0ch1; - i2c46 = &i2c11mux0ch2; - i2c47 = &i2c11mux0ch3; - i2c48 = &i2c11mux0ch4; - i2c49 = &i2c11mux0ch5; - i2c50 = &i2c11mux0ch6; - i2c51 = &i2c11mux0ch7; - i2c52 = &i2c13mux0ch0; - i2c53 = &i2c13mux0ch1; - i2c54 = &i2c13mux0ch2; - i2c55 = &i2c13mux0ch3; - i2c56 = &i2c13mux0ch4; - i2c57 = &i2c13mux0ch5; - i2c58 = &i2c13mux0ch6; - i2c59 = &i2c13mux0ch7; - }; - - chosen { - stdout-path = "serial4:57600n8"; - }; - - iio-hwmon { - compatible = "iio-hwmon"; - io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, - <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, - <&adc1 2>; - }; - - leds { - compatible = "gpio-leds"; - - led-0 { - label = "bmc_heartbeat_amber"; - gpios = <&gpio0 ASPEED_GPIO(P, 7) GPIO_ACTIVE_LOW>; - linux,default-trigger = "heartbeat"; - }; - - led-1 { - label = "fp_id_amber"; - default-state = "off"; - gpios = <&gpio0 ASPEED_GPIO(B, 5) GPIO_ACTIVE_HIGH>; - }; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x80000000>; - }; - - reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - video_engine_memory: video { - size = <0x02c00000>; - alignment = <0x00100000>; - compatible = "shared-dma-pool"; - reusable; - }; - - gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; - }; - }; - - p3v3_bmc_aux: regulator-p3v3-bmc-aux { - compatible = "regulator-fixed"; - regulator-name = "p3v3_bmc_aux"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - spi_gpio: spi { - compatible = "spi-gpio"; - #address-cells = <1>; - #size-cells = <0>; - - sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>; - mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>; - miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>; - num-chipselects = <1>; - status = "okay"; - - tpm@0 { - compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; - spi-max-frequency = <33000000>; - reg = <0>; - }; - }; -}; - -&adc0 { - aspeed,int-vref-microvolt = <2500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default - &pinctrl_adc2_default &pinctrl_adc3_default - &pinctrl_adc4_default &pinctrl_adc5_default - &pinctrl_adc6_default &pinctrl_adc7_default>; - status = "okay"; -}; - -&adc1 { - aspeed,int-vref-microvolt = <2500000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc10_default>; - status = "okay"; -}; - -&ehci1 { - status = "okay"; -}; - -&fmc { - status = "okay"; - - flash@0 { - status = "okay"; - m25p,fast-read; - label = "bmc"; - spi-max-frequency = <50000000>; -#include "openbmc-flash-layout-128.dtsi" - }; - - flash@1 { - status = "okay"; - m25p,fast-read; - label = "alt-bmc"; - spi-max-frequency = <50000000>; - }; -}; - -&gfx { - status = "okay"; - memory-region = <&gfx_memory>; -}; - -&gpio0 { - gpio-line-names = - - /*A0-A7*/ - "","","","","","","","", - - /*B0-B7*/ - "BATTERY_DETECT", "", "", "BMC_READY", - "", "FM_ID_LED", "", "", - - /*C0-C7*/ - "","","","","","","","", - - /*D0-D7*/ - "","","","","","","","", - - /*E0-E7*/ - "","","","","","","","", - - /*F0-F7*/ - "","","","","","","","", - - /*G0-G7*/ - "FM_MUX1_SEL", "", "", "", - "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N", - - /*H0-H7*/ - "","","","","","","","", - - /*I0-I7*/ - "", "", "", "", - "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "", - - /*J0-J7*/ - "","","","","","","","", - - /*K0-K7*/ - "","","","","","","","", - - /*L0-L7*/ - "","","","","","","","", - - /*M0-M7*/ - "", "BMC_FRU_WP", "", "", - "", "", "", "", - - /*N0-N7*/ - "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3", - "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7", - - /*O0-O7*/ - "","","","","","","","", - - /*P0-P7*/ - "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "", - "PWR_LED", "", "", "BMC_HEARTBEAT_N", - - /*Q0-Q7*/ - "","","","","","","","", - - /*R0-R7*/ - "","","","","","","","", - - /*S0-S7*/ - "", "", "SYS_BMC_PWRBTN_N", "", - "", "", "", "RUN_POWER_FAULT", - - /*T0-T7*/ - "","","","","","","","", - - /*U0-U7*/ - "","","","","","","","", - - /*V0-V7*/ - "","","","","","","","", - - /*W0-W7*/ - "","","","","","","","", - - /*X0-X7*/ - "","","","","","","","", - - /*Y0-Y7*/ - "","","","","","","","", - - /*Z0-Z7*/ - "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK", - "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", ""; -}; - -&gpio1 { - gpio-line-names = - /*18A0-18A7*/ - "","","","","","","","", - - /*18B0-18B7*/ - "","","","", - "FM_BOARD_BMC_REV_ID0", "FM_BOARD_BMC_REV_ID1", - "FM_BOARD_BMC_REV_ID2", "", - - /*18C0-18C7*/ - "","","","","","","","", - - /*18D0-18D7*/ - "","","","","","","","", - - /*18E0-18E3*/ - "FM_BMC_PROT_LS_EN", "AC_PWR_BMC_BTN_N", "", ""; -}; - -// L Bridge Board -&i2c0 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c2048"; - reg = <0x50>; - pagesize = <128>; - }; - - i2c-mux@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c0mux0ch0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c0mux0ch1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c0mux0ch2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c0mux0ch3: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -// R Bridge Board -&i2c1 { - status = "okay"; - - eeprom@50 { - compatible = "atmel,24c2048"; - reg = <0x50>; - pagesize = <128>; - }; - - i2c-mux@70 { - compatible = "nxp,pca9546"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c1mux0ch0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c1mux0ch1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c1mux0ch2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c1mux0ch3: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -// MB - E1.S -&i2c4 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c4mux0ch0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c4mux0ch1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c4mux0ch2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c4mux0ch3: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c4mux0ch4: i2c@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c4mux0ch5: i2c@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c4mux0ch6: i2c@6 { - reg = <6>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c4mux0ch7: i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -// AMC -&i2c5 { - status = "okay"; -}; - -// MB -&i2c6 { - status = "okay"; - - // HPM FRU - eeprom@50 { - compatible = "atmel,24c256"; - reg = <0x50>; - }; -}; - -// SCM -&i2c7 { - status = "okay"; - - -}; - -// MB - PDB -&i2c8 { - status = "okay"; - - i2c-mux@72 { - compatible = "nxp,pca9546"; - reg = <0x72>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c8mux0ch0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - adc@1f { - compatible = "ti,adc128d818"; - reg = <0x1f>; - ti,mode = /bits/ 8 <1>; - }; - - gpio@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&sgpiom0>; - interrupts = <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names = - "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TEMP75_U8_ALERT_R_N", - "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", - "RPDB_FAN_CT_FAN_FAIL_R_N", "", - "", "", - "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", - "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", - "RPDB_I2C_P12V_MB_VRM_ALERT_R_N", - "RPDB_I2C_P12V_STBY_VRM_ALERT_R_N", - "RPDB_PGD_P3V3_STBY_PWRGD_R", - "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; - }; - - gpio@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&sgpiom0>; - interrupts = <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names = - "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", - "RPDB_PWRGD_P50V_HSC4_SYS_R", - "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", - "RPDB_P50V_FAN1_R2_PG", "RPDB_P50V_FAN2_R2_PG", - "RPDB_P50V_FAN3_R2_PG", "RPDB_P50V_FAN4_R2_PG", - "", "RPDB_FAN1_PRSNT_N_R", - "", "RPDB_FAN2_PRSNT_N_R", - "RPDB_FAN3_PRSNT_N_R", "RPDB_FAN4_PRSNT_N_R", - "", ""; - }; - - // R-PDB FRU - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - }; - i2c8mux0ch1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - gpio@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&sgpiom0>; - interrupts = <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names = - "LPDB_FAN_FULL_SPEED_R_N","LPDB_I2C_TEMP75_U8_ALERT_R_N", - "LPDB_I2C_TMP432_U29_ALERT_R_N","LPDB_GLOBAL_WP", - "LPDB_FAN_CT_FAN_FAIL_R_N","", - "","", - "LPDB_ALERT_P50V_HSC0_R_N","LPDB_ALERT_P50V_HSC1_R_N", - "LPDB_ALERT_P50V_HSC5_R_N","LPDB_I2C_P12V_SW_VRM_ALERT_R_N", - "LPDB_EAM0_PRSNT_MOS_N_R","LPDB_EAM1_PRSNT_MOS_N_R", - "LPDB_PWRGD_P50V_HSC5_SYS_R",""; - }; - - gpio@24 { - compatible = "nxp,pca9555"; - reg = <0x24>; - gpio-controller; - #gpio-cells = <2>; - - interrupt-parent = <&sgpiom0>; - interrupts = <174 IRQ_TYPE_LEVEL_LOW>; - - gpio-line-names = - "LPDB_P50V_FAN1_R2_PG","LPDB_P50V_FAN2_R2_PG", - "LPDB_P50V_FAN3_R2_PG","LPDB_P50V_FAN4_R2_PG", - "LPDB_P50V_FAN5_R2_PG","LPDB_FAN1_PRSNT_N_R", - "LPDB_FAN2_PRSNT_N_R","LPDB_FAN3_PRSNT_N_R", - "LPDB_FAN4_PRSNT_N_R","LPDB_FAN5_PRSNT_N_R", - "","", - "","", - "",""; - }; - - // L-PDB FRU - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - }; - i2c8mux0ch2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c8mux0ch3: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -// SCM -&i2c9 { - status = "okay"; - - // SCM FRU - eeprom@50 { - compatible = "atmel,24c128"; - reg = <0x50>; - }; - - // BSM FRU - eeprom@56 { - compatible = "atmel,24c64"; - reg = <0x56>; - }; -}; - -// R Bridge Board -&i2c10 { - status = "okay"; - - i2c-mux@71 { - compatible = "nxp,pca9548"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c10mux0ch0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c10mux0ch1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c10mux0ch2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c10mux0ch3: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c10mux0ch4: i2c@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c10mux0ch5: i2c@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - - gpio@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "","", - "","RBB_CPLD_REFRESH_IN_PRGRS_R_L", - "RBB_EAM0_NIC_CBL_PRSNT_R_L","RBB_EAM1_NIC_CBL_PRSNT_R_L", - "RBB_AINIC_JTAG_MUX_R2_SEL","RBB_SPI_MUX0_R2_SEL", - "RBB_AINIC_PRSNT_R_L","RBB_AINIC_OE_R_N", - "RBB_AINIC_BOARD_R2_ID","RBB_RST_USB2_HUB_R_N", - "RBB_RST_FT4222_R_N","RBB_RST_MCP2210_R_N", - "",""; - }; - - // R Bridge Board FRU - eeprom@52 { - compatible = "atmel,24c256"; - reg = <0x52>; - }; - }; - i2c10mux0ch6: i2c@6 { - reg = <6>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c10mux0ch7: i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -// L Bridge Board -&i2c11 { - status = "okay"; - - i2c-mux@71 { - compatible = "nxp,pca9548"; - reg = <0x71>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c11mux0ch0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c11mux0ch1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c11mux0ch2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c11mux0ch3: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c11mux0ch4: i2c@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c11mux0ch5: i2c@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - - gpio@22 { - compatible = "nxp,pca9555"; - reg = <0x22>; - gpio-controller; - #gpio-cells = <2>; - - gpio-line-names = - "","", - "","LBB_CPLD_REFRESH_IN_PRGRS_R_L", - "LBB_EAM0_NIC_CBL_PRSNT_R_L","LBB_EAM1_NIC_CBL_PRSNT_R_L", - "LBB_AINIC_JTAG_MUX_R2_SEL","LBB_SPI_MUX0_R2_SEL", - "LBB_AINIC_PRSNT_R_L","LBB_AINIC_OE_R_N", - "LBB_AINIC_BOARD_R2_ID","LBB_RST_USB2_HUB_R_N", - "LBB_RST_FT4222_R_N","LBB_RST_MCP2210_R_N", - "",""; - }; - - // L Bridge Board FRU - eeprom@52 { - compatible = "atmel,24c256"; - reg = <0x52>; - }; - }; - i2c11mux0ch6: i2c@6 { - reg = <6>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c11mux0ch7: i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -// Debug Card -&i2c12 { - status = "okay"; -}; - -// MB -&i2c13 { - status = "okay"; - - i2c-mux@70 { - compatible = "nxp,pca9548"; - reg = <0x70>; - #address-cells = <1>; - #size-cells = <0>; - i2c-mux-idle-disconnect; - - i2c13mux0ch0: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c13mux0ch1: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c13mux0ch2: i2c@2 { - reg = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c13mux0ch3: i2c@3 { - reg = <3>; - #address-cells = <1>; - #size-cells = <0>; - - adc@1f { - compatible = "ti,adc128d818"; - reg = <0x1f>; - ti,mode = /bits/ 8 <1>; - }; - }; - i2c13mux0ch4: i2c@4 { - reg = <4>; - #address-cells = <1>; - #size-cells = <0>; - - // HPM BRD ID FRU - eeprom@51 { - compatible = "atmel,24c256"; - reg = <0x51>; - }; - }; - i2c13mux0ch5: i2c@5 { - reg = <5>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c13mux0ch6: i2c@6 { - reg = <6>; - #address-cells = <1>; - #size-cells = <0>; - }; - i2c13mux0ch7: i2c@7 { - reg = <7>; - #address-cells = <1>; - #size-cells = <0>; - - nfc@28 { - compatible = "nxp,nxp-nci-i2c"; - reg = <0x28>; - - interrupt-parent = <&sgpiom0>; - interrupts = <156 IRQ_TYPE_LEVEL_HIGH>; - - enable-gpios = <&sgpiom0 241 GPIO_ACTIVE_HIGH>; - }; - }; - }; -}; - -// SCM -&i2c14 { - status = "okay"; -}; - -&i2c15 { - status = "okay"; -}; - -&kcs2 { - aspeed,lpc-io-reg = <0xca8>; - status = "okay"; -}; - -&kcs3 { - aspeed,lpc-io-reg = <0xca2>; - status = "okay"; -}; - -&lpc_ctrl { - status = "okay"; -}; - -&mac2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ncsi3_default>; - use-ncsi; -}; - -&sgpiom0 { - ngpios = <128>; - bus-frequency = <2000000>; - gpio-line-names = - /*in - out - in - out */ - /* A0-A7 line 0-15 */ - "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N", - "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0", - "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle", - "", "", "", "", - - /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "", - "Channel5_leakage_EAM1", "", - "Channel6_leakage_CPU_DIMM", "", - "Channel7_leakage_EAM2", "", - - /* C0-C7 line 32-47 */ - "RSVD_RMC_GPIO3", "", "", "", - "", "", "", "", - "LEAK_DETECT_RMC_N", "JTAG_CPLD_TRST_R_N", "", "", - "", "", "", "", - - /* D0-D7 line 48-63 */ - "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "", - "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "", - "AMC_BRD_PRSNT_CPLD_L", "", "", "", - "", "", "", "", - - /* E0-E7 line 64-79 */ - "AMC_PDB_EAMHSC0_CPLD_EN_R", "", - "AMC_PDB_EAMHSC1_CPLD_EN_R", "", - "AMC_PDB_EAMHSC2_CPLD_EN_R", "", - "AMC_PDB_EAMHSC3_CPLD_EN_R", "", - "", "", "", "", - "", "", "", "", - - /* F0-F7 line 80-95 */ - "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY", - "PWRGD_PVDDCR_CPU0_P0", "", - "", "", "", "", - "", "", "", "", - - /* G0-G7 line 96-111 */ - "L_PRSNT_EDSFF0_N", "", - "L_PRSNT_EDSFF1_N", "", - "R_PRSNT_EDSFF2_N", "", - "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", - "PWRGD_CHEH_CPU0_FPGA", "", - "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD", - "", "", - - /* H0-H7 line 112-127 */ - "PWRGD_P3V3", "", - "P12V_DDR_IP_PWRGD_R", "", - "P12V_DDR_AH_PWRGD_R", "", - "PWRGD_P12V_VRM1_CPLD_PG_R", "", - "PWRGD_P12V_VRM0_CPLD_PG_R", "", - "PWRGD_PDB_HSC4_CPLD_PG_R", "", - "PWRGD_PVDD18_S5_P0_PG", "", - "PWRGD_PVDD33_S5_P0_PG", "", - - /* I0-I7 line 128-143 */ - "EAM0_BRD_PRSNT_R_L", "", - "EAM1_BRD_PRSNT_R_L", "", - "EAM2_BRD_PRSNT_R_L", "", - "EAM3_BRD_PRSNT_R_L", "", - "EAM0_CPU_MOD_PWR_GD_R", "", - "EAM1_CPU_MOD_PWR_GD_R", "", - "PRSNT_EDSFF_BOOT_N", "", - "EAM3_CPU_MOD_PWR_GD_R", "", - - /* J0-J7 line 144-159 */ - "PRSNT_L_BIRDGE_R", "", - "PRSNT_R_BIRDGE_R", "", - "BRIDGE_L_MAIN_PG_R", "", - "BRIDGE_R_MAIN_PG_R", "", - "BRIDGE_L_STBY_PG_R", "", - "BRIDGE_R_STBY_PG_R", "", - "", "", "", "", - - /* K0-K7 line 160-175 */ - "ADC_I2C_ALERT_N", "", - "TEMP_I2C_ALERT_R_L", "", - "CPU0_VR_SMB_ALERT_CPLD_N", "", - "COVER_INTRUDER_R_N", "", - "HANDLE_INTRUDER_CPLD_N", "", - "IRQ_MCIO_CPLD_WAKE_R_N", "", - "APML_CPU0_ALERT_R_N", "", - "PDB_ALERT_R_N", "", - - /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", "R_EDSFF3_PG", "", - "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "", - "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "", - - /* M0-M7 line 192-207 */ - "EAM0_SMERR_CPLD_R_L", "", - "EAM1_SMERR_CPLD_R_L", "", - "EAM2_SMERR_CPLD_R_L", "", - "EAM3_SMERR_CPLD_R_L", "", - "CPU0_SMERR_N_R", "", - "CPU0_NV_SAVE_N_R", "", - "PDB_PWR_LOSS_CPLD_N", "", - "IRQ_BMC_SMI_ACTIVE_R_N", "", - - /* N0-N7 line 208-223 */ - "AMCROT_BMC_S5_RDY_R", "", - "AMC_RDY_R", "", - "AMC_STBY_PGOOD_R", "", - "CPU_AMC_SLP_S5_R_L", "", - "AMC_CPU_EAMPG_R", "", - "", "", "", "", - - /* O0-O7 line 224-239 */ - "HPM_PWR_FAIL", "Port80_b0", - "FM_DIMM_IP_FAIL", "Port80_b1", - "FM_DIMM_AH_FAIL", "Port80_b2", - "AMC_THERMTRIP_ASSERT", "Port80_b3", - "CPU_THERMTRIP_ASSERT", "Port80_b4", - "PVDDCR_SOC_P0_OCP_L", "Port80_b5", - "CPLD_SGPIO_RDY", "Port80_b6", - "", "Port80_b7", - - /* P0-P7 line 240-255 */ - "CPU0_SLP_S5_N_R", "NFC_VEN", - "CPU0_SLP_S3_N_R", "", - "FM_CPU0_PWRGD", "", - "PWRGD_RMC", "", - "FM_RST_CPU0_RESET_N", "", - "FM_PWRGD_CPU0_PWROK", "", - "wS5_PWR_Ready", "", - "wS0_ON_N", "PWRGD_P1V0_AUX"; - status = "okay"; -}; - -// BIOS Flash -&spi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_spi2_default>; - status = "okay"; - reg = <0x1e631000 0xc4>, <0x50000000 0x8000000>; - - flash@0 { - compatible = "jedec,spi-nor"; - label = "pnor"; - spi-max-frequency = <12000000>; - spi-tx-bus-width = <2>; - spi-rx-bus-width = <2>; - status = "okay"; - }; -}; - -// HOST BIOS Debug -&uart1 { - status = "okay"; -}; - -&uart3 { - status = "okay"; -}; - -&uart4 { - status = "okay"; -}; - -// BMC Debug Console -&uart5 { - status = "okay"; -}; - -&uart_routing { - status = "okay"; -}; - -&uhci { - status = "okay"; -}; - -&vhub { - status = "okay"; - pinctrl-names = "default"; -}; - -&video { - status = "okay"; - memory-region = <&video_engine_memory>; -}; - -&wdt1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdtrst1_default>; - aspeed,reset-type = "soc"; - aspeed,external-signal; - aspeed,ext-push-pull; - aspeed,ext-active-high; - aspeed,ext-pulse-duration = <256>; - status = "okay"; -}; +#include "aspeed-bmc-facebook-anacapa-evt1.dtsi" -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 02/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang 2026-09-30 6:10 ` [PATCH v9 01/15] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 03/15] ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2 Colin Huang ` (12 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC EVT2 hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang <u8813345@gmail.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 167 +++++++++++++++++++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 168 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi new file mode 100644 index 000000000000..c43090618c4a --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "aspeed-bmc-facebook-anacapa-evt1.dtsi" + +&sgpiom0 { + gpio-line-names = + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "", "JTAG_CPLD_TRST_R_N", + "", "", + "", "", + "", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "", "", + "", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 5e76076bdcd4..606dacb605c5 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include "aspeed-bmc-facebook-anacapa-evt1.dtsi" +#include "aspeed-bmc-facebook-anacapa-evt2.dtsi" -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 03/15] ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang 2026-09-30 6:10 ` [PATCH v9 01/15] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it Colin Huang 2026-09-30 6:10 ` [PATCH v9 02/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 04/15] ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM Colin Huang ` (11 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang Add a development-phase devicetree for the Facebook Anacapa BMC DVT hardware revision and update the Anacapa wrapper DTS to reference it. Signed-off-by: Colin Huang <u8813345@gmail.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 167 +++++++++++++++++++++ .../dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 2 +- 2 files changed, 168 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi new file mode 100644 index 000000000000..0509bc8bb9cd --- /dev/null +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -0,0 +1,167 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include "aspeed-bmc-facebook-anacapa-evt2.dtsi" + +&sgpiom0 { + gpio-line-names = + /*in - out */ + /* A0-A7 line 0-15 */ + "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N", + "L_BNIC0_FLT", "CPU0_KBRST_N", + "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N", + "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0", + "L_BNIC3_FLT", "Force_I3C_SEL", + "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle", + "", "", + "", "", + + /* B0-B7 line 16-31 */ + "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + + /* C0-C7 line 32-47 */ + "RSVD_RMC_GPIO3", "RTM_MUX_L", + "LEAK_DETECT_RMC_N", "RTM_MUX_R", + "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", + "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", + "R_EAM1_NIC_CBL_PRSNT_L", "", + "L_EAM0_NIC_CBL_PRSNT_L", "", + "L_EAM1_NIC_CBL_PRSNT_L", "", + + /* D0-D7 line 48-63 */ + "Channel0_leakage_present_EAM3", "", + "Channel1_leakage_present_EAM0", "", + "Channel2_leakage_present_Manifold1", "", + "Channel4_leakage_present_Manifold2", "", + "AMC_BRD_PRSNT_CPLD_L", "", + "Channel7_leakage_present_EAM2", "", + "", "", + "", "", + + /* E0-E7 line 64-79 */ + "L_PRSNT_B_FENIC_R2_N", "", + "L_PRSNT_B_BENIC0_R2_N", "", + "L_PRSNT_B_BENIC1_R2_N", "", + "L_PRSNT_B_BENIC2_R2_N", "", + "L_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* F0-F7 line 80-95 */ + "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY", + "R_PRSNT_B_BENIC0_R2_N", "", + "R_PRSNT_B_BENIC1_R2_N", "", + "R_PRSNT_B_BENIC2_R2_N", "", + "R_PRSNT_B_BENIC3_R2_N", "", + "", "", + "", "", + "", "", + + /* G0-G7 line 96-111 */ + "L_PRSNT_EDSFF0_N", "", + "L_PRSNT_EDSFF1_N", "", + "R_PRSNT_EDSFF2_N", "", + "R_PRSNT_EDSFF3_N", "", + "HPM_EDSFF_PG", "", + "", "", + "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", + "PRSNT_NFC_BOARD_R", "", + + /* H0-H7 line 112-127 */ + "R_FNIC_FLT", "", + "R_BNIC0_FLT", "", + "R_BNIC1_FLT", "", + "R_BNIC2_FLT", "", + "R_BNIC3_FLT", "", + "R_RTM_SW_FLT", "", + "RBB_Cable_Present", "", + "LBB_Cable_Present", "", + + /* I0-I7 line 128-143 */ + "EAM0_BRD_PRSNT_R_L", "", + "EAM1_BRD_PRSNT_R_L", "", + "EAM2_BRD_PRSNT_R_L", "", + "EAM3_BRD_PRSNT_R_L", "", + "FM_TPM_PRSNT_R_N", "", + "PDB_L_PRSNT_R_N", "", + "PRSNT_EDSFF_BOOT_N", "", + "PRSNT_CPU0_N", "", + + /* J0-J7 line 144-159 */ + "PRSNT_L_BRIDGE_R", "", + "PRSNT_R_BRIDGE_R", "", + "BRIDGE_L_MAIN_PG_R", "", + "BRIDGE_R_MAIN_PG_R", "", + "BRIDGE_L_STBY_PG_R", "", + "BRIDGE_R_STBY_PG_R", "", + "IRQ_NFC_BOARD_R", "", + "RSMRST_N", "", + + /* K0-K7 line 160-175 */ + "ADC_I2C_ALERT_N", "", + "TEMP_I2C_ALERT_R_L", "", + "CPU0_VR_SMB_ALERT_CPLD_N", "", + "COVER_INTRUDER_R_N", "", + "HANDLE_INTRUDER_CPLD_N", "", + "IRQ_MCIO_CPLD_WAKE_R_N", "", + "APML_CPU0_ALERT_R_N", "", + "PDB_ALERT_R_N", "", + + /* L0-L7 line 176-191 */ + "L_EDSFF0_PG", "", + "L_EDSFF1_PG", "", + "R_EDSFF2_PG", "", + "R_EDSFF3_PG", "", + "HPM_CPLD_HEART_BIT", "", + "RBB_CPLD_HEART_BIT", "", + "LBB_CPLD_HEART_BIT", "", + "FM_BIOS_POST_CMPLT_R_N", "", + + /* M0-M7 line 192-207 */ + "EAM0_SMERR_CPLD_R_L", "", + "EAM1_SMERR_CPLD_R_L", "", + "EAM2_SMERR_CPLD_R_L", "", + "EAM3_SMERR_CPLD_R_L", "", + "CPU0_SMERR_N_R", "", + "CPU0_NV_SAVE_N_R", "", + "PDB_PWR_LOSS_CPLD_N", "", + "IRQ_BMC_SMI_ACTIVE_R_N", "", + + /* N0-N7 line 208-223 */ + "AMCROT_BMC_S5_RDY_R", "", + "AMC_RDY_R", "", + "AMC_STBY_PGOOD_R", "", + "CPU_AMC_SLP_S5_R_L", "", + "AMC_CPU_EAMPG_R", "", + "DIMM_PMIC_PG_TIMEOUT", "", + "EAM_MOD_PWR_GD_TIMEOUT", "", + "CPLD_AMC_STBY_PWR_EN", "", + + /* O0-O7 line 224-239 */ + "HPM_PWR_FAIL", "Port80_b0", + "FM_DIMM_IP_FAIL", "Port80_b1", + "FM_DIMM_AH_FAIL", "Port80_b2", + "AMC_THERMTRIP_ASSERT", "Port80_b3", + "CPU_THERMTRIP_ASSERT", "Port80_b4", + "PVDDCR_SOC_P0_OCP_L", "Port80_b5", + "CPLD_SGPIO_RDY", "Port80_b6", + "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7", + + /* P0-P7 line 240-255 */ + "CPU0_SLP_S5_N_R", "NFC_VEN", + "CPU0_SLP_S3_N_R", "", + "FM_CPU0_PWRGD", "", + "PWRGD_RMC", "", + "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST", + "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST", + "AMC_FAIL", "HPM_CPLD_RISCV_RST", + "S0_ON", ""; +}; diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts index 606dacb605c5..1eee0d84c0a8 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts @@ -1,4 +1,4 @@ // SPDX-License-Identifier: GPL-2.0-or-later /dts-v1/; -#include "aspeed-bmc-facebook-anacapa-evt2.dtsi" +#include "aspeed-bmc-facebook-anacapa-dvt.dtsi" -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 04/15] ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (2 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 03/15] ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2 Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 05/15] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Colin Huang ` (10 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang The SCM FRU EEPROM I2C address differs between SCM revisions: - Rev B uses address 0x50 - Rev C/D/E/F and later use address 0x51 Add an additional AT24C128 EEPROM node at 0x51 on i2c9 so the same device tree can support multiple SCM revisions. Signed-off-by: Colin Huang <u8813345@gmail.com> --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index c43090618c4a..8c4a03a82d44 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -2,6 +2,20 @@ #include "aspeed-bmc-facebook-anacapa-evt1.dtsi" +// SCM +&i2c9 { + // SCM FRU + // | DC-SCM Rev | Slave address of eeprom | + // |-------------------|--------------------------| + // | Rev B | 0x50 | + // | Rev C/D/E/F/above | 0x51 | + + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; +}; + &sgpiom0 { gpio-line-names = /*in - out */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 05/15] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (3 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 04/15] ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 06/15] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Colin Huang ` (9 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Carl Lee From: Carl Lee <carl.lee@amd.com> Add eeprom device node for NFC adaptor board FRU. Signed-off-by: Carl Lee <carl.lee@amd.com> --- .../boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 8c4a03a82d44..a2392f684b80 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -16,6 +16,19 @@ eeprom@51 { }; }; +// MB +&i2c13 { + i2c-mux@70 { + i2c@7 { + // NFC adaptor board FRU + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + }; + }; + }; +}; + &sgpiom0 { gpio-line-names = /*in - out */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 06/15] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (4 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 05/15] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 07/15] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Colin Huang ` (8 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Rex Fu From: Rex Fu <rex.fu.amd@gmail.com> Update the LPDB and RPDB fan GPIO line names to align with the platform fan numbering scheme. The LPDB fan GPIOs are named FAN0 through FAN4, while the RPDB fan GPIOs are named FAN5 through FAN8. This keeps the GPIO line names consistent with the fan inventory and platform-level fan numbering. Signed-off-by: Rex Fu <rex.fu.amd@gmail.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index a2392f684b80..3ea5d67865d4 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -2,6 +2,40 @@ #include "aspeed-bmc-facebook-anacapa-evt1.dtsi" +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@24 { + gpio-line-names = + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + }; + + i2c@1 { + gpio@24 { + gpio-line-names = + "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG","LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG","LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R","LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R","LPDB_FAN4_PRSNT_N_R", + "","", + "","", + "",""; + }; + }; + }; +}; + // SCM &i2c9 { // SCM FRU -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 07/15] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (5 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 06/15] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 08/15] ARM: dts: aspeed: anacapa: evt2: Add shunt resistor values for HSC monitors Colin Huang ` (7 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Andy Chung From: Andy Chung <Andy.Chung@amd.com> Add the mctp-controller property to enable frontend NIC management via PLDM over MCTP. Also add EEPROM device for NIC FRU and reorder the I2C virtual bus index accroding to the system silkscreen index. Signed-off-by: Andy Chung <Andy.Chung@amd.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 137 +++++++++++++++++++++ 1 file changed, 137 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 3ea5d67865d4..ab16e5ad5871 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -2,6 +2,25 @@ #include "aspeed-bmc-facebook-anacapa-evt1.dtsi" +&{/aliases} { + i2c36 = &i2c11mux0ch5; + i2c37 = &i2c11mux0ch6; + i2c38 = &i2c11mux0ch7; + i2c39 = &i2c11mux0ch0; + i2c40 = &i2c11mux0ch1; + i2c41 = &i2c11mux0ch2; + i2c42 = &i2c11mux0ch3; + i2c43 = &i2c11mux0ch4; + i2c44 = &i2c10mux0ch1; + i2c45 = &i2c10mux0ch2; + i2c46 = &i2c10mux0ch3; + i2c47 = &i2c10mux0ch4; + i2c48 = &i2c10mux0ch5; + i2c49 = &i2c10mux0ch6; + i2c50 = &i2c10mux0ch7; + i2c51 = &i2c10mux0ch0; +}; + // MB - PDB &i2c8 { i2c-mux@72 { @@ -50,6 +69,124 @@ eeprom@51 { }; }; +// R Bridge Board +&i2c10 { + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c10mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c10mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c10mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c10mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + }; +}; + +// L Bridge Board +&i2c11 { + multi-master; + + mctp@10 { + compatible = "mctp-i2c-controller"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + }; + + i2c-mux@71 { + /delete-property/ i2c-mux-idle-disconnect; + + i2c11mux0ch0: i2c@0 { + mctp-controller; + // FE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch1: i2c@1 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch2: i2c@2 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch3: i2c@3 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + + i2c11mux0ch4: i2c@4 { + mctp-controller; + // BE NIC FRU + + eeprom@50 { + compatible = "atmel,24c32"; + reg = <0x50>; + }; + }; + }; +}; + // MB &i2c13 { i2c-mux@70 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 08/15] ARM: dts: aspeed: anacapa: evt2: Add shunt resistor values for HSC monitors 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (6 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 07/15] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 09/15] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Colin Huang ` (6 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Peter Shen From: Peter Shen <peter.shen@amd.com> Add shunt resistor configuration for LTC4287 hot-swap controllers on Anacapa EVT2 platform. The resistor values are required for accurate current and power measurement by the driver. These settings reflect the actual BOM used on EVT2, where different sense resistor values (150 uOhm and 250 uOhm) are populated across rails. Without this configuration, the reported readings would be incorrect. Signed-off-by: Peter Shen <peter.shen@amd.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index ab16e5ad5871..5f849bd21fe0 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -37,6 +37,30 @@ gpio@24 { "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", "", ""; }; + + power-monitor@42 { + compatible = "lltc,ltc4287"; + reg = <0x42>; + shunt-resistor-micro-ohms = <150>; + }; + + power-monitor@43 { + compatible = "lltc,ltc4287"; + reg = <0x43>; + shunt-resistor-micro-ohms = <150>; + }; + + power-monitor@44 { + compatible = "lltc,ltc4287"; + reg = <0x44>; + shunt-resistor-micro-ohms = <250>; + }; + + power-monitor@45 { + compatible = "lltc,ltc4287"; + reg = <0x45>; + shunt-resistor-micro-ohms = <250>; + }; }; i2c@1 { @@ -51,6 +75,24 @@ gpio@24 { "","", "",""; }; + + power-monitor@40 { + compatible = "lltc,ltc4287"; + reg = <0x40>; + shunt-resistor-micro-ohms = <150>; + }; + + power-monitor@41 { + compatible = "lltc,ltc4287"; + reg = <0x41>; + shunt-resistor-micro-ohms = <150>; + }; + + power-monitor@45 { + compatible = "lltc,ltc4287"; + reg = <0x45>; + shunt-resistor-micro-ohms = <250>; + }; }; }; }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 09/15] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (7 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 08/15] ARM: dts: aspeed: anacapa: evt2: Add shunt resistor values for HSC monitors Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 10/15] ARM: dts: aspeed: anacapa: Simplify leakage GPIO line names Colin Huang ` (5 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Rex Fu From: Rex Fu <rex.fu.amd@gmail.com> Add PCA9554 GPIO expanders for PDB fuse monitor signals on the Anacapa DVT board. The patch adds GPIO expander definitions for both the left and right PDBs under the i2c8 multiplexer and updates the associated gpio-line-names to reflect the final signal assignments. Signed-off-by: Rex Fu <rex.fu.amd@gmail.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 92 ++++++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 0509bc8bb9cd..2fd7e46daa63 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -2,6 +2,98 @@ #include "aspeed-bmc-facebook-anacapa-evt2.dtsi" +// MB - PDB +&i2c8 { + i2c-mux@72 { + i2c@0 { + gpio@22 { + gpio-line-names = + "RPDB_FAN_FULL_SPEED_R_N", "RPDB_I2C_TMP432_U8_ALERT_R_N", + "RPDB_I2C_TMP432_U29_ALERT_R_N", "RPDB_GLOBAL_WP", + "RPDB_FAN_CT_FAN_FAIL_R_N", "RPDB_VERID_A0", + "RPDB_VERID_A1", "RPDB_VERID_A2", + "RPDB_ALERT_P50V_HSC2_R_N", "RPDB_ALERT_P50V_HSC3_R_N", + "RPDB_ALERT_P50V_HSC4_R_N", "RPDB_ALERT_P50V_STBY_R_N", + "RPDB_P12V_MB_VRM_ALERT_R_N", + "RPDB_P12V_STBY_VRM_ALERT_R_N", + "RPDB_PGD_P3V3_STBY_PWRGD_R", + "RPDB_P12V_STBY_VRM_PWRGD_BUF_R"; + }; + + gpio@24 { + gpio-line-names = + "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", + "RPDB_PWRGD_P50V_HSC4_SYS_R", + "RPDB_PWRGD_P50V_STBY_SYS_BUF_R", + "RPDB_P50V_FAN5_R2_PG", "RPDB_P50V_FAN6_R2_PG", + "RPDB_P50V_FAN7_R2_PG", "RPDB_P50V_FAN8_R2_PG", + "RPDB_SKU_ID0", "RPDB_FAN5_PRSNT_N_R", + "", "RPDB_FAN6_PRSNT_N_R", + "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", + "", ""; + }; + + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "RPDB_P50V_FUSE2_TVS1", "RPDB_P50V_FUSE2_TVS2", + "RPDB_P50V_FUSE3_TVS1", "RPDB_P50V_FUSE3_TVS2", + "RPDB_P50V_FUSE4_TVS1", "", + "", ""; + + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + i2c@1 { + gpio@22 { + gpio-line-names = + "LPDB_FAN_FULL_SPEED_R_N", "LPDB_I2C_TEMP75_U8_ALERT_R_N", + "LPDB_I2C_TMP432_U29_ALERT_R_N", "LPDB_GLOBAL_WP", + "LPDB_FAN_CT_FAN_FAIL_R_N", "LPDB_VERID_A0", + "LPDB_VERID_A1", "LPDB_VERID_A2", + "LPDB_ALERT_P50V_HSC0_R_N", "LPDB_ALERT_P50V_HSC1_R_N", + "LPDB_ALERT_P50V_HSC5_R_N", "LPDB_I2C_P12V_SW_VRM_ALERT_R_N", + "LPDB_EAM0_PRSNT_MOS_N_R", "LPDB_EAM1_PRSNT_MOS_N_R", + "LPDB_PWRGD_P50V_HSC5_SYS_R", "BARKLIP_PRSNT_N_R3"; + }; + + gpio@24 { + gpio-line-names = + "LPDB_P50V_FAN0_R2_PG", "LPDB_P50V_FAN1_R2_PG", + "LPDB_P50V_FAN2_R2_PG", "LPDB_P50V_FAN3_R2_PG", + "LPDB_P50V_FAN4_R2_PG", "LPDB_FAN0_PRSNT_N_R", + "LPDB_FAN1_PRSNT_N_R", "LPDB_FAN2_PRSNT_N_R", + "LPDB_FAN3_PRSNT_N_R", "LPDB_FAN4_PRSNT_N_R", + "LPDB_SKU_ID0", "", + "", "", + "", "LPDB_PG_P3V3_R"; + }; + + gpio@38 { + compatible = "nxp,pca9554"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + + gpio-line-names = + "LPDB_P50V_FUSE0_TVS1", "LPDB_P50V_FUSE0_TVS2", + "LPDB_P50V_FUSE1_TVS1", "LPDB_P50V_FUSE1_TVS2", + "LPDB_P50V_FUSE5_TVS1", "", + "", ""; + + interrupt-parent = <&sgpiom0>; + interrupts = <174 IRQ_TYPE_LEVEL_LOW>; + }; + }; + }; +}; + &sgpiom0 { gpio-line-names = /*in - out */ -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 10/15] ARM: dts: aspeed: anacapa: Simplify leakage GPIO line names 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (8 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 09/15] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 11/15] ARM: dts: aspeed: anacapa: Add SPI flash VCC supply Colin Huang ` (4 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Rex Fu From: Rex Fu <rex.fu.amd@gmail.com> Remove the board location suffixes from the leakage present GPIO line names. The channel number is enough to identify each leakage present signal. Signed-off-by: Rex Fu <rex.fu.amd@gmail.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 28 +++++++++++----------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 2fd7e46daa63..3b3967b47980 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -108,32 +108,32 @@ &sgpiom0 { "", "", /* B0-B7 line 16-31 */ - "Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL", - "Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL", - "Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL", - "Channel5_leakage_present_EAM1", "FM_CPU0_NMI_SYNC_FLOOD_N", - "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L", - "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L", - "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330", - "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331", + "Channel0_leakage", "FM_CPU_FPGA_JTAG_MUX_SEL", + "Channel1_leakage", "FM_SCM_JTAG_MUX_SEL", + "Channel2_leakage", "FM_BRIDGE_JTAG_MUX_SEL", + "Channel5_leakage_present", "FM_CPU0_NMI_SYNC_FLOOD_N", + "Channel4_leakage", "BMC_AINIC0_WP_R2_L", + "Channel5_leakage", "BMC_AINIC1_WP_R2_L", + "Channel6_leakage", "CPLD_BUF_R_AGPIO330", + "Channel7_leakage", "CPLD_BUF_R_AGPIO331", /* C0-C7 line 32-47 */ "RSVD_RMC_GPIO3", "RTM_MUX_L", "LEAK_DETECT_RMC_N", "RTM_MUX_R", "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N", - "Channel6_leakage_present_CPU_DIMM", "whdt_sel", + "Channel6_leakage_present", "whdt_sel", "R_EAM0_NIC_CBL_PRSNT_L", "JTAG_CPLD_TRST_R_N", "R_EAM1_NIC_CBL_PRSNT_L", "", "L_EAM0_NIC_CBL_PRSNT_L", "", "L_EAM1_NIC_CBL_PRSNT_L", "", /* D0-D7 line 48-63 */ - "Channel0_leakage_present_EAM3", "", - "Channel1_leakage_present_EAM0", "", - "Channel2_leakage_present_Manifold1", "", - "Channel4_leakage_present_Manifold2", "", + "Channel0_leakage_present", "", + "Channel1_leakage_present", "", + "Channel2_leakage_present", "", + "Channel4_leakage_present", "", "AMC_BRD_PRSNT_CPLD_L", "", - "Channel7_leakage_present_EAM2", "", + "Channel7_leakage_present", "", "", "", "", "", -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 11/15] ARM: dts: aspeed: anacapa: Add SPI flash VCC supply 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (9 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 10/15] ARM: dts: aspeed: anacapa: Simplify leakage GPIO line names Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 12/15] ARM: dts: aspeed: anacapa: Add NCT7363 fan controllers Colin Huang ` (3 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Rex Fu From: Rex Fu <rex.fu.amd@gmail.com> Specify the 3.3 V auxiliary rail as the SPI flash VCC supply to avoid using the dummy regulator during device initialization. Signed-off-by: Rex Fu <rex.fu.amd@gmail.com> Signed-off-by: Colin Huang <u8813345@gmail.com> --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi index 5f9cfeec39cb..e429f7be46db 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi @@ -92,7 +92,7 @@ memory@80000000 { device_type = "memory"; }; - regulator-p3v3-bmc-aux { + p3v3_bmc_aux: regulator-p3v3-bmc-aux { compatible = "regulator-fixed"; regulator-always-on; regulator-max-microvolt = <3300000>; @@ -170,6 +170,7 @@ &fmc { flash@0 { label = "bmc"; spi-max-frequency = <50000000>; + vcc-supply = <&p3v3_bmc_aux>; m25p,fast-read; status = "okay"; @@ -179,6 +180,7 @@ flash@0 { flash@1 { label = "alt-bmc"; spi-max-frequency = <50000000>; + vcc-supply = <&p3v3_bmc_aux>; m25p,fast-read; status = "okay"; @@ -1073,6 +1075,7 @@ flash@0 { spi-max-frequency = <12000000>; spi-rx-bus-width = <2>; spi-tx-bus-width = <2>; + vcc-supply = <&p3v3_bmc_aux>; status = "okay"; }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 12/15] ARM: dts: aspeed: anacapa: Add NCT7363 fan controllers 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (10 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 11/15] ARM: dts: aspeed: anacapa: Add SPI flash VCC supply Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 13/15] ARM: dts: aspeed: anacapa: Remove LTC4287 power monitors Colin Huang ` (2 subsequent siblings) 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Carl Lee From: Carl Lee <carl.lee@amd.com> Add two NCT7363 fan-controller nodes on Anacapa I2C mux channels and define their PWM/tach channel mappings. This matches the fan-control hardware layout and allows the kernel to probe the correct fan-controller devices. Signed-off-by: Carl Lee <carl.lee@amd.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 102 +++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 5f849bd21fe0..f546a7b5786a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -25,6 +25,52 @@ &i2c8 { i2c-mux@72 { i2c@0 { + fanctl1: fan-controller@21 { + compatible = "nuvoton,nct7363"; + reg = <0x21>; + #pwm-cells = <2>; + + fan-0 { + pwms = <&fanctl1 6 40000>; + tach-ch = /bits/ 8 <0x00>; + }; + + fan-2 { + pwms = <&fanctl1 9 40000>; + tach-ch = /bits/ 8 <0x02>; + }; + + fan-3 { + pwms = <&fanctl1 9 40000>; + tach-ch = /bits/ 8 <0x03>; + }; + + fan-5 { + pwms = <&fanctl1 12 40000>; + tach-ch = /bits/ 8 <0x05>; + }; + + fan-6 { + pwms = <&fanctl1 12 40000>; + tach-ch = /bits/ 8 <0x06>; + }; + + fan-9 { + pwms = <&fanctl1 0 40000>; + tach-ch = /bits/ 8 <0x09>; + }; + + fan-10 { + pwms = <&fanctl1 0 40000>; + tach-ch = /bits/ 8 <0x0a>; + }; + + fan-15 { + pwms = <&fanctl1 6 40000>; + tach-ch = /bits/ 8 <0x0f>; + }; + }; + gpio@24 { gpio-line-names = "RPDB_EAM2_PRSNT_MOS_N_R", "RPDB_EAM3_PRSNT_MOS_N_R", @@ -64,6 +110,62 @@ power-monitor@45 { }; i2c@1 { + fanctl0: fan-controller@23 { + compatible = "nuvoton,nct7363"; + reg = <0x23>; + #pwm-cells = <2>; + + fan-0 { + pwms = <&fanctl0 6 40000>; + tach-ch = /bits/ 8 <0x00>; + }; + + fan-2 { + pwms = <&fanctl0 9 40000>; + tach-ch = /bits/ 8 <0x02>; + }; + + fan-3 { + pwms = <&fanctl0 9 40000>; + tach-ch = /bits/ 8 <0x03>; + }; + + fan-5 { + pwms = <&fanctl0 12 40000>; + tach-ch = /bits/ 8 <0x05>; + }; + + fan-6 { + pwms = <&fanctl0 12 40000>; + tach-ch = /bits/ 8 <0x06>; + }; + + fan-9 { + pwms = <&fanctl0 0 40000>; + tach-ch = /bits/ 8 <0x09>; + }; + + fan-10 { + pwms = <&fanctl0 0 40000>; + tach-ch = /bits/ 8 <0x0a>; + }; + + fan-12 { + pwms = <&fanctl0 3 40000>; + tach-ch = /bits/ 8 <0x0c>; + }; + + fan-13 { + pwms = <&fanctl0 3 40000>; + tach-ch = /bits/ 8 <0x0d>; + }; + + fan-15 { + pwms = <&fanctl0 6 40000>; + tach-ch = /bits/ 8 <0x0f>; + }; + }; + gpio@24 { gpio-line-names = "LPDB_P50V_FAN0_R2_PG","LPDB_P50V_FAN1_R2_PG", -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 13/15] ARM: dts: aspeed: anacapa: Remove LTC4287 power monitors 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (11 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 12/15] ARM: dts: aspeed: anacapa: Add NCT7363 fan controllers Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 14/15] ARM: dts: aspeed: anacapa: Update EDSFF power status signals Colin Huang 2026-09-30 6:10 ` [PATCH v9 15/15] ARM: dts: aspeed: anacapa: Add E1.S FRU EEPROMs Colin Huang 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Carl Lee From: Carl Lee <carl.lee@amd.com> The LTC4287 power-monitor nodes in the Anacapa DTS overlap I2C addresses used by other devices on the same buses. Keeping these nodes may cause incorrect probing/binding attempts. Remove them to avoid address conflicts. Signed-off-by: Carl Lee <carl.lee@amd.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 42 ---------------------- 1 file changed, 42 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index f546a7b5786a..5c0d874fa24a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -83,30 +83,6 @@ gpio@24 { "RPDB_FAN7_PRSNT_N_R", "RPDB_FAN8_PRSNT_N_R", "", ""; }; - - power-monitor@42 { - compatible = "lltc,ltc4287"; - reg = <0x42>; - shunt-resistor-micro-ohms = <150>; - }; - - power-monitor@43 { - compatible = "lltc,ltc4287"; - reg = <0x43>; - shunt-resistor-micro-ohms = <150>; - }; - - power-monitor@44 { - compatible = "lltc,ltc4287"; - reg = <0x44>; - shunt-resistor-micro-ohms = <250>; - }; - - power-monitor@45 { - compatible = "lltc,ltc4287"; - reg = <0x45>; - shunt-resistor-micro-ohms = <250>; - }; }; i2c@1 { @@ -177,24 +153,6 @@ gpio@24 { "","", "",""; }; - - power-monitor@40 { - compatible = "lltc,ltc4287"; - reg = <0x40>; - shunt-resistor-micro-ohms = <150>; - }; - - power-monitor@41 { - compatible = "lltc,ltc4287"; - reg = <0x41>; - shunt-resistor-micro-ohms = <150>; - }; - - power-monitor@45 { - compatible = "lltc,ltc4287"; - reg = <0x45>; - shunt-resistor-micro-ohms = <250>; - }; }; }; }; -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 14/15] ARM: dts: aspeed: anacapa: Update EDSFF power status signals 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (12 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 13/15] ARM: dts: aspeed: anacapa: Remove LTC4287 power monitors Colin Huang @ 2026-09-30 6:10 ` Colin Huang 2026-09-30 6:10 ` [PATCH v9 15/15] ARM: dts: aspeed: anacapa: Add E1.S FRU EEPROMs Colin Huang 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang, Rex Fu From: Rex Fu <rex.fu.amd@gmail.com> The CPLD definition for the EDSFF power status signals has changed from PG to FLT. Update the corresponding SGPIO line names to match the CPLD definition. Signed-off-by: Rex Fu <rex.fu.amd@gmail.com> --- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi | 10 +++++----- arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi | 10 +++++----- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi index 3b3967b47980..698308049c38 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-dvt.dtsi @@ -162,7 +162,7 @@ &sgpiom0 { "L_PRSNT_EDSFF1_N", "", "R_PRSNT_EDSFF2_N", "", "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", + "EDSFF_BOOT_FLT", "", "", "", "P12V_PWR_CABLE_PRSNT_L_R", "FM_BMC_READY_PLD", "PRSNT_NFC_BOARD_R", "", @@ -208,10 +208,10 @@ &sgpiom0 { "PDB_ALERT_R_N", "", /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", - "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", - "R_EDSFF3_PG", "", + "L_EDSFF0_FLT", "", + "L_EDSFF1_FLT", "", + "R_EDSFF2_FLT", "", + "R_EDSFF3_FLT", "", "HPM_CPLD_HEART_BIT", "", "RBB_CPLD_HEART_BIT", "", "LBB_CPLD_HEART_BIT", "", diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi index 5c0d874fa24a..766aa26b6cea 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt2.dtsi @@ -370,7 +370,7 @@ &sgpiom0 { "L_PRSNT_EDSFF1_N", "", "R_PRSNT_EDSFF2_N", "", "R_PRSNT_EDSFF3_N", "", - "HPM_EDSFF_PG", "", + "EDSFF_BOOT_FLT", "", "", "", "", "FM_BMC_READY_PLD", "PRSNT_NFC_BOARD_R", "", @@ -416,10 +416,10 @@ &sgpiom0 { "PDB_ALERT_R_N", "", /* L0-L7 line 176-191 */ - "L_EDSFF0_PG", "", - "L_EDSFF1_PG", "", - "R_EDSFF2_PG", "", - "R_EDSFF3_PG", "", + "L_EDSFF0_FLT", "", + "L_EDSFF1_FLT", "", + "R_EDSFF2_FLT", "", + "R_EDSFF3_FLT", "", "HPM_CPLD_HEART_BIT", "", "RBB_CPLD_HEART_BIT", "", "LBB_CPLD_HEART_BIT", "", -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v9 15/15] ARM: dts: aspeed: anacapa: Add E1.S FRU EEPROMs 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang ` (13 preceding siblings ...) 2026-09-30 6:10 ` [PATCH v9 14/15] ARM: dts: aspeed: anacapa: Update EDSFF power status signals Colin Huang @ 2026-09-30 6:10 ` Colin Huang 14 siblings, 0 replies; 16+ messages in thread From: Colin Huang @ 2026-09-30 6:10 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery, Ryan Chen, Billy Tsai Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel, colin.huang2, Colin Huang Add the FRU EEPROM definitions for the E1.S boot drive and the four E1.S NVMe slots on Anacapa EVT1/EVT2 and DVT. Signed-off-by: Colin Huang <u8813345@gmail.com> --- .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi | 35 ++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi index e429f7be46db..cd87ca27e18c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa-evt1.dtsi @@ -404,30 +404,65 @@ i2c4mux0ch0: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; + + // E1S_Boot FRU + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; i2c4mux0ch1: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; + + // E1S_0 FRU + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; i2c4mux0ch2: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; + + // E1S_1 FRU + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; i2c4mux0ch3: i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; + + // E1S_2 FRU + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; i2c4mux0ch4: i2c@4 { reg = <4>; #address-cells = <1>; #size-cells = <0>; + + // E1S_3 FRU + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; }; i2c4mux0ch5: i2c@5 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2026-09-30 6:16 UTC | newest] Thread overview: 16+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2026-09-30 6:10 [PATCH v9 00/15] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase Colin Huang 2026-09-30 6:10 ` [PATCH v9 01/15] ARM: dts: aspeed: anacapa: Add EVT1 devicetree and point wrapper to it Colin Huang 2026-09-30 6:10 ` [PATCH v9 02/15] ARM: dts: aspeed: anacapa: Add EVT2 devicetree inheriting EVT1 Colin Huang 2026-09-30 6:10 ` [PATCH v9 03/15] ARM: dts: aspeed: anacapa: Add DVT devicetree inheriting EVT2 Colin Huang 2026-09-30 6:10 ` [PATCH v9 04/15] ARM: dts: aspeed: anacapa: Add additional EEPROM node for SCM Colin Huang 2026-09-30 6:10 ` [PATCH v9 05/15] ARM: dts: aspeed: anacapa: Add eeprom device node for NFC adaptor board Colin Huang 2026-09-30 6:10 ` [PATCH v9 06/15] ARM: dts: aspeed: anacapa: Align PDB fan GPIO numbering Colin Huang 2026-09-30 6:10 ` [PATCH v9 07/15] ARM: dts: aspeed: anacapa: Enable MCTP and FRU for NIC Colin Huang 2026-09-30 6:10 ` [PATCH v9 08/15] ARM: dts: aspeed: anacapa: evt2: Add shunt resistor values for HSC monitors Colin Huang 2026-09-30 6:10 ` [PATCH v9 09/15] ARM: dts: aspeed: anacapa: Add LPDB fuse monitor GPIO expander Colin Huang 2026-09-30 6:10 ` [PATCH v9 10/15] ARM: dts: aspeed: anacapa: Simplify leakage GPIO line names Colin Huang 2026-09-30 6:10 ` [PATCH v9 11/15] ARM: dts: aspeed: anacapa: Add SPI flash VCC supply Colin Huang 2026-09-30 6:10 ` [PATCH v9 12/15] ARM: dts: aspeed: anacapa: Add NCT7363 fan controllers Colin Huang 2026-09-30 6:10 ` [PATCH v9 13/15] ARM: dts: aspeed: anacapa: Remove LTC4287 power monitors Colin Huang 2026-09-30 6:10 ` [PATCH v9 14/15] ARM: dts: aspeed: anacapa: Update EDSFF power status signals Colin Huang 2026-09-30 6:10 ` [PATCH v9 15/15] ARM: dts: aspeed: anacapa: Add E1.S FRU EEPROMs Colin Huang
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