[PATCH 0/3] drm/panfrost: Enable the GPU timestamp counter on MT8188

[PATCH 0/3] drm/panfrost: Enable the GPU timestamp counter on MT8188

[Michał Kopeć]

On MT8188 the GPU timestamp counter reads zero until a register in the
MFG configuration block routes the SoC system timer to it, and the
setting is lost whenever the GPU power domain is turned off. As a
result, the SYSTEM_TIMESTAMP query and the timestamps written by jobs
are always zero, which breaks timestamp queries in userspace drivers.

This series adds an optional mediatek,mfgcfg phandle to the Mali
binding, uses it in panfrost to set the register on every power-up,
and adds it to the MT8188 GPU node. Without the phandle the driver
behaves as before.

MT8370 shares the GPU node and the MFG block with MT8188, so the
binding allows the phandle there too, but the driver only enables the
quirk on MT8188, where it was tested.

Patch 3 is meant for the MediaTek tree; patches 1 and 2 can go through
drm-misc.

Tested on the Lenovo Chromebook Duet Gen 9 (Ciri, MT8188): the 13 MHz
counter advances by 100 ms over a 100 ms sleep, also after resuming
from deep suspend.

Michał Kopeć (3):
  dt-bindings: gpu: mali-bifrost: Add the MT8188 MFGCFG phandle
  drm/panfrost: Enable the GPU timestamp counter on MT8188
  arm64: dts: mediatek: mt8188: Add the MFGCFG phandle to the GPU

 .../bindings/gpu/arm,mali-bifrost.yaml        | 17 ++++++++
 arch/arm64/boot/dts/mediatek/mt8188.dtsi      |  1 +
 drivers/gpu/drm/panfrost/panfrost_device.h    |  1 +
 drivers/gpu/drm/panfrost/panfrost_drv.c       |  1 +
 drivers/gpu/drm/panfrost/panfrost_gpu.c       | 39 +++++++++++++++++++
 drivers/gpu/drm/panfrost/panfrost_gpu.h       |  1 +
 6 files changed, 60 insertions(+)


base-commit: 70456f05d4b6396b22048c4b8cd3cb98ecf9f9e3
-- 
2.55.0

[PATCH 1/3] dt-bindings: gpu: mali-bifrost: Add the MT8188 MFGCFG phandle

[Michał Kopeć]

On MT8188 the GPU timestamp counter only counts once a register in the
MFG configuration block routes the SoC system timer to it, and the
setting is lost whenever the GPU power domain is turned off. The GPU
driver has to restore it on every power-up, so it needs a reference to
that block.

Add an optional mediatek,mfgcfg phandle. Allow it on MT8370 as well,
which shares the GPU and the MFG block with MT8188 and its GPU node in
mt8188.dtsi. It is optional so that existing devicetrees stay valid;
without it the timestamp counter reads zero, as before.

Signed-off-by: Michał Kopeć <michal@nozomi.space>
---
 .../bindings/gpu/arm,mali-bifrost.yaml          | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
index 9db9f84ad964b..08c1c22a270cb 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
@@ -122,6 +122,12 @@ properties:
   nvmem-cells:
     maxItems: 1
 
+  mediatek,mfgcfg:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the MFG configuration block, which routes the SoC system
+      timer to the GPU timestamp counter.
+
 required:
   - compatible
   - reg
@@ -226,6 +232,17 @@ allOf:
       required:
         - power-domains
         - power-domain-names
+  - if:
+      properties:
+        compatible:
+          not:
+            contains:
+              enum:
+                - mediatek,mt8188-mali
+                - mediatek,mt8370-mali
+    then:
+      properties:
+        mediatek,mfgcfg: false
   - if:
       properties:
         compatible:
-- 
2.55.0

[PATCH 2/3] drm/panfrost: Enable the GPU timestamp counter on MT8188

[Michał Kopeć]

On MediaTek SoCs the GPU timestamp counter is fed by the SoC system timer
only once the TOP_TSVALUEB enable bits are set in the MFGCFG block. The
setting is lost whenever the GPU power domain is turned off.

Without it, GPU_TIMESTAMP reads zero, so the SYSTEM_TIMESTAMP query and
timestamps written by jobs are always zero, which breaks timestamp
queries in userspace drivers.

Look up the MFGCFG block from the mediatek,mfgcfg phandle and set the
bits from the vendor quirk hook, which runs on every power-up, as the
downstream kbase driver does. Without the phandle nothing changes.

Signed-off-by: Michał Kopeć <michal@nozomi.space>
---
 drivers/gpu/drm/panfrost/panfrost_device.h |  1 +
 drivers/gpu/drm/panfrost/panfrost_drv.c    |  1 +
 drivers/gpu/drm/panfrost/panfrost_gpu.c    | 39 ++++++++++++++++++++++
 drivers/gpu/drm/panfrost/panfrost_gpu.h    |  1 +
 4 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index 1fe1554f2652b..0a73939a023c3 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -134,6 +134,7 @@ struct panfrost_device {
 	int mmu_irq;
 
 	void __iomem *iomem;
+	struct regmap *mtk_mfgcfg;
 	struct clk *clock;
 	struct clk *bus_clock;
 	struct clk *bus_ace_clock;
diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
index 70c05210ea846..e811652e2384d 100644
--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
+++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
@@ -1133,6 +1133,7 @@ static const struct panfrost_compatible mediatek_mt8188_data = {
 	.pm_domain_names = mediatek_pm_domains,
 	.pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF),
 	.gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE),
+	.vendor_quirk = panfrost_gpu_mt8188_quirk,
 };
 
 static const struct panfrost_compatible mediatek_mt8192_data = {
diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c
index 29ac0dce5ff89..971abc9cc222c 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gpu.c
+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c
@@ -9,8 +9,11 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/iopoll.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 
 #include <drm/drm_print.h>
 
@@ -114,6 +117,40 @@ void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev)
 	gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16));
 }
 
+#define MTK_MFG_TIMESTAMP			0x130
+#define   MTK_MFG_TIMESTAMP_TOP_TSVALUEB_EN	0x3
+
+void panfrost_gpu_mt8188_quirk(struct panfrost_device *pfdev)
+{
+	/*
+	 * The GPU timestamp counter only counts once MFGCFG routes the SoC
+	 * system timer to it. The setting is lost whenever the GPU power
+	 * domain is turned off, so it has to be restored on every power-up.
+	 */
+	if (pfdev->mtk_mfgcfg)
+		regmap_write(pfdev->mtk_mfgcfg, MTK_MFG_TIMESTAMP,
+			     MTK_MFG_TIMESTAMP_TOP_TSVALUEB_EN);
+}
+
+static void panfrost_gpu_get_mtk_mfgcfg(struct panfrost_device *pfdev)
+{
+	struct device_node *np;
+	struct regmap *regmap;
+
+	np = of_parse_phandle(pfdev->base.dev->of_node, "mediatek,mfgcfg", 0);
+	if (!np)
+		return;
+
+	regmap = device_node_to_regmap(np);
+	of_node_put(np);
+	if (IS_ERR(regmap)) {
+		dev_warn(pfdev->base.dev, "failed to get MFGCFG: %pe\n", regmap);
+		return;
+	}
+
+	pfdev->mtk_mfgcfg = regmap;
+}
+
 static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev)
 {
 	u32 quirks = 0;
@@ -519,6 +556,8 @@ int panfrost_gpu_init(struct panfrost_device *pfdev)
 {
 	int err;
 
+	panfrost_gpu_get_mtk_mfgcfg(pfdev);
+
 	err = panfrost_gpu_soft_reset(pfdev);
 	if (err)
 		return err;
diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.h b/drivers/gpu/drm/panfrost/panfrost_gpu.h
index b4fef11211d5f..2b974576b96e9 100644
--- a/drivers/gpu/drm/panfrost/panfrost_gpu.h
+++ b/drivers/gpu/drm/panfrost/panfrost_gpu.h
@@ -23,5 +23,6 @@ unsigned long long panfrost_cycle_counter_read(struct panfrost_device *pfdev);
 unsigned long long panfrost_timestamp_read(struct panfrost_device *pfdev);
 
 void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev);
+void panfrost_gpu_mt8188_quirk(struct panfrost_device *pfdev);
 
 #endif
-- 
2.55.0

[PATCH 3/3] arm64: dts: mediatek: mt8188: Add the MFGCFG phandle to the GPU

[Michał Kopeć]

The GPU driver needs the MFG configuration block to enable the GPU
timestamp counter, which otherwise reads zero.

Signed-off-by: Michał Kopeć <michal@nozomi.space>
---
 arch/arm64/boot/dts/mediatek/mt8188.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
index 14a320f0c70cb..b4be89bf55bf7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
@@ -2266,6 +2266,7 @@ gpu: gpu@13000000 {
 				     <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>,
 				     <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>;
 			interrupt-names = "job", "mmu", "gpu";
+			mediatek,mfgcfg = <&mfgcfg>;
 			nvmem-cells = <&gpu_speedbin>;
 			nvmem-cell-names = "speed-bin";
 			operating-points-v2 = <&gpu_opp_table>;
-- 
2.55.0

Re: [PATCH 1/3] dt-bindings: gpu: mali-bifrost: Add the MT8188 MFGCFG phandle

[Krzysztof Kozlowski]

On Sat, Oct 03, 2026 at 10:01:30PM +0200, Michał Kopeć wrote:
> On MT8188 the GPU timestamp counter only counts once a register in the
> MFG configuration block routes the SoC system timer to it, and the
> setting is lost whenever the GPU power domain is turned off. The GPU
> driver has to restore it on every power-up, so it needs a reference to
> that block.

This looks rather like power domain issue, e.g. missing restore of
registers. Otherwise next time there will be one more phandle and then
one more, each for one register being lost during power down.

> 
> Add an optional mediatek,mfgcfg phandle. Allow it on MT8370 as well,
> which shares the GPU and the MFG block with MT8188 and its GPU node in
> mt8188.dtsi. It is optional so that existing devicetrees stay valid;
> without it the timestamp counter reads zero, as before.
> 
> Signed-off-by: Michał Kopeć <michal@nozomi.space>
> ---
>  .../bindings/gpu/arm,mali-bifrost.yaml          | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)

Best regards,
Krzysztof